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soc/intel/cannonlake: Fix PCH-H IRQ constraints 

Cannon Point PCH-H does not implement the eMMC, I2C4 and I2C5 devices.
Guard the IRQ constraints for these devices to prevent FSP assertions.

Tested on Prodrive Hermes, debug FSP builds no longer fail to boot.

Change-Id: I58674d1c3c5fe4535c022020674d48d6a5315bf9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Angel Pons 2021-08-23 13:21:31 +02:00 committed by Felix Held
parent 111bc431ce
commit 5d805f64f9
1 changed files with 6 additions and 0 deletions
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6
src/soc/intel/cannonlake/fsp_params.c
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@ -74,7 +74,9 @@ static const struct slot_irq_constraints irq_constraints[] = {
.slot = PCH_DEV_SLOT_THERMAL,
.fns = {
ANY_PIRQ(PCH_DEVFN_THERMAL),
#if !CONFIG(SOC_INTEL_CANNONLAKE_PCH_H)
ANY_PIRQ(PCH_DEVFN_UFS),
#endif
DIRECT_IRQ(PCH_DEVFN_GSPI2),
},
},
@ -122,17 +124,21 @@ static const struct slot_irq_constraints irq_constraints[] = {
{
.slot = PCH_DEV_SLOT_SIO2,
.fns = {
#if !CONFIG(SOC_INTEL_CANNONLAKE_PCH_H)
DIRECT_IRQ(PCH_DEVFN_I2C4),
DIRECT_IRQ(PCH_DEVFN_I2C5),
#endif
DIRECT_IRQ(PCH_DEVFN_UART2),
},
},
#if !CONFIG(SOC_INTEL_CANNONLAKE_PCH_H)
{
.slot = PCH_DEV_SLOT_STORAGE,
.fns = {
ANY_PIRQ(PCH_DEVFN_EMMC),
},
},
#endif
#if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H)
{
.slot = PCH_DEV_SLOT_PCIE_2,