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soc/amd/stoneyridge: Rename AcpiMmio blocks 

A subsequent patch will move the AcpiMmio support into amd/common.
Take this opportunity to rename the blocks in the 0xfed8xxxx region
with more consistency.

Change-Id: I9a69a6ecfc10f78b4860df05a77a061d2fc8be7d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Marshall Dawson 2019-05-01 16:14:42 -06:00 committed by Martin Roth
parent fe80bf2fd1
commit 5de4771360
10 changed files with 75 additions and 63 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/mainboard/google/kahlee/mainboard.c
View File

@ -145,13 +145,13 @@ static void mainboard_init(void *chip_info)
pm_write8(PM_PCIB_CFG, pm_read8(PM_PCIB_CFG) | PM_GENINT_DISABLE);
/* Set low-power mode for BayHub eMMC bridge's PCIe clock. */
clrsetbits_le32((uint32_t *)(MISC_MMIO_BASE + GPP_CLK_CNTRL),
clrsetbits_le32((uint32_t *)(ACPIMMIO_MISC_BASE + GPP_CLK_CNTRL),
GPP_CLK2_REQ_MAP_MASK,
GPP_CLK2_REQ_MAP_CLK_REQ2 <<
GPP_CLK2_REQ_MAP_SHIFT);
/* Same for the WiFi */
clrsetbits_le32((uint32_t *)(MISC_MMIO_BASE + GPP_CLK_CNTRL),
clrsetbits_le32((uint32_t *)(ACPIMMIO_MISC_BASE + GPP_CLK_CNTRL),
GPP_CLK0_REQ_MAP_MASK,
GPP_CLK0_REQ_MAP_CLK_REQ0 <<
GPP_CLK0_REQ_MAP_SHIFT);

2
src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl
View File

@ -35,7 +35,7 @@ Device (I2S)
Name (RBUF, ResourceTemplate () {
// Memory resource is for MISC FCH register set.
// It is needed for enabling the clock.
Memory32Fixed(ReadWrite, MISC_MMIO_BASE, 0x100)
Memory32Fixed(ReadWrite, ACPIMMIO_MISC_BASE, 0x100)
})
Return (RBUF)

2
src/soc/amd/stoneyridge/acpi/gpio_lib.asl
View File

@ -19,7 +19,7 @@
Method (GPAD, 0x1)
{
/* Arg0 - GPIO pin number */
Return (Add(Multiply(Arg0, 4), GPIO_CONTROL_MMIO_BASE))
Return (Add(Multiply(Arg0, 4), ACPIMMIO_GPIO0_BASE))
}
/* Read pin control dword */

2
src/soc/amd/stoneyridge/acpi/sb_fch.asl
View File

@ -144,7 +144,7 @@ Device (MISC)
Name (_HID, "AMD0040")
Name (_UID, 0x3)
Name (_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, MISC_MMIO_BASE, 0x100)
Memory32Fixed(ReadWrite, ACPIMMIO_MISC_BASE, 0x100)
})
Method (_STA, 0x0, NotSerialized)
{

14
src/soc/amd/stoneyridge/gpio.c
View File

@ -228,7 +228,7 @@ void sb_program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size)
uint8_t mux, index, gpio;
int gevent_num;
inter_master = (uint32_t *)(uintptr_t)(GPIO_CONTROL_MMIO_BASE
inter_master = (uint32_t *)(uintptr_t)(ACPIMMIO_GPIO0_BASE
+ GPIO_MASTER_SWITCH);
direction = 0;
edge_level = 0;
@ -252,7 +252,7 @@ void sb_program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size)
control = gpio_list_ptr[index].control;
control_flags = gpio_list_ptr[index].flags;
mux_ptr = (uint8_t *)(uintptr_t)(gpio + GPIO_IOMUX_MMIO_BASE);
mux_ptr = (uint8_t *)(uintptr_t)(gpio + ACPIMMIO_IOMUX_BASE);
write8(mux_ptr, mux & AMD_GPIO_MUX_MASK);
read8(mux_ptr); /* Flush posted write */
/* special case if pin 2 is assigned to wake */
@ -316,11 +316,13 @@ void sb_program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size)
mem_read_write32(inter_master, GPIO_INTERRUPT_EN, GPIO_INTERRUPT_EN);
/* Set all SCI trigger direction (high/low) */
mem_read_write32((uint32_t *)(uintptr_t)(APU_SMI_BASE + SMI_SCI_TRIG),
mem_read_write32((uint32_t *)
(uintptr_t)(ACPIMMIO_SMI_BASE + SMI_SCI_TRIG),
direction, mask);
/* Set all SCI trigger level (edge/level) */
mem_read_write32((uint32_t *)(uintptr_t)(APU_SMI_BASE + SMI_SCI_LEVEL),
mem_read_write32((uint32_t *)
(uintptr_t)(ACPIMMIO_SMI_BASE + SMI_SCI_LEVEL),
edge_level, mask);
}
@ -348,7 +350,7 @@ static void save_i2c_pin_registers(uint8_t gpio,
uint32_t *gpio_ptr;
uint8_t *mux_ptr;
mux_ptr = (uint8_t *)(uintptr_t)(gpio + GPIO_IOMUX_MMIO_BASE);
mux_ptr = (uint8_t *)(uintptr_t)(gpio + ACPIMMIO_IOMUX_BASE);
gpio_ptr = (uint32_t *)gpio_get_address(gpio);
save_table->mux_value = read8(mux_ptr);
save_table->control_value = read32(gpio_ptr);
@ -360,7 +362,7 @@ static void restore_i2c_pin_registers(uint8_t gpio,
uint32_t *gpio_ptr;
uint8_t *mux_ptr;
mux_ptr = (uint8_t *)(uintptr_t)(gpio + GPIO_IOMUX_MMIO_BASE);
mux_ptr = (uint8_t *)(uintptr_t)(gpio + ACPIMMIO_IOMUX_BASE);
gpio_ptr = (uint32_t *)gpio_get_address(gpio);
write8(mux_ptr, save_table->mux_value);
read8(mux_ptr);

34
src/soc/amd/stoneyridge/include/soc/iomap.h
View File

@ -32,19 +32,29 @@
#endif
#define HPET_BASE_ADDRESS 0xfed00000
/* Register blocks at fixed offsets from FED8_0000h and enabled in PMx04[1] */
/* AcpiMmio blocks are at fixed offsets from FED8_0000h, enabled in PMx04[1] */
#define AMD_SB_ACPI_MMIO_ADDR 0xfed80000
#define APU_SMI_BASE 0xfed80200
#define PM_MMIO_BASE 0xfed80300
#define BIOSRAM_MMIO_BASE 0xfed80500
#define ACPI_REG_MMIO_BASE 0xfed80800
#define ASF_MMIO_BASE 0xfed80900
#define SMBUS_MMIO_BASE 0xfed80a00
#define GPIO_IOMUX_MMIO_BASE 0xfed80d00
#define MISC_MMIO_BASE 0xfed80e00
#define XHCI_ACPI_PM_MMIO_BASE 0xfed81c00
#define GPIO_CONTROL_MMIO_BASE 0xfed81500
#define AOAC_MMIO_BASE 0xfed81e00
#define ACPIMMIO_SM_PCI_BASE 0xfed80000
#define ACPIMMIO_SMI_BASE 0xfed80200
#define ACPIMMIO_PMIO_BASE 0xfed80300
#define ACPIMMIO_PMIO2_BASE 0xfed80400
#define ACPIMMIO_BIOSRAM_BASE 0xfed80500
#define ACPIMMIO_CMOSRAM_BASE 0xfed80600
#define ACPIMMIO_CMOS_BASE 0xfed80700
#define ACPIMMIO_ACPI_BASE 0xfed80800
#define ACPIMMIO_ASF_BASE 0xfed80900
#define ACPIMMIO_SMBUS_BASE 0xfed80a00
#define ACPIMMIO_WDT_BASE 0xfed80b00
#define ACPIMMIO_HPET_BASE 0xfed80c00
#define ACPIMMIO_IOMUX_BASE 0xfed80d00
#define ACPIMMIO_MISC_BASE 0xfed80e00
#define ACPIMMIO_DPVGA_BASE 0xfed81400
#define ACPIMMIO_GPIO0_BASE 0xfed81500
#define ACPIMMIO_GPIO1_BASE 0xfed81600
#define ACPIMMIO_GPIO2_BASE 0xfed81700
#define ACPIMMIO_XHCIPM_BASE 0xfed81c00
#define ACPIMMIO_ACDCTMR_BASE 0xfed81d00
#define ACPIMMIO_AOAC_BASE 0xfed81e00
#define APU_UART0_BASE 0xfedc6000
#define APU_UART1_BASE 0xfedc8000

56
src/soc/amd/stoneyridge/sb_util.c
View File

@ -20,112 +20,112 @@
void pm_write8(u8 reg, u8 value)
{
write8((void *)(PM_MMIO_BASE + reg), value);
write8((void *)(ACPIMMIO_PMIO_BASE + reg), value);
}
u8 pm_read8(u8 reg)
{
return read8((void *)(PM_MMIO_BASE + reg));
return read8((void *)(ACPIMMIO_PMIO_BASE + reg));
}
void pm_write16(u8 reg, u16 value)
{
write16((void *)(PM_MMIO_BASE + reg), value);
write16((void *)(ACPIMMIO_PMIO_BASE + reg), value);
}
u16 pm_read16(u8 reg)
{
return read16((void *)(PM_MMIO_BASE + reg));
return read16((void *)(ACPIMMIO_PMIO_BASE + reg));
}
void misc_write32(u8 reg, u32 value)
{
write32((void *)(MISC_MMIO_BASE + reg), value);
write32((void *)(ACPIMMIO_MISC_BASE + reg), value);
}
u32 misc_read32(u8 reg)
{
return read32((void *)(MISC_MMIO_BASE + reg));
return read32((void *)(ACPIMMIO_MISC_BASE + reg));
}
void pm_write32(u8 reg, u32 value)
{
write32((void *)(PM_MMIO_BASE + reg), value);
write32((void *)(ACPIMMIO_PMIO_BASE + reg), value);
}
u32 pm_read32(u8 reg)
{
return read32((void *)(PM_MMIO_BASE + reg));
return read32((void *)(ACPIMMIO_PMIO_BASE + reg));
}
u8 acpi_read8(u8 reg)
{
return read8((void *)(ACPI_REG_MMIO_BASE + reg));
return read8((void *)(ACPIMMIO_ACPI_BASE + reg));
}
u16 acpi_read16(u8 reg)
{
return read16((void *)(ACPI_REG_MMIO_BASE + reg));
return read16((void *)(ACPIMMIO_ACPI_BASE + reg));
}
u32 acpi_read32(u8 reg)
{
return read32((void *)(ACPI_REG_MMIO_BASE + reg));
return read32((void *)(ACPIMMIO_ACPI_BASE + reg));
}
void acpi_write8(u8 reg, u8 value)
{
write8((void *)(ACPI_REG_MMIO_BASE + reg), value);
write8((void *)(ACPIMMIO_ACPI_BASE + reg), value);
}
void acpi_write16(u8 reg, u16 value)
{
write16((void *)(ACPI_REG_MMIO_BASE + reg), value);
write16((void *)(ACPIMMIO_ACPI_BASE + reg), value);
}
void acpi_write32(u8 reg, u32 value)
{
write32((void *)(ACPI_REG_MMIO_BASE + reg), value);
write32((void *)(ACPIMMIO_ACPI_BASE + reg), value);
}
void smi_write32(uint8_t offset, uint32_t value)
{
write32((void *)(APU_SMI_BASE + offset), value);
write32((void *)(ACPIMMIO_SMI_BASE + offset), value);
}
uint32_t smi_read32(uint8_t offset)
{
return read32((void *)(APU_SMI_BASE + offset));
return read32((void *)(ACPIMMIO_SMI_BASE + offset));
}
uint16_t smi_read16(uint8_t offset)
{
return read16((void *)(APU_SMI_BASE + offset));
return read16((void *)(ACPIMMIO_SMI_BASE + offset));
}
void smi_write16(uint8_t offset, uint16_t value)
{
write16((void *)(APU_SMI_BASE + offset), value);
write16((void *)(ACPIMMIO_SMI_BASE + offset), value);
}
uint8_t smi_read8(uint8_t offset)
{
return read8((void *)(APU_SMI_BASE + offset));
return read8((void *)(ACPIMMIO_SMI_BASE + offset));
}
void smi_write8(uint8_t offset, uint8_t value)
{
write8((void *)(APU_SMI_BASE + offset), value);
write8((void *)(ACPIMMIO_SMI_BASE + offset), value);
}
uint8_t biosram_read8(uint8_t offset)
{
return read8((void *)(BIOSRAM_MMIO_BASE + offset));
return read8((void *)(ACPIMMIO_BIOSRAM_BASE + offset));
}
void biosram_write8(uint8_t offset, uint8_t value)
{
write8((void *)(BIOSRAM_MMIO_BASE + offset), value);
write8((void *)(ACPIMMIO_BIOSRAM_BASE + offset), value);
}
/* BiosRam may only be accessed a byte at a time */
@ -174,32 +174,32 @@ uint16_t pm_acpi_pm_evt_blk(void)
void xhci_pm_write8(uint8_t reg, uint8_t value)
{
write8((void *)(XHCI_ACPI_PM_MMIO_BASE + reg), value);
write8((void *)(ACPIMMIO_XHCIPM_BASE + reg), value);
}
uint8_t xhci_pm_read8(uint8_t reg)
{
return read8((void *)(XHCI_ACPI_PM_MMIO_BASE + reg));
return read8((void *)(ACPIMMIO_XHCIPM_BASE + reg));
}
void xhci_pm_write16(uint8_t reg, uint16_t value)
{
write16((void *)(XHCI_ACPI_PM_MMIO_BASE + reg), value);
write16((void *)(ACPIMMIO_XHCIPM_BASE + reg), value);
}
uint16_t xhci_pm_read16(uint8_t reg)
{
return read16((void *)(XHCI_ACPI_PM_MMIO_BASE + reg));
return read16((void *)(ACPIMMIO_XHCIPM_BASE + reg));
}
void xhci_pm_write32(uint8_t reg, uint32_t value)
{
write32((void *)(XHCI_ACPI_PM_MMIO_BASE + reg), value);
write32((void *)(ACPIMMIO_XHCIPM_BASE + reg), value);
}
uint32_t xhci_pm_read32(uint8_t reg)
{
return read32((void *)(XHCI_ACPI_PM_MMIO_BASE + reg));
return read32((void *)(ACPIMMIO_XHCIPM_BASE + reg));
}
void smbus_write8(uint32_t mmio, uint8_t reg, uint8_t value)

4
src/soc/amd/stoneyridge/sm.c
View File

@ -42,9 +42,9 @@ static u32 get_sm_mmio(struct device *dev)
pbus = get_pbus_smbus(dev);
res = find_resource(pbus->dev, 0x90);
if (res->base == SMB_BASE_ADDR)
return SMBUS_MMIO_BASE;
return ACPIMMIO_SMBUS_BASE;
return ASF_MMIO_BASE;
return ACPIMMIO_ASF_BASE;
}
static int lsmbus_recv_byte(struct device *dev)

4
src/soc/amd/stoneyridge/smbus_spd.c
View File

@ -46,7 +46,7 @@ static int readspd(uint8_t SmbusSlaveAddress, char *buffer, size_t count)
dev_addr = (SmbusSlaveAddress >> 1);
/* Read the first SPD byte */
error = do_smbus_read_byte(SMBUS_MMIO_BASE, dev_addr, 0);
error = do_smbus_read_byte(ACPIMMIO_SMBUS_BASE, dev_addr, 0);
if (error < 0) {
printk(BIOS_ERR, "-------------SPD READ ERROR-----------\n");
return error;
@ -56,7 +56,7 @@ static int readspd(uint8_t SmbusSlaveAddress, char *buffer, size_t count)
/* Read the remaining SPD bytes using do_smbus_recv_byte for speed */
for (index = 1 ; index < count ; index++) {
error = do_smbus_recv_byte(SMBUS_MMIO_BASE, dev_addr);
error = do_smbus_recv_byte(ACPIMMIO_SMBUS_BASE, dev_addr);
if (error < 0) {
printk(BIOS_ERR, "-------------SPD READ ERROR-----------\n");
return error;

16
src/soc/amd/stoneyridge/southbridge.c
View File

@ -279,7 +279,7 @@ int sb_set_wideio_range(uint16_t start, uint16_t size)
static void power_on_aoac_device(int aoac_device_control_register)
{
uint8_t byte;
uint8_t *register_pointer = (uint8_t *)(uintptr_t)AOAC_MMIO_BASE
uint8_t *register_pointer = (uint8_t *)(uintptr_t)ACPIMMIO_AOAC_BASE
+ aoac_device_control_register;
/* Power on the UART and AMBA devices */
@ -291,7 +291,7 @@ static void power_on_aoac_device(int aoac_device_control_register)
static bool is_aoac_device_enabled(int aoac_device_status_register)
{
uint8_t byte;
byte = read8((uint8_t *)(uintptr_t)AOAC_MMIO_BASE
byte = read8((uint8_t *)(uintptr_t)ACPIMMIO_AOAC_BASE
+ aoac_device_status_register);
byte &= (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_RST_CLK_OK_STATE);
if (byte == (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_RST_CLK_OK_STATE))
@ -393,7 +393,7 @@ static void sb_enable_legacy_io(void)
void sb_clk_output_48Mhz(u32 osc)
{
u32 ctrl;
u32 *misc_clk_cntl_1_ptr = (u32 *)(uintptr_t)(MISC_MMIO_BASE
u32 *misc_clk_cntl_1_ptr = (u32 *)(uintptr_t)(ACPIMMIO_MISC_BASE
+ MISC_CLK_CNTL1);
/*
@ -632,12 +632,12 @@ static void setup_misc(int *reboot)
static void fch_smbus_init(void)
{
pm_write8(SMB_ASF_IO_BASE, SMB_BASE_ADDR >> 8);
smbus_write8(SMBUS_MMIO_BASE, SMBTIMING, SMB_SPEED_400KHZ);
smbus_write8(ACPIMMIO_SMBUS_BASE, SMBTIMING, SMB_SPEED_400KHZ);
/* Clear all SMBUS status bits */
smbus_write8(SMBUS_MMIO_BASE, SMBHSTSTAT, SMBHST_STAT_CLEAR);
smbus_write8(SMBUS_MMIO_BASE, SMBSLVSTAT, SMBSLV_STAT_CLEAR);
smbus_write8(ASF_MMIO_BASE, SMBHSTSTAT, SMBHST_STAT_CLEAR);
smbus_write8(ASF_MMIO_BASE, SMBSLVSTAT, SMBSLV_STAT_CLEAR);
smbus_write8(ACPIMMIO_SMBUS_BASE, SMBHSTSTAT, SMBHST_STAT_CLEAR);
smbus_write8(ACPIMMIO_SMBUS_BASE, SMBSLVSTAT, SMBSLV_STAT_CLEAR);
smbus_write8(ACPIMMIO_ASF_BASE, SMBHSTSTAT, SMBHST_STAT_CLEAR);
smbus_write8(ACPIMMIO_ASF_BASE, SMBSLVSTAT, SMBSLV_STAT_CLEAR);
}
/* Before console init */