Documentation: Convert vboot to markdown
Convert the HTML document to markdown and place it under security section. Change-Id: I212c6d0c977fd6772371ff6676478d48cc215d6e Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32610 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Patrick Rudolph
Patrick Georgi
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@ -29,7 +29,6 @@
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</li>
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<li><a target="_blank" href="SoC/soc.html">SoC</a> support</li>
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<li><a target="_blank" href="Board/board.html">Board</a> support</li>
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<li><a target="_blank" href="vboot.html">Verified Boot (vboot)</a> support</li>
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</ul>
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@ -1,402 +0,0 @@
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<!DOCTYPE html>
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<html>
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<head>
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<title>vboot - Verified Boot Support</title>
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</head>
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<body>
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<h1>vboot - Verified Boot Support</h1>
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<p>
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Google's verified boot support consists of:
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</p>
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<ul>
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<li>A root of trust</li>
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<li>Special firmware layout</li>
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<li>Firmware verification</li>
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<li>Firmware measurements</li>
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<li>A firmware update mechanism</li>
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<li>Specific build flags</li>
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<li>Signing the coreboot image</li>
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</ul>
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Google's vboot verifies the firmware and places measurements
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within the TPM.
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<hr>
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<h2>Root of Trust</h2>
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<p>
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When using vboot, the root-of-trust is basically the read-only portion of the
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SPI flash. The following items factor into the trust equation:
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</p>
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<ul>
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<li>The GCC compiler must reliably translate the code into machine code
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without inserting any additional code (virus, backdoor, etc.)
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</li>
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<li>The CPU must reliably execute the reset sequence and instructions as
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documented by the CPU manufacturer.
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</li>
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<li>The SPI flash must provide only the code programmed into it to the CPU
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without providing any alternative reset vector or code sequence.
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</li>
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<li>The SPI flash must honor the write-protect input and protect the
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specified portion of the SPI flash from all erase and write accesses.
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</li>
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</ul>
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<p>
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The firmware is typically protected using the write-protect pin on the SPI
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flash part and setting some of the write-protect bits in the status register
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during manufacturing. The protected area is platform specific and for x86
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platforms is typically 1/4th of the SPI flash
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part size. Because this portion of the SPI flash is hardware write protected,
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it is not possible to update this portion of the SPI flash in the field,
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without altering the system to eliminate the ground connection to the SPI flash
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write-protect pin. Without hardware modifications, this portion of the SPI
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flash maintains the manufactured state during the system's lifetime.
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</p>
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<hr>
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<h2>Firmware Layout</h2>
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<p>
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Several sections are added to the firmware layout to support vboot:
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</p>
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<ul>
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<li>Read-only section</li>
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<li>Google Binary Blob (GBB) area</li>
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<li>Read/write section A</li>
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<li>Read/write section B</li>
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</ul>
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<p>
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The following sections describe the various portions of the flash layout.
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</p>
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<h3>Read-Only Section</h3>
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<p>
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The read-only section contains a coreboot file system (CBFS) that contains all
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of the boot firmware necessary to perform recovery for the system. This
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firmware is typically protected using the write-protect pin on the SPI flash
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part and setting some of the write-protect bits in the status register during
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manufacturing. The protected area is typically 1/4th of the SPI flash part
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size and must cover the entire read-only section which consists of:
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</p>
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<ul>
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<li>Vital Product Data (VPD) area</li>
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<li>Firmware ID area</li>
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<li>Google Binary Blob (GBB) area</li>
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<li>coreboot file system containing read-only recovery firmware</li>
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</ul>
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<h3>Google Binary Blob (GBB) Area</h3>
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<p>
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The GBB area is part of the read-only section. This area contains a 4096 or
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8192 bit public root RSA key that is used to verify the VBLOCK area to obtain
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the firmware signing key.
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</p>
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<h3>Recovery Firmware</h3>
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<p>
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The recovery firmware is contained within a coreboot file system and consists
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of:
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</p>
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<ul>
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<li>reset vector</li>
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<li>bootblock</li>
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<li>verstage</li>
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<li>romstage</li>
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<li>postcar</li>
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<li>ramstage</li>
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<li>payload</li>
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<li>flash map file</li>
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<li>config file</li>
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<li>processor specific files:
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<ul>
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<li>Microcode</li>
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<li>fspm.bin</li>
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<li>fsps.bin</li>
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</ul>
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</li>
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</ul>
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<p>
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The recovery firmware is written during manufacturing and typically contains
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code to write the storage device (eMMC device or hard disk). The recovery
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image is usually contained on a socketed device such as a USB flash drive or
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an SD card. Depending upon the payload firmware doing the recovery, it may
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be possible for the user to interact with the system to specify the recovery
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image path. Part of the recovery is also to write the A and B areas of the
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SPI flash device to boot the system.
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</p>
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<h3>Read/Write Section</h3>
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<p>
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The read/write sections contain an area which contains the firmware signing
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key and signature and an area containing a coreboot file system with a subset
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of the firmware. The firmware files in FW_MAIN_A and FW_MAIN_B are:
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</p>
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<ul>
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<li>romstage</li>
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<li>postcar</li>
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<li>ramstage</li>
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<li>payload</li>
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<li>config file</li>
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<li>processor specific files:
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<ul>
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<li>Microcode</li>
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<li>fspm.bin</li>
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<li>fsps.bin</li>
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</ul>
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</li>
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</ul>
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<p>
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The firmware subset enables most issues to be fixed in the field with firmware
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updates. The firmware files handle memory and most of silicon initialization.
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These files also produce the tables which get passed to the operating system.
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</p>
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<hr>
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<h2>Firmware Updates</h2>
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<p>
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The read/write sections exist in one of three states:
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</p>
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<ul>
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<li>Invalid</li>
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<li>Ready to boot</li>
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<li>Successfully booted</li>
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</ul>
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<table border="1">
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<tr bgcolor="#ffc0c0">
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<td>
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Where is this state information written?
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<br/>CMOS?
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<br/>RW_NVRAM?
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<br/>RW_FWID_*
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</td>
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</tr>
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</table>
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<p>
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Firmware updates are handled by the operating system by writing any read/write
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section that is not in the "successfully booted" state. Upon the next reboot,
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vboot determines the section to boot. If it finds one in the "ready to boot"
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state then it attempts to boot using that section. If the boot fails then
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vboot marks the section as invalid and attempts to fall back to a read/write
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section in the "successfully booted" state. If vboot is not able to find a
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section in the "successfully booted" state then vboot enters recovery mode.
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</p>
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<p>
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Only the operating system is able to transition a section from the "ready to
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boot" state to the "successfully booted" state. The transition is typically
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done after the operating system has been running for a while indicating
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that successful boot was possible and the operating system is stable.
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</p>
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<p>
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Note that as long as the SPI write protection is in place then the system is
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always recoverable. If the flash update fails then the system will continue
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to boot using the previous read/write area. The same is true if coreboot
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passes control to the payload or the operating system and then the boot fails.
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In the worst case, the SPI flash gets totally corrupted in which case vboot
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fails the signature checks and enters recovery mode. There are no times where
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the SPI flash is exposed and the reset vector or part of the recovery firmware
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gets corrupted.
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</p>
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<hr>
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<h2>Build Flags</h2>
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<p>
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The following Kconfig values need to be selected to enable vboot:
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</p>
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<ul>
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<li>COLLECT_TIMESTAMPS</li>
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<li>VBOOT</li>
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</ul>
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<p>
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The starting stage needs to be specified by selecting either
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VBOOT_STARTS_IN_BOOTBLOCK or VBOOT_STARTS_IN_ROMSTAGE.
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</p>
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<p>
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If vboot starts in bootblock then vboot may be built as a separate stage by
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selecting VBOOT_SEPARATE_VERSTAGE. Additionally, if static RAM is too small
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to fit both verstage and romstage then selecting VBOOT_RETURN_FROM_VERSTAGE
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enables bootblock to reuse the RAM occupied by verstage for romstage.
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</p>
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<p>
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Non-volatile flash is needed for vboot operation. This flash area may be in
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CMOS, the EC, or in a read/write area of the SPI flash device. Select one of
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the following:
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</p>
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<ul>
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<li>VBOOT_VBNV_CMOS</li>
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<li>VBOOT_VBNV_EC</li>
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<li>VBOOT_VBNV_FLASH</li>
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</ul>
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<p>
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More non-volatile storage features may be found in src/vboot/Kconfig.
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</p>
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<p>
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A TPM is also required for vboot operation. TPMs are available in
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drivers/i2c/tpm and drivers/pc80/tpm.
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</p>
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<p>
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In addition to adding the coreboot files into the read-only region, enabling
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vboot causes the build script to add the read/write files into coreboot file
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systems in FW_MAIN_A and FW_MAIN_B.
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</p>
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<hr>
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<h2>Signing the coreboot Image</h2>
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<p>
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The following command script is an example of how to sign the coreboot image file.
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This script is used on the Intel Galileo board and creates the GBB area and
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inserts it into the coreboot image. It also updates the VBLOCK areas with the
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firmware signing key and the signature for the FW_MAIN firmware. More details
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are available in 3rdparty/vboot/README.
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</p>
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<pre><code>#!/bin/sh
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#
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# The necessary tools were built and installed using the following commands:
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#
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# pushd 3rdparty/vboot
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# make
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# sudo make install
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# popd
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#
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# The keys were made using the following command
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#
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# 3rdparty/vboot/scripts/keygeneration/create_new_keys.sh \
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# --4k --4k-root --output $PWD/keys
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#
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#
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# The "magic" numbers below are derived from the GBB section in
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# src/mainboard/intel/galileo/vboot.fmd.
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#
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# GBB Header Size: 0x80
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# GBB Offset: 0x611000, 4KiB block number: 1553 (0x611)
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# GBB Length: 0x7f000, 4KiB blocks: 127 (0x7f)
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# COREBOOT Offset: 0x690000, 4KiB block number: 1680 (0x690)
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# COREBOOT Length: 0x170000, 4KiB blocks: 368 (0x170)
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#
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# 0x7f000 (GBB Length) = 0x80 + 0x100 + 0x1000 + 0x7ce80 + 0x1000
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#
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# Create the GBB area blob
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# Parameters: hwid_size,rootkey_size,bmpfv_size,recoverykey_size
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#
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gbb_utility -c 0x100,0x1000,0x7ce80,0x1000 gbb.blob
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#
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# Copy from the start of the flash to the GBB region into the signed flash
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# image.
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#
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# 1553 * 4096 = 0x611 * 0x1000 = 0x611000, size of area before GBB
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#
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dd conv=fdatasync ibs=4096 obs=4096 count=1553 \
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if=build/coreboot.rom of=build/coreboot.signed.rom
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#
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# Append the empty GBB area to the coreboot.rom image.
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#
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# 1553 * 4096 = 0x611 * 0x1000 = 0x611000, offset to GBB
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#
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dd conv=fdatasync obs=4096 obs=4096 seek=1553 if=gbb.blob \
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of=build/coreboot.signed.rom
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#
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# Append the rest of the read-only region into the signed flash image.
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#
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# 1680 * 4096 = 0x690 * 0x1000 = 0x690000, offset to COREBOOT area
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# 368 * 4096 = 0x170 * 0x1000 = 0x170000, length of COREBOOT area
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#
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dd conv=fdatasync ibs=4096 obs=4096 skip=1680 seek=1680 count=368 \
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if=build/coreboot.rom of=build/coreboot.signed.rom
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#
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# Insert the HWID and public root and recovery RSA keys into the GBB area.
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#
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gbb_utility \
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--set --hwid='Galileo' \
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-r $PWD/keys/recovery_key.vbpubk \
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-k $PWD/keys/root_key.vbpubk \
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build/coreboot.signed.rom
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#
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# Sign the read/write firmware areas with the private signing key and update
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# the VBLOCK_A and VBLOCK_B regions.
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#
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3rdparty/vboot/scripts/image_signing/sign_firmware.sh \
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build/coreboot.signed.rom \
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$PWD/keys \
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build/coreboot.signed.rom
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</code></pre>
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<hr>
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<h2>Boot Flow</h2>
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<p>
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The reset vector exist in the read-only area and points to the bootblock entry
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point. The only copy of the bootblock exists in the read-only area of the SPI
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flash. Verstage may be part of the bootblock or a separate stage. If separate
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then the bootblock loads verstage from the read-only area and transfers control
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to it.
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</p>
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<p>
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Upon first boot, verstage attempts to verify the read/write section A. It gets
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the public root key from the GBB area and uses that to verify the VBLOCK area
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in read-write section A. If the VBLOCK area is valid then it extracts the
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firmware signing key (1024-8192 bits) and uses that to verify the FW_MAIN_A
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area of read/write section A. If the verification is successful then verstage
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instructs coreboot to use the coreboot file system in read/write section A for
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the contents of the remaining boot firmware (romstage, postcar, ramstage and
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the payload).
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</p>
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<p>
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If verification fails for the read/write area and the other read/write area is
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not valid vboot falls back to the read-only area to boot into system recovery.
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</p>
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<hr>
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<h2>Chromebook Special Features</h2>
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<p>
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Google's Chromebooks have some special features:
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</p>
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<ul>
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<li>Developer mode</li>
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<li>Write-protect screw</li>
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</ul>
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<h3>Developer Mode</h3>
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<p>
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Developer mode allows the user to use coreboot to boot another operating system.
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This may be a another (beta) version of Chrome OS, or another flavor of
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GNU/Linux. Use of developer mode does not void the system warranty. Upon
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entry into developer mode, all locally saved data on the system is lost.
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This prevents someone from entering developer mode to subvert the system
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security to access files on the local system or cloud.
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</p>
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<h3>Write Protect Screw</h3>
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<p>
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Chromebooks have a write-protect screw which provides the ground to the
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write-protect pin of the SPI flash. Google specifically did this to allow
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the manufacturing line and advanced developers to re-write the entire SPI flash
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part. Once the screw is removed, any firmware may be placed on the device.
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However, accessing this screw requires opening the case and voids the system
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warranty!
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</p>
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<hr>
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<p>Modified: 2 May 2017</p>
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</body>
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</html>
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@ -4,4 +4,5 @@ This section describes documentation about the security architecture of coreboot
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## Vendor
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- [Verified Boot](vboot/index.md)
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- [Measured Boot](vboot/measured_boot.md)
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|
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|
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@ -0,0 +1,324 @@
|
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# vboot - Verified Boot Support
|
||||
|
||||
Google's verified boot support consists of:
|
||||
|
||||
* A root of trust
|
||||
* Special firmware layout
|
||||
* Firmware verification
|
||||
* Firmware measurements
|
||||
* A firmware update mechanism
|
||||
* Specific build flags
|
||||
* Signing the coreboot image
|
||||
|
||||
Google's vboot verifies the firmware and places measurements within the TPM.
|
||||
|
||||
***
|
||||
|
||||
## Root of Trust
|
||||
|
||||
When using vboot, the root-of-trust is basically the read-only portion of the
|
||||
SPI flash. The following items factor into the trust equation:
|
||||
|
||||
* The GCC compiler must reliably translate the code into machine code
|
||||
without inserting any additional code (virus, backdoor, etc.)
|
||||
* The CPU must reliably execute the reset sequence and instructions as
|
||||
documented by the CPU manufacturer.
|
||||
* The SPI flash must provide only the code programmed into it to the CPU
|
||||
without providing any alternative reset vector or code sequence.
|
||||
* The SPI flash must honor the write-protect input and protect the specified
|
||||
portion of the SPI flash from all erase and write accesses.
|
||||
|
||||
The firmware is typically protected using the write-protect pin on the SPI
|
||||
flash part and setting some of the write-protect bits in the status register
|
||||
during manufacturing. The protected area is platform specific and for x86
|
||||
platforms is typically 1/4th of the SPI flash part size.
|
||||
Because this portion of the SPI flash is hardware write protected, it is not
|
||||
possible to update this portion of the SPI flash in the field, without altering
|
||||
the system to eliminate the ground connection to the SPI flash write-protect pin.
|
||||
Without hardware modifications, this portion of the SPI flash maintains the
|
||||
manufactured state during the system's lifetime.
|
||||
|
||||
***
|
||||
|
||||
## Firmware Layout
|
||||
|
||||
Several sections are added to the firmware layout to support vboot:
|
||||
|
||||
* Read-only section
|
||||
* Google Binary Blob (GBB) area
|
||||
* Read/write section A
|
||||
* Read/write section B
|
||||
|
||||
The following sections describe the various portions of the flash layout.
|
||||
|
||||
### Read-Only Section
|
||||
|
||||
The read-only section contains a coreboot file system (CBFS) that contains all
|
||||
of the boot firmware necessary to perform recovery for the system. This firmware
|
||||
is typically protected using the write-protect pin on the SPI flash part and
|
||||
setting some of the write-protect bits in the status register during
|
||||
manufacturing.
|
||||
The protected area is typically 1/4th of the SPI flash part size and must cover
|
||||
the entire read-only section which consists of:
|
||||
|
||||
* Vital Product Data (VPD) area
|
||||
* Firmware ID area
|
||||
* Google Binary Blob (GBB) area
|
||||
* coreboot file system containing read-only recovery firmware
|
||||
|
||||
### Google Binary Blob (GBB) Area
|
||||
|
||||
The GBB area is part of the read-only section. This area contains a 4096 or 8192
|
||||
bit public root RSA key that is used to verify the *VBLOCK* area to obtain the
|
||||
firmware signing key.
|
||||
|
||||
### Recovery Firmware
|
||||
|
||||
The recovery firmware is contained within a coreboot file system and consists of:
|
||||
|
||||
* reset vector
|
||||
* bootblock
|
||||
* verstage
|
||||
* romstage
|
||||
* postcar
|
||||
* ramstage
|
||||
* payload
|
||||
* flash map file
|
||||
* config file
|
||||
* processor specific files:
|
||||
* Microcode
|
||||
* fspm.bin
|
||||
* fsps.bin
|
||||
|
||||
The recovery firmware is written during manufacturing and typically contains
|
||||
code to write the storage device (eMMC device or hard disk). The recovery image
|
||||
is usually contained on a socketed device such as a USB flash drive or an
|
||||
SD card. Depending upon the payload firmware doing the recovery, it may be
|
||||
possible for the user to interact with the system to specify the recovery
|
||||
image path. Part of the recovery is also to write the A and B areas of the SPI
|
||||
flash device to boot the system.
|
||||
|
||||
### Read/Write Section
|
||||
|
||||
The read/write sections contain an area which contains the firmware signing
|
||||
key and signature and an area containing a coreboot file system with a subset
|
||||
of the firmware. The firmware files in *FW_MAIN_A* and *FW_MAIN_B* are:
|
||||
|
||||
* romstage
|
||||
* postcar
|
||||
* ramstage
|
||||
* payload
|
||||
* config file
|
||||
* processor specific files:
|
||||
* Microcode
|
||||
* fspm.bin
|
||||
* fsps.bin
|
||||
|
||||
The firmware subset enables most issues to be fixed in the field with firmware
|
||||
updates. The firmware files handle memory and most of silicon initialization.
|
||||
These files also produce the tables which get passed to the operating system.
|
||||
|
||||
***
|
||||
|
||||
## Firmware Updates
|
||||
|
||||
The read/write sections exist in one of three states:
|
||||
|
||||
* Invalid
|
||||
* Ready to boot
|
||||
* Successfully booted
|
||||
|
||||
|
||||
Firmware updates are handled by the operating system by writing any read/write
|
||||
section that is not in the "successfully booted" state. Upon the next reboot,
|
||||
vboot determines the section to boot. If it finds one in the "ready to boot"
|
||||
state then it attempts to boot using that section. If the boot fails then
|
||||
vboot marks the section as invalid and attempts to fall back to a read/write
|
||||
section in the "successfully booted" state. If vboot is not able to find a
|
||||
section in the "successfully booted" state then vboot enters recovery mode.
|
||||
|
||||
Only the operating system is able to transition a section from the
|
||||
"ready to boot" state to the "successfully booted" state.
|
||||
The transition is typically done after the operating system has been running
|
||||
for a while indicating that successful boot was possible and the operating
|
||||
system is stable.
|
||||
|
||||
Note that as long as the SPI write protection is in place then the system
|
||||
is always recoverable. If the flash update fails then the system will continue
|
||||
to boot using the previous read/write area. The same is true if coreboot passes
|
||||
control to the payload or the operating system and then the boot fails. In the
|
||||
worst case, the SPI flash gets totally corrupted in which case vboot fails the
|
||||
signature checks and enters recovery mode. There are no times where the SPI
|
||||
flash is exposed and the reset vector or part of the recovery firmware gets
|
||||
corrupted.
|
||||
|
||||
***
|
||||
|
||||
## Build Flags
|
||||
|
||||
The following *Kconfig* values need to be selected to enable vboot:
|
||||
|
||||
* COLLECT_TIMESTAMPS
|
||||
* VBOOT
|
||||
|
||||
The starting stage needs to be specified by selecting either
|
||||
VBOOT_STARTS_IN_BOOTBLOCK or VBOOT_STARTS_IN_ROMSTAGE.
|
||||
|
||||
If vboot starts in bootblock then vboot may be built as a separate stage by
|
||||
selecting `VBOOT_SEPARATE_VERSTAGE`. Additionally, if static RAM is too small
|
||||
to fit both verstage and romstage then selecting `VBOOT_RETURN_FROM_VERSTAGE`
|
||||
enables bootblock to reuse the RAM occupied by verstage for romstage.
|
||||
|
||||
Non-volatile flash is needed for vboot operation. This flash area may be in
|
||||
CMOS, the EC, or in a read/write area of the SPI flash device.
|
||||
Select one of the following:
|
||||
|
||||
* `VBOOT_VBNV_CMOS`
|
||||
* `VBOOT_VBNV_EC`
|
||||
* `VBOOT_VBNV_FLASH`
|
||||
|
||||
More non-volatile storage features may be found in `security/vboot/Kconfig`.
|
||||
|
||||
A TPM is also required for vboot operation.
|
||||
TPMs are available in `drivers/i2c/tpm` and `drivers/pc80/tpm`.
|
||||
|
||||
In addition to adding the coreboot files into the read-only region,
|
||||
enabling vboot causes the build script to add the read/write files into
|
||||
coreboot file systems in *FW_MAIN_A* and *FW_MAIN_B*.
|
||||
|
||||
***
|
||||
|
||||
## Signing the coreboot Image
|
||||
|
||||
The following command script is an example of how to sign the coreboot image
|
||||
file. This script is used on the Intel Galileo board and creates the *GBB* area
|
||||
and inserts it into the coreboot image. It also updates the *VBLOCK* areas with
|
||||
the firmware signing key and the signature for the *FW_MAIN* firmware.
|
||||
More details are available in `3rdparty/vboot/README`.
|
||||
|
||||
```bash
|
||||
#!/bin/sh
|
||||
#
|
||||
# The necessary tools were built and installed using the following commands:
|
||||
#
|
||||
# pushd 3rdparty/vboot
|
||||
# make
|
||||
# sudo make install
|
||||
# popd
|
||||
#
|
||||
# The keys were made using the following command
|
||||
#
|
||||
# 3rdparty/vboot/scripts/keygeneration/create_new_keys.sh \
|
||||
# --4k --4k-root --output $PWD/keys
|
||||
#
|
||||
#
|
||||
# The "magic" numbers below are derived from the GBB section in
|
||||
# src/mainboard/intel/galileo/vboot.fmd.
|
||||
#
|
||||
# GBB Header Size: 0x80
|
||||
# GBB Offset: 0x611000, 4KiB block number: 1553 (0x611)
|
||||
# GBB Length: 0x7f000, 4KiB blocks: 127 (0x7f)
|
||||
# COREBOOT Offset: 0x690000, 4KiB block number: 1680 (0x690)
|
||||
# COREBOOT Length: 0x170000, 4KiB blocks: 368 (0x170)
|
||||
#
|
||||
# 0x7f000 (GBB Length) = 0x80 + 0x100 + 0x1000 + 0x7ce80 + 0x1000
|
||||
#
|
||||
# Create the GBB area blob
|
||||
# Parameters: hwid_size,rootkey_size,bmpfv_size,recoverykey_size
|
||||
#
|
||||
gbb_utility -c 0x100,0x1000,0x7ce80,0x1000 gbb.blob
|
||||
|
||||
#
|
||||
# Copy from the start of the flash to the GBB region into the signed flash
|
||||
# image.
|
||||
#
|
||||
# 1553 * 4096 = 0x611 * 0x1000 = 0x611000, size of area before GBB
|
||||
#
|
||||
dd conv=fdatasync ibs=4096 obs=4096 count=1553 \
|
||||
if=build/coreboot.rom of=build/coreboot.signed.rom
|
||||
|
||||
#
|
||||
# Append the empty GBB area to the coreboot.rom image.
|
||||
#
|
||||
# 1553 * 4096 = 0x611 * 0x1000 = 0x611000, offset to GBB
|
||||
#
|
||||
dd conv=fdatasync obs=4096 obs=4096 seek=1553 if=gbb.blob \
|
||||
of=build/coreboot.signed.rom
|
||||
|
||||
#
|
||||
# Append the rest of the read-only region into the signed flash image.
|
||||
#
|
||||
# 1680 * 4096 = 0x690 * 0x1000 = 0x690000, offset to COREBOOT area
|
||||
# 368 * 4096 = 0x170 * 0x1000 = 0x170000, length of COREBOOT area
|
||||
#
|
||||
dd conv=fdatasync ibs=4096 obs=4096 skip=1680 seek=1680 count=368 \
|
||||
if=build/coreboot.rom of=build/coreboot.signed.rom
|
||||
|
||||
#
|
||||
# Insert the HWID and public root and recovery RSA keys into the GBB area.
|
||||
#
|
||||
gbb_utility \
|
||||
--set --hwid='Galileo' \
|
||||
-r $PWD/keys/recovery_key.vbpubk \
|
||||
-k $PWD/keys/root_key.vbpubk \
|
||||
build/coreboot.signed.rom
|
||||
|
||||
#
|
||||
# Sign the read/write firmware areas with the private signing key and update
|
||||
# the VBLOCK_A and VBLOCK_B regions.
|
||||
#
|
||||
3rdparty/vboot/scripts/image_signing/sign_firmware.sh \
|
||||
build/coreboot.signed.rom \
|
||||
$PWD/keys \
|
||||
build/coreboot.signed.rom
|
||||
```
|
||||
|
||||
***
|
||||
|
||||
## Boot Flow
|
||||
|
||||
The reset vector exist in the read-only area and points to the bootblock
|
||||
entry point. The only copy of the bootblock exists in the read-only area
|
||||
of the SPI flash. Verstage may be part of the bootblock or a separate stage.
|
||||
If separate then the bootblock loads verstage from the read-only area and
|
||||
transfers control to it.
|
||||
|
||||
Upon first boot, verstage attempts to verify the read/write section A.
|
||||
It gets the public root key from the GBB area and uses that to verify the
|
||||
*VBLOCK* area in read-write section A. If the *VBLOCK* area is valid then it
|
||||
extracts the firmware signing key (1024-8192 bits) and uses that to verify
|
||||
the *FW_MAIN_A* area of read/write section A. If the verification is successful
|
||||
then verstage instructs coreboot to use the coreboot file system in read/write
|
||||
section A for the contents of the remaining boot firmware (romstage, postcar,
|
||||
ramstage and the payload).
|
||||
|
||||
If verification fails for the read/write area and the other read/write area is
|
||||
not valid vboot falls back to the read-only area to boot into system recovery.
|
||||
|
||||
***
|
||||
|
||||
## Chromebook Special Features
|
||||
|
||||
Google's Chromebooks have some special features:
|
||||
|
||||
* Developer mode
|
||||
* Write-protect screw
|
||||
|
||||
### Developer Mode
|
||||
|
||||
Developer mode allows the user to use coreboot to boot another operating system.
|
||||
This may be a another (beta) version of Chrome OS, or another flavor of
|
||||
GNU/Linux. Use of developer mode does not void the system warranty. Upon entry
|
||||
into developer mode, all locally saved data on the system is lost.
|
||||
This prevents someone from entering developer mode to subvert the system
|
||||
security to access files on the local system or cloud.
|
||||
|
||||
### Write Protect Screw
|
||||
|
||||
Chromebooks have a write-protect screw which provides the ground to the
|
||||
write-protect pin of the SPI flash.
|
||||
Google specifically did this to allow the manufacturing line and advanced
|
||||
developers to re-write the entire SPI flash part. Once the screw is removed,
|
||||
any firmware may be placed on the device.
|
||||
However, accessing this screw requires opening the case and voids the
|
||||
system warranty!
|
||||
Loading…
Reference in New Issue