- Modify the code to C style indenting.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1180 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Eric Biederman
parent
fae510cd84
commit
5ebf4d3431
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@ -13,10 +13,11 @@
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#include "northbridge/via/vt8601/raminit.h"
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/*
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*/
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void udelay(int usecs) {
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int i;
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for(i = 0; i < usecs; i++)
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outb(i&0xff, 0x80);
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void udelay(int usecs)
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{
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int i;
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for(i = 0; i < usecs; i++)
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outb(i&0xff, 0x80);
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}
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#include "lib/delay.c"
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@ -40,9 +41,9 @@ static void memreset_setup(void)
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*/
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static inline int spd_read_byte(unsigned device, unsigned address)
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{
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unsigned char c;
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c = smbus_read_byte(device, address);
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return c;
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unsigned char c;
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c = smbus_read_byte(device, address);
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return c;
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}
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@ -52,84 +53,85 @@ static inline int spd_read_byte(unsigned device, unsigned address)
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#include "sdram/generic_sdram.c"
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*/
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static void
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enable_mainboard_devices(void) {
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device_t dev;
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/* dev 0 for southbridge */
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static void enable_mainboard_devices(void)
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{
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device_t dev;
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/* dev 0 for southbridge */
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dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0);
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dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0);
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if (dev == PCI_DEV_INVALID) {
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die("Southbridge not found!!!\n");
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}
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pci_write_config8(dev, 0x50, 7);
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pci_write_config8(dev, 0x51, 0xff);
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if (dev == PCI_DEV_INVALID) {
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die("Southbridge not found!!!\n");
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}
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pci_write_config8(dev, 0x50, 7);
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pci_write_config8(dev, 0x51, 0xff);
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#if 0
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// This early setup switches IDE into compatibility mode before PCI gets
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// // a chance to assign I/Os
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// movl $CONFIG_ADDR(0, 0x89, 0x42), %eax
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// // movb $0x09, %dl
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// movb $0x00, %dl
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// PCI_WRITE_CONFIG_BYTE
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//
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// This early setup switches IDE into compatibility mode before PCI gets
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// // a chance to assign I/Os
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// movl $CONFIG_ADDR(0, 0x89, 0x42), %eax
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// // movb $0x09, %dl
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// movb $0x00, %dl
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// PCI_WRITE_CONFIG_BYTE
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//
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#endif
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/* we do this here as in V2, we can not yet do raw operations
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* to pci!
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*/
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dev++; /* ICKY */
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pci_write_config8(dev, 0x42, 0);
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/* we do this here as in V2, we can not yet do raw operations
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* to pci!
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*/
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dev++; /* ICKY */
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pci_write_config8(dev, 0x42, 0);
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}
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static void
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enable_shadow_ram(void) {
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device_t dev = 0; /* no need to look up 0:0.0 */
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unsigned char shadowreg;
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/* dev 0 for southbridge */
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shadowreg = pci_read_config8(dev, 0x63);
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/* 0xf0000-0xfffff */
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shadowreg |= 0x30;
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pci_write_config8(dev, 0x63, shadowreg);
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static void enable_shadow_ram(void)
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{
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device_t dev = 0; /* no need to look up 0:0.0 */
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unsigned char shadowreg;
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/* dev 0 for southbridge */
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shadowreg = pci_read_config8(dev, 0x63);
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/* 0xf0000-0xfffff */
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shadowreg |= 0x30;
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pci_write_config8(dev, 0x63, shadowreg);
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}
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static void main(void)
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{
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unsigned long x;
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/* init_timer();*/
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outb(5, 0x80);
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enable_vt8231_serial();
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enable_mainboard_devices();
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uart_init();
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console_init();
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unsigned long x;
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/* init_timer();*/
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outb(5, 0x80);
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enable_smbus();
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enable_shadow_ram();
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/*
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memreset_setup();
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this is way more generic than we need.
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sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
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*/
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sdram_set_registers((const struct mem_controller *) 0);
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sdram_set_spd_registers((const struct mem_controller *) 0);
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sdram_enable(0, (const struct mem_controller *) 0);
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/* Check all of memory */
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enable_vt8231_serial();
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enable_mainboard_devices();
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uart_init();
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console_init();
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enable_smbus();
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enable_shadow_ram();
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/*
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memreset_setup();
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this is way more generic than we need.
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sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
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*/
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sdram_set_registers((const struct mem_controller *) 0);
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sdram_set_spd_registers((const struct mem_controller *) 0);
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sdram_enable(0, (const struct mem_controller *) 0);
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/* Check all of memory */
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#if 0
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ram_check(0x00000000, msr.lo);
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ram_check(0x00000000, msr.lo);
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#endif
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#if 0
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static const struct {
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unsigned long lo, hi;
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} check_addrs[] = {
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/* Check 16MB of memory @ 0*/
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{ 0x00000000, 0x01000000 },
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static const struct {
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unsigned long lo, hi;
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} check_addrs[] = {
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/* Check 16MB of memory @ 0*/
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{ 0x00000000, 0x01000000 },
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#if TOTAL_CPUS > 1
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/* Check 16MB of memory @ 2GB */
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{ 0x80000000, 0x81000000 },
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/* Check 16MB of memory @ 2GB */
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{ 0x80000000, 0x81000000 },
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#endif
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};
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int i;
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for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) {
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ram_check(check_addrs[i].lo, check_addrs[i].hi);
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}
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};
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int i;
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for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) {
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ram_check(check_addrs[i].lo, check_addrs[i].hi);
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}
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#endif
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}
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@ -47,424 +47,436 @@ it with the version available from LANL.
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#define DIMM_CL2 0
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#endif
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void dimms_read(unsigned long x) {
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uint8_t c;
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unsigned long eax;
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volatile unsigned long y;
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eax = x;
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for(c = 0; c < 6; c++) {
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print_err("dimms_read: ");
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print_err_hex32(eax);
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print_err("\r\n");
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y = * (volatile unsigned long *) eax;
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eax += 0x10000000;
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}
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void dimms_read(unsigned long x)
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{
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uint8_t c;
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unsigned long eax;
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volatile unsigned long y;
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eax = x;
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for(c = 0; c < 6; c++) {
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print_err("dimms_read: ");
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print_err_hex32(eax);
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print_err("\r\n");
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y = * (volatile unsigned long *) eax;
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eax += 0x10000000;
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}
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}
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void dimms_write(int x) {
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uint8_t c;
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unsigned long eax = x;
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for(c = 0; c < 6; c++) {
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print_err("dimms_write: ");
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print_err_hex32(eax);
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print_err("\r\n");
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*(volatile unsigned long *) eax = 0;
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eax += 0x10000000;
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}
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void dimms_write(int x)
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{
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uint8_t c;
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unsigned long eax = x;
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for(c = 0; c < 6; c++) {
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print_err("dimms_write: ");
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print_err_hex32(eax);
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print_err("\r\n");
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*(volatile unsigned long *) eax = 0;
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eax += 0x10000000;
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}
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}
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#ifdef DEBUG_SETNORTHB
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void setnorthb(device_t north, uint8_t reg, uint8_t val) {
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print_err("setnorth: reg ");
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print_err_hex8(reg);
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print_err(" to ");
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print_err_hex8(val);
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print_err("\r\n");
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pci_write_config8(north, reg, val);
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void setnorthb(device_t north, uint8_t reg, uint8_t val)
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{
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print_err("setnorth: reg ");
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print_err_hex8(reg);
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print_err(" to ");
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print_err_hex8(val);
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print_err("\r\n");
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pci_write_config8(north, reg, val);
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}
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#else
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#define setnorthb pci_write_config8
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#endif
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void
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dumpnorth(device_t north) {
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uint8_t r, c;
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for(r = 0; r < 256; r += 16) {
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print_err_hex8(r);
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print_err(":");
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for(c = 0; c < 16; c++) {
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print_err_hex8(pci_read_config8(north, r+c));
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print_err(" ");
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}
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print_err("\r\n");
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dumpnorth(device_t north)
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{
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uint8_t r, c;
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for(r = 0; r < 256; r += 16) {
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print_err_hex8(r);
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print_err(":");
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for(c = 0; c < 16; c++) {
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print_err_hex8(pci_read_config8(north, r+c));
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print_err(" ");
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}
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print_err("\r\n");
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}
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}
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static void sdram_set_registers(const struct mem_controller *ctrl) {
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static const uint16_t raminit_ma_reg_table[] = {
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/* Values for MA type register to try */
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0x0000, 0x8088, 0xe0ee,
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0xffff // end mark
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};
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static const unsigned char ramregs[] = {0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
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static void sdram_set_registers(const struct mem_controller *ctrl)
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{
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static const uint16_t raminit_ma_reg_table[] = {
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/* Values for MA type register to try */
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0x0000, 0x8088, 0xe0ee,
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0xffff // end mark
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};
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static const unsigned char ramregs[] = {0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
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0x56, 0x57};
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device_t north = (device_t) 0;
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uint8_t c, r;
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device_t north = (device_t) 0;
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uint8_t c, r;
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print_err("vt8601 init starting\n");
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north = pci_locate_device(PCI_ID(0x1106, 0x8601), 0);
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north = 0;
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print_err_hex32(north);
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print_err(" is the north\n");
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print_err_hex16(pci_read_config16(north, 0));
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print_err(" ");
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print_err_hex16(pci_read_config16(north, 2));
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print_err("\r\n");
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/* All we are doing now is setting initial known-good values that will
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* be revised later as we read SPD
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*/
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// memory clk enable. We are not using ECC
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pci_write_config8(north,0x78, 0x01);
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print_err_hex8(pci_read_config8(north, 0x78));
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// dram control, see the book.
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print_err("vt8601 init starting\n");
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north = pci_locate_device(PCI_ID(0x1106, 0x8601), 0);
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north = 0;
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print_err_hex32(north);
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print_err(" is the north\n");
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print_err_hex16(pci_read_config16(north, 0));
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print_err(" ");
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print_err_hex16(pci_read_config16(north, 2));
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print_err("\r\n");
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/* All we are doing now is setting initial known-good values that will
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* be revised later as we read SPD
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*/
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// memory clk enable. We are not using ECC
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pci_write_config8(north,0x78, 0x01);
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print_err_hex8(pci_read_config8(north, 0x78));
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// dram control, see the book.
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#if DIMM_PC133
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pci_write_config8(north,0x68, 0x52);
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pci_write_config8(north,0x68, 0x52);
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#else
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pci_write_config8(north,0x68, 0x42);
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pci_write_config8(north,0x68, 0x42);
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#endif
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// dram control, see the book.
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pci_write_config8(north,0x6B, 0x0c);
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// Initial setting, 256MB in each bank, will be rewritten later.
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pci_write_config8(north,0x5A, 0x20);
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print_err_hex8(pci_read_config8(north, 0x5a));
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pci_write_config8(north,0x5B, 0x40);
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pci_write_config8(north,0x5C, 0x60);
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pci_write_config8(north,0x5D, 0x80);
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pci_write_config8(north,0x5E, 0xA0);
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pci_write_config8(north,0x5F, 0xC0);
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// It seems we have to take care of these 2 registers as if
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// they are bank 6 and 7.
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pci_write_config8(north,0x56, 0xC0);
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pci_write_config8(north,0x57, 0xC0);
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// SDRAM in all banks
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pci_write_config8(north,0x60, 0x3F);
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// DRAM timing. I'm suspicious of this
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// This is for all banks, 64 is 0,1. 65 is 2,3. 66 is 4,5.
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// ras precharge 4T, RAS pulse 5T
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// cas2 is 0xd6, cas3 is 0xe6
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// we're also backing off write pulse width to 2T, so result is 0xee
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// dram control, see the book.
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pci_write_config8(north,0x6B, 0x0c);
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// Initial setting, 256MB in each bank, will be rewritten later.
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pci_write_config8(north,0x5A, 0x20);
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print_err_hex8(pci_read_config8(north, 0x5a));
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pci_write_config8(north,0x5B, 0x40);
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pci_write_config8(north,0x5C, 0x60);
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pci_write_config8(north,0x5D, 0x80);
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pci_write_config8(north,0x5E, 0xA0);
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pci_write_config8(north,0x5F, 0xC0);
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// It seems we have to take care of these 2 registers as if
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// they are bank 6 and 7.
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pci_write_config8(north,0x56, 0xC0);
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pci_write_config8(north,0x57, 0xC0);
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// SDRAM in all banks
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pci_write_config8(north,0x60, 0x3F);
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// DRAM timing. I'm suspicious of this
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// This is for all banks, 64 is 0,1. 65 is 2,3. 66 is 4,5.
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// ras precharge 4T, RAS pulse 5T
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// cas2 is 0xd6, cas3 is 0xe6
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// we're also backing off write pulse width to 2T, so result is 0xee
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#if DIMM_CL2
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pci_write_config8(north,0x64, 0xd4);
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pci_write_config8(north,0x65, 0xd4);
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pci_write_config8(north,0x66, 0xd4);
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pci_write_config8(north,0x64, 0xd4);
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pci_write_config8(north,0x65, 0xd4);
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pci_write_config8(north,0x66, 0xd4);
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#else // CL=3
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pci_write_config8(north,0x64, 0xe4);
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pci_write_config8(north,0x65, 0xe4);
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pci_write_config8(north,0x66, 0xe4);
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pci_write_config8(north,0x64, 0xe4);
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pci_write_config8(north,0x65, 0xe4);
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pci_write_config8(north,0x66, 0xe4);
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#endif
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// dram frequency select.
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// enable 4K pages for 64M dram.
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// dram frequency select.
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// enable 4K pages for 64M dram.
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#if DIMM_PC133
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pci_write_config8(north,0x69, 0x3c);
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pci_write_config8(north,0x69, 0x3c);
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#else
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pci_write_config8(north,0x69, 0xac);
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pci_write_config8(north,0x69, 0xac);
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#endif
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/* IMPORTANT -- disable refresh counter */
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// refresh counter, disabled.
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pci_write_config8(north,0x6A, 0x00);
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/* IMPORTANT -- disable refresh counter */
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// refresh counter, disabled.
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pci_write_config8(north,0x6A, 0x00);
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// clkenable configuration. kevinh FIXME - add precharge
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pci_write_config8(north,0x6C, 0x00);
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// dram read latch delay of 1 ns, MD drive 8 mA,
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// high drive strength on MA[2: 13], we#, cas#, ras#
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// As per Cindy Lee, set to 0x37, not 0x57
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pci_write_config8(north,0x6D, 0x7f);
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// clkenable configuration. kevinh FIXME - add precharge
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pci_write_config8(north,0x6C, 0x00);
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// dram read latch delay of 1 ns, MD drive 8 mA,
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// high drive strength on MA[2: 13], we#, cas#, ras#
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// As per Cindy Lee, set to 0x37, not 0x57
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pci_write_config8(north,0x6D, 0x7f);
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|
||||
/* Initialize all banks at once */
|
||||
/* Initialize all banks at once */
|
||||
|
||||
}
|
||||
|
||||
/* slot is the dram slot. Base is the *8M base. */
|
||||
static unsigned char
|
||||
do_module_size(unsigned char slot) { /*, unsigned char base) */
|
||||
static const unsigned char log2[256] = {[1] = 0, [2] = 1, [4] = 2, [8] = 3,
|
||||
[16]=4, [32]=5, [64]=6,
|
||||
[128]=7};
|
||||
static const uint8_t ramregs[] = {0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
|
||||
0x56, 0x57};
|
||||
device_t north = 0;
|
||||
/* for all the DRAMS, see if they are there and get the size of each
|
||||
* module. This is just a very early first cut at sizing.
|
||||
*/
|
||||
/* we may run out of registers ... */
|
||||
unsigned char width, banks, rows, cols, reg;
|
||||
unsigned char value = 0;
|
||||
unsigned char module = 0xa1 | (slot << 1);
|
||||
/* is the module there? if byte 2 is not 4, then we'll assume it
|
||||
* is useless.
|
||||
*/
|
||||
if (smbus_read_byte(module, 2) != 4)
|
||||
goto done;
|
||||
|
||||
//print_err_hex8(slot);
|
||||
// print_err(" is SDRAM\n");
|
||||
width = smbus_read_byte(module, 6) | (smbus_read_byte(module,7)<<0);
|
||||
banks = smbus_read_byte(module, 17);
|
||||
/* we're going to assume symmetric banks. Sorry. */
|
||||
cols = smbus_read_byte(module, 4) & 0xf;
|
||||
rows = smbus_read_byte(module, 3) & 0xf;
|
||||
/* grand total. You have rows+cols addressing, * times of banks, times
|
||||
* width of data in bytes*/
|
||||
/* do this in terms of address bits. Then subtract 23 from it.
|
||||
* That might do it.
|
||||
*/
|
||||
value = cols + rows + log2[banks] + log2[width];
|
||||
value -= 23;
|
||||
/* now subtract 3 more bits as these are 8-bit bytes */
|
||||
value -= 3;
|
||||
// print_err_hex8(value);
|
||||
// print_err(" is the # bits for this bank\n");
|
||||
/* now put that size into the correct register */
|
||||
value = (1 << value);
|
||||
done:
|
||||
reg = ramregs[slot];
|
||||
|
||||
// print_err_hex8(value); print_err(" would go into ");
|
||||
// print_err_hex8(ramregs[reg]); print_err("\n");
|
||||
// pci_write_config8(north, ramregs[reg], value);
|
||||
return value;
|
||||
}
|
||||
|
||||
static void sdram_set_spd_registers(const struct mem_controller *ctrl) {
|
||||
#define T133 7
|
||||
unsigned char Trp = 1, Tras = 1, casl = 2, val;
|
||||
unsigned char timing = 0xe4;
|
||||
/* read Trp */
|
||||
val = smbus_read_byte(0xa0, 27);
|
||||
if (val < 2*T133)
|
||||
Trp = 1;
|
||||
val = smbus_read_byte(0xa0, 30);
|
||||
if (val < 5*T133)
|
||||
Tras = 0;
|
||||
val = smbus_read_byte(0xa0, 18);
|
||||
if (val < 8)
|
||||
casl = 1;
|
||||
if (val < 4)
|
||||
casl = 0;
|
||||
|
||||
val = (Trp << 7) | (Tras << 6) | (casl << 4) | 4;
|
||||
|
||||
print_err_hex8(val); print_err(" is the computed timing\n");
|
||||
/* don't set it. Experience shows that this screwy chipset should just
|
||||
* be run with the most conservative timing.
|
||||
* pci_write_config8(0, 0x64, val);
|
||||
*/
|
||||
}
|
||||
|
||||
static void sdram_enable(int controllers, const struct mem_controller *ctrl) {
|
||||
unsigned char i;
|
||||
static const uint16_t raminit_ma_reg_table[] = {
|
||||
/* Values for MA type register to try */
|
||||
0x0000, 0x8088, 0xe0ee,
|
||||
0xffff // end mark
|
||||
};
|
||||
static const uint8_t ramregs[] = {0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
|
||||
0x56, 0x57};
|
||||
|
||||
device_t north = 0;
|
||||
uint8_t c, r, base;
|
||||
/* begin to initialize*/
|
||||
// I forget why we need this, but we do
|
||||
dimms_write(0xa55a5aa5);
|
||||
|
||||
/* set NOP*/
|
||||
pci_write_config8(north,0x6C, 0x01);
|
||||
print_err("NOP\r\n");
|
||||
/* wait 200us*/
|
||||
// You need to do the memory reference. That causes the nop cycle.
|
||||
dimms_read(0);
|
||||
udelay(400);
|
||||
print_err("PRECHARGE\r\n");
|
||||
/* set precharge */
|
||||
pci_write_config8(north,0x6C, 0x02);
|
||||
print_err("DUMMY READS\r\n");
|
||||
/* dummy reads*/
|
||||
dimms_read(0);
|
||||
udelay(200);
|
||||
print_err("CBR\r\n");
|
||||
/* set CBR*/
|
||||
pci_write_config8(north,0x6C, 0x04);
|
||||
do_module_size(unsigned char slot /*, unsigned char base) */)
|
||||
{
|
||||
static const unsigned char log2[256] = {
|
||||
[1] = 0, [2] = 1, [4] = 2, [8] = 3,
|
||||
[16]=4, [32]=5, [64]=6,
|
||||
[128]=7
|
||||
};
|
||||
static const uint8_t ramregs[] = {0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
|
||||
0x56, 0x57};
|
||||
device_t north = 0;
|
||||
/* for all the DRAMS, see if they are there and get the size of each
|
||||
* module. This is just a very early first cut at sizing.
|
||||
*/
|
||||
/* we may run out of registers ... */
|
||||
unsigned char width, banks, rows, cols, reg;
|
||||
unsigned char value = 0;
|
||||
unsigned char module = 0xa1 | (slot << 1);
|
||||
/* is the module there? if byte 2 is not 4, then we'll assume it
|
||||
* is useless.
|
||||
*/
|
||||
if (smbus_read_byte(module, 2) != 4)
|
||||
goto done;
|
||||
|
||||
/* do 8 reads and wait >100us between each - from via*/
|
||||
dimms_read(0);
|
||||
udelay(200);
|
||||
dimms_read(0);
|
||||
udelay(200);
|
||||
dimms_read(0);
|
||||
udelay(200);
|
||||
dimms_read(0);
|
||||
udelay(200);
|
||||
dimms_read(0);
|
||||
udelay(200);
|
||||
dimms_read(0);
|
||||
udelay(200);
|
||||
dimms_read(0);
|
||||
udelay(200);
|
||||
dimms_read(0);
|
||||
udelay(200);
|
||||
print_err("MRS\r\n");
|
||||
/* set MRS*/
|
||||
pci_write_config8(north,0x6c, 0x03);
|
||||
#if DIMM_CL2
|
||||
dimms_read(0x150);
|
||||
#else // CL=3
|
||||
dimms_read(0x1d0);
|
||||
#endif
|
||||
udelay(200);
|
||||
print_err("NORMAL\r\n");
|
||||
/* set to normal mode */
|
||||
pci_write_config8(north,0x6C, 0x08);
|
||||
|
||||
dimms_write(0x55aa55aa);
|
||||
dimms_read(0);
|
||||
udelay(200);
|
||||
print_err("set ref. rate\r\n");
|
||||
// Set the refresh rate.
|
||||
#if DIMM_PC133
|
||||
pci_write_config8(north,0x6A, 0x86);
|
||||
#else
|
||||
pci_write_config8(north,0x6A, 0x65);
|
||||
#endif
|
||||
print_err("enable multi-page open\r\n");
|
||||
// enable multi-page open
|
||||
pci_write_config8(north,0x6B, 0x0d);
|
||||
|
||||
/* Begin auto-detection
|
||||
* Find the first bank with DIMM equipped. */
|
||||
|
||||
/* Maximum possible memory in bank 0, none in other banks.
|
||||
* Starting from bank 0, we fill 0 in these registers
|
||||
* until memory is found. */
|
||||
pci_write_config8(north,0x5A, 0xff);
|
||||
pci_write_config8(north,0x5B, 0xff);
|
||||
pci_write_config8(north,0x5C, 0xff);
|
||||
pci_write_config8(north,0x5D, 0xff);
|
||||
pci_write_config8(north,0x5E, 0xff);
|
||||
pci_write_config8(north,0x5F, 0xff);
|
||||
pci_write_config8(north,0x56, 0xff);
|
||||
pci_write_config8(north,0x57, 0xff);
|
||||
dumpnorth(north);
|
||||
print_err("MA\r\n");
|
||||
for(c = 0; c < 8; c++) {
|
||||
/* Write different values to 0 and 8, then read from 0.
|
||||
* If values of address 0 match, we have something there. */
|
||||
print_err("write to 0\r\n");
|
||||
*(volatile unsigned long *) 0 = 0x12345678;
|
||||
|
||||
/* LEAVE THIS HERE. IT IS ESSENTIAL. OTHERWISE BUFFERING
|
||||
* WILL FOOL YOU!
|
||||
*/
|
||||
print_err("write to 8\r\n");
|
||||
*(volatile unsigned long *) 8 = 0x87654321;
|
||||
|
||||
if (*(volatile unsigned long *) 0 != 0x12345678) {
|
||||
print_err("no memory in this bank\r\n");
|
||||
/* No memory in this bank. Tell it to the bridge. */
|
||||
pci_write_config8(north,ramregs[c], 0);
|
||||
}
|
||||
/* found something */
|
||||
{
|
||||
uint8_t best = 0;
|
||||
|
||||
/* Detect MA mapping type of the bank. */
|
||||
|
||||
for(r = 0; r < 3; r++) {
|
||||
volatile unsigned long esi = 0;
|
||||
volatile unsigned long eax = 0;
|
||||
pci_write_config8(north,0x58, raminit_ma_reg_table[r]);
|
||||
|
||||
* (volatile unsigned long *) eax = 0;
|
||||
print_err(" done write to eax\r\n");
|
||||
// Write to addresses with only one address bit
|
||||
// on, from 0x80000000 to 0x00000008 (lower 3 bits
|
||||
// are ignored, assuming 64-bit bus). Then what
|
||||
// is read at address 0 is the value written to
|
||||
// the lowest address where it gets
|
||||
// wrap-around. That address is either the size of
|
||||
// the bank, or a missing bit due to incorrect MA
|
||||
// mapping.
|
||||
eax = 0x80000000;
|
||||
while (eax != 4) {
|
||||
* (volatile unsigned long *) eax = eax;
|
||||
//print_err_hex32(eax);
|
||||
outb(eax&0xff, 0x80);
|
||||
eax >>= 1;
|
||||
}
|
||||
print_err(" done read to eax\r\n");
|
||||
eax = * (unsigned long *)0;
|
||||
/* oh boy ... what is this.
|
||||
movl 0, %eax
|
||||
cmpl %eax, %esi
|
||||
jnc 3f
|
||||
*/
|
||||
print_err("eax and esi: ");
|
||||
print_err_hex32(eax); print_err(" ");
|
||||
print_err_hex32(esi); print_err("\r\n");
|
||||
|
||||
if (eax > esi) { /* ??*/
|
||||
|
||||
// This is the current best MA mapping.
|
||||
// Save the address and its MA mapping value.
|
||||
best = r;
|
||||
esi = eax;
|
||||
}
|
||||
}
|
||||
|
||||
pci_write_config8(north,0x58, raminit_ma_reg_table[best]);
|
||||
print_err("enabled first bank of ram ... ma is ");
|
||||
print_err_hex8(pci_read_config8(north, 0x58));
|
||||
print_err("\r\n");
|
||||
}
|
||||
}
|
||||
base = 0;
|
||||
/* runs out of variable space. */
|
||||
/* this is unrolled and constants used as much as possible to help
|
||||
* us not run out of registers.
|
||||
* we'll run out of code space instead :-)
|
||||
*/
|
||||
// for(i = 0; i < 8; i++)
|
||||
base = do_module_size(0); /*, base);*/
|
||||
pci_write_config8(north, ramregs[0], base);
|
||||
base = do_module_size(1); /*, base);*/
|
||||
base += pci_read_config8(north, ramregs[0]);
|
||||
pci_write_config8(north, ramregs[1], base);
|
||||
/* runs out of code space. */
|
||||
for(i = 0; i < 8; i++){
|
||||
pci_write_config8(north, ramregs[i], base);
|
||||
/*
|
||||
pci_write_config8(north, ramregs[3], base);
|
||||
pci_write_config8(north, ramregs[4], base);
|
||||
pci_write_config8(north, ramregs[5], base);
|
||||
pci_write_config8(north, ramregs[6], base);
|
||||
pci_write_config8(north, ramregs[7], base);
|
||||
*/
|
||||
}
|
||||
/*
|
||||
base = do_module_size(0xa0, base);
|
||||
base = do_module_size(0xa0, base);
|
||||
base = do_module_size(0xa0, base);
|
||||
base = do_module_size(0xa0, base);
|
||||
base = do_module_size(0xa0, base);
|
||||
base = do_module_size(0xa0, base);*/
|
||||
print_err("vt8601 done\n");
|
||||
dumpnorth(north);
|
||||
udelay(1000);
|
||||
//print_err_hex8(slot);
|
||||
// print_err(" is SDRAM\n");
|
||||
width = smbus_read_byte(module, 6) | (smbus_read_byte(module,7)<<0);
|
||||
banks = smbus_read_byte(module, 17);
|
||||
/* we're going to assume symmetric banks. Sorry. */
|
||||
cols = smbus_read_byte(module, 4) & 0xf;
|
||||
rows = smbus_read_byte(module, 3) & 0xf;
|
||||
/* grand total. You have rows+cols addressing, * times of banks, times
|
||||
* width of data in bytes*/
|
||||
/* do this in terms of address bits. Then subtract 23 from it.
|
||||
* That might do it.
|
||||
*/
|
||||
value = cols + rows + log2[banks] + log2[width];
|
||||
value -= 23;
|
||||
/* now subtract 3 more bits as these are 8-bit bytes */
|
||||
value -= 3;
|
||||
// print_err_hex8(value);
|
||||
// print_err(" is the # bits for this bank\n");
|
||||
/* now put that size into the correct register */
|
||||
value = (1 << value);
|
||||
done:
|
||||
reg = ramregs[slot];
|
||||
|
||||
// print_err_hex8(value); print_err(" would go into ");
|
||||
// print_err_hex8(ramregs[reg]); print_err("\n");
|
||||
// pci_write_config8(north, ramregs[reg], value);
|
||||
return value;
|
||||
}
|
||||
|
||||
static void sdram_set_spd_registers(const struct mem_controller *ctrl)
|
||||
{
|
||||
#define T133 7
|
||||
unsigned char Trp = 1, Tras = 1, casl = 2, val;
|
||||
unsigned char timing = 0xe4;
|
||||
/* read Trp */
|
||||
val = smbus_read_byte(0xa0, 27);
|
||||
if (val < 2*T133)
|
||||
Trp = 1;
|
||||
val = smbus_read_byte(0xa0, 30);
|
||||
if (val < 5*T133)
|
||||
Tras = 0;
|
||||
val = smbus_read_byte(0xa0, 18);
|
||||
if (val < 8)
|
||||
casl = 1;
|
||||
if (val < 4)
|
||||
casl = 0;
|
||||
|
||||
val = (Trp << 7) | (Tras << 6) | (casl << 4) | 4;
|
||||
|
||||
print_err_hex8(val); print_err(" is the computed timing\n");
|
||||
/* don't set it. Experience shows that this screwy chipset should just
|
||||
* be run with the most conservative timing.
|
||||
* pci_write_config8(0, 0x64, val);
|
||||
*/
|
||||
}
|
||||
|
||||
static void sdram_enable(int controllers, const struct mem_controller *ctrl)
|
||||
{
|
||||
unsigned char i;
|
||||
static const uint16_t raminit_ma_reg_table[] = {
|
||||
/* Values for MA type register to try */
|
||||
0x0000, 0x8088, 0xe0ee,
|
||||
0xffff // end mark
|
||||
};
|
||||
static const uint8_t ramregs[] = {
|
||||
0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x56, 0x57
|
||||
};
|
||||
|
||||
device_t north = 0;
|
||||
uint8_t c, r, base;
|
||||
/* begin to initialize*/
|
||||
// I forget why we need this, but we do
|
||||
dimms_write(0xa55a5aa5);
|
||||
|
||||
/* set NOP*/
|
||||
pci_write_config8(north,0x6C, 0x01);
|
||||
print_err("NOP\r\n");
|
||||
/* wait 200us*/
|
||||
// You need to do the memory reference. That causes the nop cycle.
|
||||
dimms_read(0);
|
||||
udelay(400);
|
||||
print_err("PRECHARGE\r\n");
|
||||
/* set precharge */
|
||||
pci_write_config8(north,0x6C, 0x02);
|
||||
print_err("DUMMY READS\r\n");
|
||||
/* dummy reads*/
|
||||
dimms_read(0);
|
||||
udelay(200);
|
||||
print_err("CBR\r\n");
|
||||
/* set CBR*/
|
||||
pci_write_config8(north,0x6C, 0x04);
|
||||
|
||||
/* do 8 reads and wait >100us between each - from via*/
|
||||
dimms_read(0);
|
||||
udelay(200);
|
||||
dimms_read(0);
|
||||
udelay(200);
|
||||
dimms_read(0);
|
||||
udelay(200);
|
||||
dimms_read(0);
|
||||
udelay(200);
|
||||
dimms_read(0);
|
||||
udelay(200);
|
||||
dimms_read(0);
|
||||
udelay(200);
|
||||
dimms_read(0);
|
||||
udelay(200);
|
||||
dimms_read(0);
|
||||
udelay(200);
|
||||
print_err("MRS\r\n");
|
||||
/* set MRS*/
|
||||
pci_write_config8(north,0x6c, 0x03);
|
||||
#if DIMM_CL2
|
||||
dimms_read(0x150);
|
||||
#else // CL=3
|
||||
dimms_read(0x1d0);
|
||||
#endif
|
||||
udelay(200);
|
||||
print_err("NORMAL\r\n");
|
||||
/* set to normal mode */
|
||||
pci_write_config8(north,0x6C, 0x08);
|
||||
|
||||
dimms_write(0x55aa55aa);
|
||||
dimms_read(0);
|
||||
udelay(200);
|
||||
print_err("set ref. rate\r\n");
|
||||
// Set the refresh rate.
|
||||
#if DIMM_PC133
|
||||
pci_write_config8(north,0x6A, 0x86);
|
||||
#else
|
||||
pci_write_config8(north,0x6A, 0x65);
|
||||
#endif
|
||||
print_err("enable multi-page open\r\n");
|
||||
// enable multi-page open
|
||||
pci_write_config8(north,0x6B, 0x0d);
|
||||
|
||||
/* Begin auto-detection
|
||||
* Find the first bank with DIMM equipped. */
|
||||
|
||||
/* Maximum possible memory in bank 0, none in other banks.
|
||||
* Starting from bank 0, we fill 0 in these registers
|
||||
* until memory is found. */
|
||||
pci_write_config8(north,0x5A, 0xff);
|
||||
pci_write_config8(north,0x5B, 0xff);
|
||||
pci_write_config8(north,0x5C, 0xff);
|
||||
pci_write_config8(north,0x5D, 0xff);
|
||||
pci_write_config8(north,0x5E, 0xff);
|
||||
pci_write_config8(north,0x5F, 0xff);
|
||||
pci_write_config8(north,0x56, 0xff);
|
||||
pci_write_config8(north,0x57, 0xff);
|
||||
dumpnorth(north);
|
||||
print_err("MA\r\n");
|
||||
for(c = 0; c < 8; c++) {
|
||||
/* Write different values to 0 and 8, then read from 0.
|
||||
* If values of address 0 match, we have something there. */
|
||||
print_err("write to 0\r\n");
|
||||
*(volatile unsigned long *) 0 = 0x12345678;
|
||||
|
||||
/* LEAVE THIS HERE. IT IS ESSENTIAL. OTHERWISE BUFFERING
|
||||
* WILL FOOL YOU!
|
||||
*/
|
||||
print_err("write to 8\r\n");
|
||||
*(volatile unsigned long *) 8 = 0x87654321;
|
||||
|
||||
if (*(volatile unsigned long *) 0 != 0x12345678) {
|
||||
print_err("no memory in this bank\r\n");
|
||||
/* No memory in this bank. Tell it to the bridge. */
|
||||
pci_write_config8(north,ramregs[c], 0);
|
||||
}
|
||||
/* found something */
|
||||
{
|
||||
uint8_t best = 0;
|
||||
|
||||
/* Detect MA mapping type of the bank. */
|
||||
|
||||
for(r = 0; r < 3; r++) {
|
||||
volatile unsigned long esi = 0;
|
||||
volatile unsigned long eax = 0;
|
||||
pci_write_config8(north,0x58, raminit_ma_reg_table[r]);
|
||||
|
||||
* (volatile unsigned long *) eax = 0;
|
||||
print_err(" done write to eax\r\n");
|
||||
// Write to addresses with only one address bit
|
||||
// on, from 0x80000000 to 0x00000008 (lower 3 bits
|
||||
// are ignored, assuming 64-bit bus). Then what
|
||||
// is read at address 0 is the value written to
|
||||
// the lowest address where it gets
|
||||
// wrap-around. That address is either the size of
|
||||
// the bank, or a missing bit due to incorrect MA
|
||||
// mapping.
|
||||
eax = 0x80000000;
|
||||
while (eax != 4) {
|
||||
* (volatile unsigned long *) eax = eax;
|
||||
//print_err_hex32(eax);
|
||||
outb(eax&0xff, 0x80);
|
||||
eax >>= 1;
|
||||
}
|
||||
print_err(" done read to eax\r\n");
|
||||
eax = * (unsigned long *)0;
|
||||
/* oh boy ... what is this.
|
||||
movl 0, %eax
|
||||
cmpl %eax, %esi
|
||||
jnc 3f
|
||||
*/
|
||||
print_err("eax and esi: ");
|
||||
print_err_hex32(eax); print_err(" ");
|
||||
print_err_hex32(esi); print_err("\r\n");
|
||||
|
||||
if (eax > esi) { /* ??*/
|
||||
|
||||
// This is the current best MA mapping.
|
||||
// Save the address and its MA mapping value.
|
||||
best = r;
|
||||
esi = eax;
|
||||
}
|
||||
}
|
||||
|
||||
pci_write_config8(north,0x58, raminit_ma_reg_table[best]);
|
||||
print_err("enabled first bank of ram ... ma is ");
|
||||
print_err_hex8(pci_read_config8(north, 0x58));
|
||||
print_err("\r\n");
|
||||
}
|
||||
}
|
||||
base = 0;
|
||||
/* runs out of variable space. */
|
||||
/* this is unrolled and constants used as much as possible to help
|
||||
* us not run out of registers.
|
||||
* we'll run out of code space instead :-)
|
||||
*/
|
||||
// for(i = 0; i < 8; i++)
|
||||
base = do_module_size(0); /*, base);*/
|
||||
pci_write_config8(north, ramregs[0], base);
|
||||
base = do_module_size(1); /*, base);*/
|
||||
base += pci_read_config8(north, ramregs[0]);
|
||||
pci_write_config8(north, ramregs[1], base);
|
||||
/* runs out of code space. */
|
||||
for(i = 0; i < 8; i++){
|
||||
pci_write_config8(north, ramregs[i], base);
|
||||
/*
|
||||
pci_write_config8(north, ramregs[3], base);
|
||||
pci_write_config8(north, ramregs[4], base);
|
||||
pci_write_config8(north, ramregs[5], base);
|
||||
pci_write_config8(north, ramregs[6], base);
|
||||
pci_write_config8(north, ramregs[7], base);
|
||||
*/
|
||||
}
|
||||
/*
|
||||
base = do_module_size(0xa0, base);
|
||||
base = do_module_size(0xa0, base);
|
||||
base = do_module_size(0xa0, base);
|
||||
base = do_module_size(0xa0, base);
|
||||
base = do_module_size(0xa0, base);
|
||||
base = do_module_size(0xa0, base);*/
|
||||
print_err("vt8601 done\n");
|
||||
dumpnorth(north);
|
||||
udelay(1000);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
#define RAMINIT_H
|
||||
|
||||
struct mem_controller {
|
||||
int empty;
|
||||
int empty;
|
||||
};
|
||||
|
||||
#endif /* RAMINIT_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue