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- Modify the code to C style indenting. 

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1180 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Eric Biederman 2003-10-03 02:53:02 +00:00
parent fae510cd84
commit 5ebf4d3431
3 changed files with 469 additions and 455 deletions
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144
src/mainboard/via/epia/auto.c
View File

@ -13,10 +13,11 @@
#include "northbridge/via/vt8601/raminit.h" #include "northbridge/via/vt8601/raminit.h"
/* /*
*/ */
void udelay(int usecs) { void udelay(int usecs)
int i; {
for(i = 0; i < usecs; i++) int i;
outb(i&0xff, 0x80); for(i = 0; i < usecs; i++)
outb(i&0xff, 0x80);
} }
#include "lib/delay.c" #include "lib/delay.c"
@ -40,9 +41,9 @@ static void memreset_setup(void)
*/ */
static inline int spd_read_byte(unsigned device, unsigned address) static inline int spd_read_byte(unsigned device, unsigned address)
{ {
unsigned char c; unsigned char c;
c = smbus_read_byte(device, address); c = smbus_read_byte(device, address);
return c; return c;
} }
@ -52,84 +53,85 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "sdram/generic_sdram.c" #include "sdram/generic_sdram.c"
*/ */
static void static void enable_mainboard_devices(void)
enable_mainboard_devices(void) { {
device_t dev; device_t dev;
/* dev 0 for southbridge */ /* dev 0 for southbridge */
dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0); dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0);
if (dev == PCI_DEV_INVALID) { if (dev == PCI_DEV_INVALID) {
die("Southbridge not found!!!\n"); die("Southbridge not found!!!\n");
} }
pci_write_config8(dev, 0x50, 7); pci_write_config8(dev, 0x50, 7);
pci_write_config8(dev, 0x51, 0xff); pci_write_config8(dev, 0x51, 0xff);
#if 0 #if 0
// This early setup switches IDE into compatibility mode before PCI gets // This early setup switches IDE into compatibility mode before PCI gets
// // a chance to assign I/Os // // a chance to assign I/Os
// movl $CONFIG_ADDR(0, 0x89, 0x42), %eax // movl $CONFIG_ADDR(0, 0x89, 0x42), %eax
// // movb $0x09, %dl // // movb $0x09, %dl
// movb $0x00, %dl // movb $0x00, %dl
// PCI_WRITE_CONFIG_BYTE // PCI_WRITE_CONFIG_BYTE
// //
#endif #endif
/* we do this here as in V2, we can not yet do raw operations /* we do this here as in V2, we can not yet do raw operations
* to pci! * to pci!
*/ */
dev++; /* ICKY */ dev++; /* ICKY */
pci_write_config8(dev, 0x42, 0); pci_write_config8(dev, 0x42, 0);
} }
static void static void enable_shadow_ram(void)
enable_shadow_ram(void) { {
device_t dev = 0; /* no need to look up 0:0.0 */ device_t dev = 0; /* no need to look up 0:0.0 */
unsigned char shadowreg; unsigned char shadowreg;
/* dev 0 for southbridge */ /* dev 0 for southbridge */
shadowreg = pci_read_config8(dev, 0x63); shadowreg = pci_read_config8(dev, 0x63);
/* 0xf0000-0xfffff */ /* 0xf0000-0xfffff */
shadowreg |= 0x30; shadowreg |= 0x30;
pci_write_config8(dev, 0x63, shadowreg); pci_write_config8(dev, 0x63, shadowreg);
} }
static void main(void) static void main(void)
{ {
unsigned long x; unsigned long x;
/* init_timer();*/ /* init_timer();*/
outb(5, 0x80); outb(5, 0x80);
enable_vt8231_serial();
enable_mainboard_devices();
uart_init();
console_init();
enable_smbus(); enable_vt8231_serial();
enable_shadow_ram(); enable_mainboard_devices();
/* uart_init();
memreset_setup(); console_init();
this is way more generic than we need.
sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); enable_smbus();
*/ enable_shadow_ram();
sdram_set_registers((const struct mem_controller *) 0); /*
sdram_set_spd_registers((const struct mem_controller *) 0); memreset_setup();
sdram_enable(0, (const struct mem_controller *) 0); this is way more generic than we need.
sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
/* Check all of memory */ */
sdram_set_registers((const struct mem_controller *) 0);
sdram_set_spd_registers((const struct mem_controller *) 0);
sdram_enable(0, (const struct mem_controller *) 0);
/* Check all of memory */
#if 0 #if 0
ram_check(0x00000000, msr.lo); ram_check(0x00000000, msr.lo);
#endif #endif
#if 0 #if 0
static const struct { static const struct {
unsigned long lo, hi; unsigned long lo, hi;
} check_addrs[] = { } check_addrs[] = {
/* Check 16MB of memory @ 0*/ /* Check 16MB of memory @ 0*/
{ 0x00000000, 0x01000000 }, { 0x00000000, 0x01000000 },
#if TOTAL_CPUS > 1 #if TOTAL_CPUS > 1
/* Check 16MB of memory @ 2GB */ /* Check 16MB of memory @ 2GB */
{ 0x80000000, 0x81000000 }, { 0x80000000, 0x81000000 },
#endif #endif
}; };
int i; int i;
for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) { for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) {
ram_check(check_addrs[i].lo, check_addrs[i].hi); ram_check(check_addrs[i].lo, check_addrs[i].hi);
} }
#endif #endif
} }

778
src/northbridge/via/vt8601/raminit.c
View File

@ -47,424 +47,436 @@ it with the version available from LANL.
#define DIMM_CL2 0 #define DIMM_CL2 0
#endif #endif
void dimms_read(unsigned long x) { void dimms_read(unsigned long x)
uint8_t c; {
unsigned long eax; uint8_t c;
volatile unsigned long y; unsigned long eax;
eax = x; volatile unsigned long y;
for(c = 0; c < 6; c++) { eax = x;
for(c = 0; c < 6; c++) {
print_err("dimms_read: ");
print_err_hex32(eax); print_err("dimms_read: ");
print_err("\r\n"); print_err_hex32(eax);
y = * (volatile unsigned long *) eax; print_err("\r\n");
eax += 0x10000000; y = * (volatile unsigned long *) eax;
} eax += 0x10000000;
}
} }
void dimms_write(int x) { void dimms_write(int x)
uint8_t c; {
unsigned long eax = x; uint8_t c;
for(c = 0; c < 6; c++) { unsigned long eax = x;
print_err("dimms_write: "); for(c = 0; c < 6; c++) {
print_err_hex32(eax); print_err("dimms_write: ");
print_err("\r\n"); print_err_hex32(eax);
*(volatile unsigned long *) eax = 0; print_err("\r\n");
eax += 0x10000000; *(volatile unsigned long *) eax = 0;
} eax += 0x10000000;
}
} }
#ifdef DEBUG_SETNORTHB #ifdef DEBUG_SETNORTHB
void setnorthb(device_t north, uint8_t reg, uint8_t val) { void setnorthb(device_t north, uint8_t reg, uint8_t val)
print_err("setnorth: reg "); {
print_err_hex8(reg); print_err("setnorth: reg ");
print_err(" to "); print_err_hex8(reg);
print_err_hex8(val); print_err(" to ");
print_err("\r\n"); print_err_hex8(val);
pci_write_config8(north, reg, val); print_err("\r\n");
pci_write_config8(north, reg, val);
} }
#else #else
#define setnorthb pci_write_config8 #define setnorthb pci_write_config8
#endif #endif
void void
dumpnorth(device_t north) { dumpnorth(device_t north)
uint8_t r, c; {
for(r = 0; r < 256; r += 16) { uint8_t r, c;
print_err_hex8(r); for(r = 0; r < 256; r += 16) {
print_err(":"); print_err_hex8(r);
for(c = 0; c < 16; c++) { print_err(":");
print_err_hex8(pci_read_config8(north, r+c)); for(c = 0; c < 16; c++) {
print_err(" "); print_err_hex8(pci_read_config8(north, r+c));
} print_err(" ");
print_err("\r\n"); }
print_err("\r\n");
} }
} }
static void sdram_set_registers(const struct mem_controller *ctrl) {
static const uint16_t raminit_ma_reg_table[] = { static void sdram_set_registers(const struct mem_controller *ctrl)
/* Values for MA type register to try */ {
0x0000, 0x8088, 0xe0ee, static const uint16_t raminit_ma_reg_table[] = {
0xffff // end mark /* Values for MA type register to try */
}; 0x0000, 0x8088, 0xe0ee,
static const unsigned char ramregs[] = {0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0xffff // end mark
};
static const unsigned char ramregs[] = {0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
0x56, 0x57}; 0x56, 0x57};
device_t north = (device_t) 0; device_t north = (device_t) 0;
uint8_t c, r; uint8_t c, r;
print_err("vt8601 init starting\n"); print_err("vt8601 init starting\n");
north = pci_locate_device(PCI_ID(0x1106, 0x8601), 0); north = pci_locate_device(PCI_ID(0x1106, 0x8601), 0);
north = 0; north = 0;
print_err_hex32(north); print_err_hex32(north);
print_err(" is the north\n"); print_err(" is the north\n");
print_err_hex16(pci_read_config16(north, 0)); print_err_hex16(pci_read_config16(north, 0));
print_err(" "); print_err(" ");
print_err_hex16(pci_read_config16(north, 2)); print_err_hex16(pci_read_config16(north, 2));
print_err("\r\n"); print_err("\r\n");
/* All we are doing now is setting initial known-good values that will /* All we are doing now is setting initial known-good values that will
* be revised later as we read SPD * be revised later as we read SPD
*/ */
// memory clk enable. We are not using ECC // memory clk enable. We are not using ECC
pci_write_config8(north,0x78, 0x01); pci_write_config8(north,0x78, 0x01);
print_err_hex8(pci_read_config8(north, 0x78)); print_err_hex8(pci_read_config8(north, 0x78));
// dram control, see the book. // dram control, see the book.
#if DIMM_PC133 #if DIMM_PC133
pci_write_config8(north,0x68, 0x52); pci_write_config8(north,0x68, 0x52);
#else #else
pci_write_config8(north,0x68, 0x42); pci_write_config8(north,0x68, 0x42);
#endif #endif
// dram control, see the book. // dram control, see the book.
pci_write_config8(north,0x6B, 0x0c); pci_write_config8(north,0x6B, 0x0c);
// Initial setting, 256MB in each bank, will be rewritten later. // Initial setting, 256MB in each bank, will be rewritten later.
pci_write_config8(north,0x5A, 0x20); pci_write_config8(north,0x5A, 0x20);
print_err_hex8(pci_read_config8(north, 0x5a)); print_err_hex8(pci_read_config8(north, 0x5a));
pci_write_config8(north,0x5B, 0x40); pci_write_config8(north,0x5B, 0x40);
pci_write_config8(north,0x5C, 0x60); pci_write_config8(north,0x5C, 0x60);
pci_write_config8(north,0x5D, 0x80); pci_write_config8(north,0x5D, 0x80);
pci_write_config8(north,0x5E, 0xA0); pci_write_config8(north,0x5E, 0xA0);
pci_write_config8(north,0x5F, 0xC0); pci_write_config8(north,0x5F, 0xC0);
// It seems we have to take care of these 2 registers as if // It seems we have to take care of these 2 registers as if
// they are bank 6 and 7. // they are bank 6 and 7.
pci_write_config8(north,0x56, 0xC0); pci_write_config8(north,0x56, 0xC0);
pci_write_config8(north,0x57, 0xC0); pci_write_config8(north,0x57, 0xC0);
// SDRAM in all banks // SDRAM in all banks
pci_write_config8(north,0x60, 0x3F); pci_write_config8(north,0x60, 0x3F);
// DRAM timing. I'm suspicious of this // DRAM timing. I'm suspicious of this
// This is for all banks, 64 is 0,1. 65 is 2,3. 66 is 4,5. // This is for all banks, 64 is 0,1. 65 is 2,3. 66 is 4,5.
// ras precharge 4T, RAS pulse 5T // ras precharge 4T, RAS pulse 5T
// cas2 is 0xd6, cas3 is 0xe6 // cas2 is 0xd6, cas3 is 0xe6
// we're also backing off write pulse width to 2T, so result is 0xee // we're also backing off write pulse width to 2T, so result is 0xee
#if DIMM_CL2 #if DIMM_CL2
pci_write_config8(north,0x64, 0xd4); pci_write_config8(north,0x64, 0xd4);
pci_write_config8(north,0x65, 0xd4); pci_write_config8(north,0x65, 0xd4);
pci_write_config8(north,0x66, 0xd4); pci_write_config8(north,0x66, 0xd4);
#else // CL=3 #else // CL=3
pci_write_config8(north,0x64, 0xe4); pci_write_config8(north,0x64, 0xe4);
pci_write_config8(north,0x65, 0xe4); pci_write_config8(north,0x65, 0xe4);
pci_write_config8(north,0x66, 0xe4); pci_write_config8(north,0x66, 0xe4);
#endif #endif
// dram frequency select. // dram frequency select.
// enable 4K pages for 64M dram. // enable 4K pages for 64M dram.
#if DIMM_PC133 #if DIMM_PC133
pci_write_config8(north,0x69, 0x3c); pci_write_config8(north,0x69, 0x3c);
#else #else
pci_write_config8(north,0x69, 0xac); pci_write_config8(north,0x69, 0xac);
#endif #endif
/* IMPORTANT -- disable refresh counter */ /* IMPORTANT -- disable refresh counter */
// refresh counter, disabled. // refresh counter, disabled.
pci_write_config8(north,0x6A, 0x00); pci_write_config8(north,0x6A, 0x00);
// clkenable configuration. kevinh FIXME - add precharge
pci_write_config8(north,0x6C, 0x00);
// dram read latch delay of 1 ns, MD drive 8 mA,
// high drive strength on MA[2: 13], we#, cas#, ras#
// As per Cindy Lee, set to 0x37, not 0x57
pci_write_config8(north,0x6D, 0x7f);
// clkenable configuration. kevinh FIXME - add precharge /* Initialize all banks at once */
pci_write_config8(north,0x6C, 0x00);
// dram read latch delay of 1 ns, MD drive 8 mA,
// high drive strength on MA[2: 13], we#, cas#, ras#
// As per Cindy Lee, set to 0x37, not 0x57
pci_write_config8(north,0x6D, 0x7f);
/* Initialize all banks at once */
} }
/* slot is the dram slot. Base is the *8M base. */ /* slot is the dram slot. Base is the *8M base. */
static unsigned char static unsigned char
do_module_size(unsigned char slot) { /*, unsigned char base) */ do_module_size(unsigned char slot /*, unsigned char base) */)
static const unsigned char log2[256] = {[1] = 0, [2] = 1, [4] = 2, [8] = 3, {
[16]=4, [32]=5, [64]=6, static const unsigned char log2[256] = {
[128]=7}; [1] = 0, [2] = 1, [4] = 2, [8] = 3,
static const uint8_t ramregs[] = {0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, [16]=4, [32]=5, [64]=6,
0x56, 0x57}; [128]=7
device_t north = 0; };
/* for all the DRAMS, see if they are there and get the size of each static const uint8_t ramregs[] = {0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
* module. This is just a very early first cut at sizing. 0x56, 0x57};
*/ device_t north = 0;
/* we may run out of registers ... */ /* for all the DRAMS, see if they are there and get the size of each
unsigned char width, banks, rows, cols, reg; * module. This is just a very early first cut at sizing.
unsigned char value = 0; */
unsigned char module = 0xa1 | (slot << 1); /* we may run out of registers ... */
/* is the module there? if byte 2 is not 4, then we'll assume it unsigned char width, banks, rows, cols, reg;
* is useless. unsigned char value = 0;
*/ unsigned char module = 0xa1 | (slot << 1);
if (smbus_read_byte(module, 2) != 4) /* is the module there? if byte 2 is not 4, then we'll assume it
goto done; * is useless.
*/
//print_err_hex8(slot); if (smbus_read_byte(module, 2) != 4)
// print_err(" is SDRAM\n"); goto done;
width = smbus_read_byte(module, 6) | (smbus_read_byte(module,7)<<0);
banks = smbus_read_byte(module, 17);
/* we're going to assume symmetric banks. Sorry. */
cols = smbus_read_byte(module, 4) & 0xf;
rows = smbus_read_byte(module, 3) & 0xf;
/* grand total. You have rows+cols addressing, * times of banks, times
* width of data in bytes*/
/* do this in terms of address bits. Then subtract 23 from it.
* That might do it.
*/
value = cols + rows + log2[banks] + log2[width];
value -= 23;
/* now subtract 3 more bits as these are 8-bit bytes */
value -= 3;
// print_err_hex8(value);
// print_err(" is the # bits for this bank\n");
/* now put that size into the correct register */
value = (1 << value);
done:
reg = ramregs[slot];
// print_err_hex8(value); print_err(" would go into ");
// print_err_hex8(ramregs[reg]); print_err("\n");
// pci_write_config8(north, ramregs[reg], value);
return value;
}
static void sdram_set_spd_registers(const struct mem_controller *ctrl) {
#define T133 7
unsigned char Trp = 1, Tras = 1, casl = 2, val;
unsigned char timing = 0xe4;
/* read Trp */
val = smbus_read_byte(0xa0, 27);
if (val < 2*T133)
Trp = 1;
val = smbus_read_byte(0xa0, 30);
if (val < 5*T133)
Tras = 0;
val = smbus_read_byte(0xa0, 18);
if (val < 8)
casl = 1;
if (val < 4)
casl = 0;
val = (Trp << 7) | (Tras << 6) | (casl << 4) | 4;
print_err_hex8(val); print_err(" is the computed timing\n");
/* don't set it. Experience shows that this screwy chipset should just
* be run with the most conservative timing.
* pci_write_config8(0, 0x64, val);
*/
}
static void sdram_enable(int controllers, const struct mem_controller *ctrl) {
unsigned char i;
static const uint16_t raminit_ma_reg_table[] = {
/* Values for MA type register to try */
0x0000, 0x8088, 0xe0ee,
0xffff // end mark
};
static const uint8_t ramregs[] = {0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
0x56, 0x57};
device_t north = 0;
uint8_t c, r, base;
/* begin to initialize*/
// I forget why we need this, but we do
dimms_write(0xa55a5aa5);
/* set NOP*/
pci_write_config8(north,0x6C, 0x01);
print_err("NOP\r\n");
/* wait 200us*/
// You need to do the memory reference. That causes the nop cycle.
dimms_read(0);
udelay(400);
print_err("PRECHARGE\r\n");
/* set precharge */
pci_write_config8(north,0x6C, 0x02);
print_err("DUMMY READS\r\n");
/* dummy reads*/
dimms_read(0);
udelay(200);
print_err("CBR\r\n");
/* set CBR*/
pci_write_config8(north,0x6C, 0x04);
/* do 8 reads and wait >100us between each - from via*/ //print_err_hex8(slot);
dimms_read(0); // print_err(" is SDRAM\n");
udelay(200); width = smbus_read_byte(module, 6) | (smbus_read_byte(module,7)<<0);
dimms_read(0); banks = smbus_read_byte(module, 17);
udelay(200); /* we're going to assume symmetric banks. Sorry. */
dimms_read(0); cols = smbus_read_byte(module, 4) & 0xf;
udelay(200); rows = smbus_read_byte(module, 3) & 0xf;
dimms_read(0); /* grand total. You have rows+cols addressing, * times of banks, times
udelay(200); * width of data in bytes*/
dimms_read(0); /* do this in terms of address bits. Then subtract 23 from it.
udelay(200); * That might do it.
dimms_read(0); */
udelay(200); value = cols + rows + log2[banks] + log2[width];
dimms_read(0); value -= 23;
udelay(200); /* now subtract 3 more bits as these are 8-bit bytes */
dimms_read(0); value -= 3;
udelay(200); // print_err_hex8(value);
print_err("MRS\r\n"); // print_err(" is the # bits for this bank\n");
/* set MRS*/ /* now put that size into the correct register */
pci_write_config8(north,0x6c, 0x03); value = (1 << value);
#if DIMM_CL2 done:
dimms_read(0x150); reg = ramregs[slot];
#else // CL=3
dimms_read(0x1d0); // print_err_hex8(value); print_err(" would go into ");
#endif // print_err_hex8(ramregs[reg]); print_err("\n");
udelay(200); // pci_write_config8(north, ramregs[reg], value);
print_err("NORMAL\r\n"); return value;
/* set to normal mode */ }
pci_write_config8(north,0x6C, 0x08);
static void sdram_set_spd_registers(const struct mem_controller *ctrl)
dimms_write(0x55aa55aa); {
dimms_read(0); #define T133 7
udelay(200); unsigned char Trp = 1, Tras = 1, casl = 2, val;
print_err("set ref. rate\r\n"); unsigned char timing = 0xe4;
// Set the refresh rate. /* read Trp */
#if DIMM_PC133 val = smbus_read_byte(0xa0, 27);
pci_write_config8(north,0x6A, 0x86); if (val < 2*T133)
#else Trp = 1;
pci_write_config8(north,0x6A, 0x65); val = smbus_read_byte(0xa0, 30);
#endif if (val < 5*T133)
print_err("enable multi-page open\r\n"); Tras = 0;
// enable multi-page open val = smbus_read_byte(0xa0, 18);
pci_write_config8(north,0x6B, 0x0d); if (val < 8)
casl = 1;
/* Begin auto-detection if (val < 4)
* Find the first bank with DIMM equipped. */ casl = 0;
/* Maximum possible memory in bank 0, none in other banks. val = (Trp << 7) | (Tras << 6) | (casl << 4) | 4;
* Starting from bank 0, we fill 0 in these registers
* until memory is found. */ print_err_hex8(val); print_err(" is the computed timing\n");
pci_write_config8(north,0x5A, 0xff); /* don't set it. Experience shows that this screwy chipset should just
pci_write_config8(north,0x5B, 0xff); * be run with the most conservative timing.
pci_write_config8(north,0x5C, 0xff); * pci_write_config8(0, 0x64, val);
pci_write_config8(north,0x5D, 0xff); */
pci_write_config8(north,0x5E, 0xff); }
pci_write_config8(north,0x5F, 0xff);
pci_write_config8(north,0x56, 0xff); static void sdram_enable(int controllers, const struct mem_controller *ctrl)
pci_write_config8(north,0x57, 0xff); {
dumpnorth(north); unsigned char i;
print_err("MA\r\n"); static const uint16_t raminit_ma_reg_table[] = {
for(c = 0; c < 8; c++) { /* Values for MA type register to try */
/* Write different values to 0 and 8, then read from 0. 0x0000, 0x8088, 0xe0ee,
* If values of address 0 match, we have something there. */ 0xffff // end mark
print_err("write to 0\r\n"); };
*(volatile unsigned long *) 0 = 0x12345678; static const uint8_t ramregs[] = {
0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x56, 0x57
/* LEAVE THIS HERE. IT IS ESSENTIAL. OTHERWISE BUFFERING };
* WILL FOOL YOU!
*/ device_t north = 0;
print_err("write to 8\r\n"); uint8_t c, r, base;
*(volatile unsigned long *) 8 = 0x87654321; /* begin to initialize*/
// I forget why we need this, but we do
if (*(volatile unsigned long *) 0 != 0x12345678) { dimms_write(0xa55a5aa5);
print_err("no memory in this bank\r\n");
/* No memory in this bank. Tell it to the bridge. */ /* set NOP*/
pci_write_config8(north,ramregs[c], 0); pci_write_config8(north,0x6C, 0x01);
} print_err("NOP\r\n");
/* found something */ /* wait 200us*/
{ // You need to do the memory reference. That causes the nop cycle.
uint8_t best = 0; dimms_read(0);
udelay(400);
/* Detect MA mapping type of the bank. */ print_err("PRECHARGE\r\n");
/* set precharge */
for(r = 0; r < 3; r++) { pci_write_config8(north,0x6C, 0x02);
volatile unsigned long esi = 0; print_err("DUMMY READS\r\n");
volatile unsigned long eax = 0; /* dummy reads*/
pci_write_config8(north,0x58, raminit_ma_reg_table[r]); dimms_read(0);
udelay(200);
* (volatile unsigned long *) eax = 0; print_err("CBR\r\n");
print_err(" done write to eax\r\n"); /* set CBR*/
// Write to addresses with only one address bit pci_write_config8(north,0x6C, 0x04);
// on, from 0x80000000 to 0x00000008 (lower 3 bits
// are ignored, assuming 64-bit bus). Then what /* do 8 reads and wait >100us between each - from via*/
// is read at address 0 is the value written to dimms_read(0);
// the lowest address where it gets udelay(200);
// wrap-around. That address is either the size of dimms_read(0);
// the bank, or a missing bit due to incorrect MA udelay(200);
// mapping. dimms_read(0);
eax = 0x80000000; udelay(200);
while (eax != 4) { dimms_read(0);
* (volatile unsigned long *) eax = eax; udelay(200);
//print_err_hex32(eax); dimms_read(0);
outb(eax&0xff, 0x80); udelay(200);
eax >>= 1; dimms_read(0);
} udelay(200);
print_err(" done read to eax\r\n"); dimms_read(0);
eax = * (unsigned long *)0; udelay(200);
/* oh boy ... what is this. dimms_read(0);
movl 0, %eax udelay(200);
cmpl %eax, %esi print_err("MRS\r\n");
jnc 3f /* set MRS*/
*/ pci_write_config8(north,0x6c, 0x03);
print_err("eax and esi: "); #if DIMM_CL2
print_err_hex32(eax); print_err(" "); dimms_read(0x150);
print_err_hex32(esi); print_err("\r\n"); #else // CL=3
dimms_read(0x1d0);
if (eax > esi) { /* ??*/ #endif
udelay(200);
// This is the current best MA mapping. print_err("NORMAL\r\n");
// Save the address and its MA mapping value. /* set to normal mode */
best = r; pci_write_config8(north,0x6C, 0x08);
esi = eax;
} dimms_write(0x55aa55aa);
} dimms_read(0);
udelay(200);
pci_write_config8(north,0x58, raminit_ma_reg_table[best]); print_err("set ref. rate\r\n");
print_err("enabled first bank of ram ... ma is "); // Set the refresh rate.
print_err_hex8(pci_read_config8(north, 0x58)); #if DIMM_PC133
print_err("\r\n"); pci_write_config8(north,0x6A, 0x86);
} #else
} pci_write_config8(north,0x6A, 0x65);
base = 0; #endif
/* runs out of variable space. */ print_err("enable multi-page open\r\n");
/* this is unrolled and constants used as much as possible to help // enable multi-page open
* us not run out of registers. pci_write_config8(north,0x6B, 0x0d);
* we'll run out of code space instead :-)
*/ /* Begin auto-detection
// for(i = 0; i < 8; i++) * Find the first bank with DIMM equipped. */
base = do_module_size(0); /*, base);*/
pci_write_config8(north, ramregs[0], base); /* Maximum possible memory in bank 0, none in other banks.
base = do_module_size(1); /*, base);*/ * Starting from bank 0, we fill 0 in these registers
base += pci_read_config8(north, ramregs[0]); * until memory is found. */
pci_write_config8(north, ramregs[1], base); pci_write_config8(north,0x5A, 0xff);
/* runs out of code space. */ pci_write_config8(north,0x5B, 0xff);
for(i = 0; i < 8; i++){ pci_write_config8(north,0x5C, 0xff);
pci_write_config8(north, ramregs[i], base); pci_write_config8(north,0x5D, 0xff);
/* pci_write_config8(north,0x5E, 0xff);
pci_write_config8(north, ramregs[3], base); pci_write_config8(north,0x5F, 0xff);
pci_write_config8(north, ramregs[4], base); pci_write_config8(north,0x56, 0xff);
pci_write_config8(north, ramregs[5], base); pci_write_config8(north,0x57, 0xff);
pci_write_config8(north, ramregs[6], base); dumpnorth(north);
pci_write_config8(north, ramregs[7], base); print_err("MA\r\n");
*/ for(c = 0; c < 8; c++) {
} /* Write different values to 0 and 8, then read from 0.
/* * If values of address 0 match, we have something there. */
base = do_module_size(0xa0, base); print_err("write to 0\r\n");
base = do_module_size(0xa0, base); *(volatile unsigned long *) 0 = 0x12345678;
base = do_module_size(0xa0, base);
base = do_module_size(0xa0, base); /* LEAVE THIS HERE. IT IS ESSENTIAL. OTHERWISE BUFFERING
base = do_module_size(0xa0, base); * WILL FOOL YOU!
base = do_module_size(0xa0, base);*/ */
print_err("vt8601 done\n"); print_err("write to 8\r\n");
dumpnorth(north); *(volatile unsigned long *) 8 = 0x87654321;
udelay(1000);
if (*(volatile unsigned long *) 0 != 0x12345678) {
print_err("no memory in this bank\r\n");
/* No memory in this bank. Tell it to the bridge. */
pci_write_config8(north,ramregs[c], 0);
}
/* found something */
{
uint8_t best = 0;
/* Detect MA mapping type of the bank. */
for(r = 0; r < 3; r++) {
volatile unsigned long esi = 0;
volatile unsigned long eax = 0;
pci_write_config8(north,0x58, raminit_ma_reg_table[r]);
* (volatile unsigned long *) eax = 0;
print_err(" done write to eax\r\n");
// Write to addresses with only one address bit
// on, from 0x80000000 to 0x00000008 (lower 3 bits
// are ignored, assuming 64-bit bus). Then what
// is read at address 0 is the value written to
// the lowest address where it gets
// wrap-around. That address is either the size of
// the bank, or a missing bit due to incorrect MA
// mapping.
eax = 0x80000000;
while (eax != 4) {
* (volatile unsigned long *) eax = eax;
//print_err_hex32(eax);
outb(eax&0xff, 0x80);
eax >>= 1;
}
print_err(" done read to eax\r\n");
eax = * (unsigned long *)0;
/* oh boy ... what is this.
movl 0, %eax
cmpl %eax, %esi
jnc 3f
*/
print_err("eax and esi: ");
print_err_hex32(eax); print_err(" ");
print_err_hex32(esi); print_err("\r\n");
if (eax > esi) { /* ??*/
// This is the current best MA mapping.
// Save the address and its MA mapping value.
best = r;
esi = eax;
}
}
pci_write_config8(north,0x58, raminit_ma_reg_table[best]);
print_err("enabled first bank of ram ... ma is ");
print_err_hex8(pci_read_config8(north, 0x58));
print_err("\r\n");
}
}
base = 0;
/* runs out of variable space. */
/* this is unrolled and constants used as much as possible to help
* us not run out of registers.
* we'll run out of code space instead :-)
*/
// for(i = 0; i < 8; i++)
base = do_module_size(0); /*, base);*/
pci_write_config8(north, ramregs[0], base);
base = do_module_size(1); /*, base);*/
base += pci_read_config8(north, ramregs[0]);
pci_write_config8(north, ramregs[1], base);
/* runs out of code space. */
for(i = 0; i < 8; i++){
pci_write_config8(north, ramregs[i], base);
/*
pci_write_config8(north, ramregs[3], base);
pci_write_config8(north, ramregs[4], base);
pci_write_config8(north, ramregs[5], base);
pci_write_config8(north, ramregs[6], base);
pci_write_config8(north, ramregs[7], base);
*/
}
/*
base = do_module_size(0xa0, base);
base = do_module_size(0xa0, base);
base = do_module_size(0xa0, base);
base = do_module_size(0xa0, base);
base = do_module_size(0xa0, base);
base = do_module_size(0xa0, base);*/
print_err("vt8601 done\n");
dumpnorth(north);
udelay(1000);
} }

2
src/northbridge/via/vt8601/raminit.h
View File

@ -2,7 +2,7 @@
#define RAMINIT_H #define RAMINIT_H
struct mem_controller { struct mem_controller {
int empty; int empty;
}; };
#endif /* RAMINIT_H */ #endif /* RAMINIT_H */