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nb/intel/sandybridge/raminit: Set REFIx9 according to spec 

Set tREFIx9 to 8.9*tREFI/1024 as suggested in
xeon-e3-1200v3-vol-2-datasheet.pdf chapter 4.2.15 or
2nd-gen-core-family-mobile-vol-2-datasheet chapter 2.14.1.

Use the minimum value of REFI*8.9 and tRASmax as suggested by
3rd-gen-core-desktop-vol-2-datasheet.pdf chapter 2.13.9.

Change-Id: Ifd32a70f28aa75418030b0e4d1fc7d539a315f83
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/22259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Patrick Rudolph 2017-10-31 10:49:52 +01:00
parent 8c85880236
commit 5ee9bc1840
1 changed files with 12 additions and 10 deletions
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22
src/northbridge/intel/sandybridge/raminit_common.c
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@ -264,16 +264,18 @@ void dram_timing_regs(ramctr_timing *ctrl)
dram_odt_stretch(ctrl, channel); dram_odt_stretch(ctrl, channel);
// REFI /*
reg = 0; * TC—Refresh timing parameters
val32 = ctrl->tREFI; * The tREFIx9 field should be programmed to minimum of
reg = (reg & ~0xffff) | val32; * 8.9*tREFI (to allow for possible delays from ZQ or
val32 = ctrl->tRFC; * isoc) and tRASmax (70us) divided by 1024.
reg = (reg & ~0x1ff0000) | (val32 << 16); */
val32 = (u32) (ctrl->tREFI * 9) / 1024; val32 = MIN((ctrl->tREFI * 89) / 10, (70000 << 8) / ctrl->tCK);
reg = (reg & ~0xfe000000) | (val32 << 25);
printram("REFI [%x] = %x\n", 0x400 * channel + 0x4298, reg = ((ctrl->tREFI & 0xffff) << 0) |
reg); ((ctrl->tRFC & 0x1ff) << 16) |
(((val32 / 1024) & 0x7f) << 25);
printram("REFI [%x] = %x\n", 0x400 * channel + 0x4298, reg);
MCHBAR32(0x400 * channel + 0x4298) = reg; MCHBAR32(0x400 * channel + 0x4298) = reg;
MCHBAR32(0x400 * channel + 0x4294) |= 0xff; MCHBAR32(0x400 * channel + 0x4294) |= 0xff;