soc/amd/common: Redo ACPIMMIO_BASE and _BANK

Change-Id: I31f2d04d9fc8bdd9e270fb3cb48d71f215999a50
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42894
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki 2020-06-29 23:56:50 +03:00 committed by Felix Held
parent d786520de1
commit 5f2f44a4cf
3 changed files with 5 additions and 11 deletions

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@ -5,12 +5,9 @@
#include <amdblocks/acpimmio_map.h>
#include <amdblocks/acpimmio.h>
#define ACPI_BANK_PTR(bank) \
(void *)(uintptr_t)(AMD_SB_ACPI_MMIO_ADDR + ACPIMMIO_ ## bank ## _BANK)
#if CONSTANT_ACPIMMIO_BASE_ADDRESS
#define DECLARE_ACPIMMIO(ptr, bank) \
uint8_t *const ptr = ACPI_BANK_PTR(bank)
uint8_t *const ptr = (void *)(uintptr_t)ACPIMMIO_BASE(bank)
#else
#define DECLARE_ACPIMMIO(ptr, bank) uint8_t *ptr
#endif

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@ -95,13 +95,10 @@
#define AMD_SB_ACPI_MMIO_ADDR 0xfed80000
#ifdef __ACPI__
/* ASL fails on additions. */
/* ASL MemoryFixed32() fails if these are additions. */
#define ACPIMMIO_MISC_BASE 0xfed80e00
#define ACPIMMIO_GPIO0_BASE 0xfed81500
#define ACPIMMIO_AOAC_BASE 0xfed81e00
#else
#endif
#define ACPIMMIO_SM_PCI_BANK 0x0000
#define ACPIMMIO_GPIO_100_BANK 0x0100
@ -126,6 +123,6 @@
#define ACPIMMIO_ACDCTMR_BANK 0x1d00
#define ACPIMMIO_AOAC_BANK 0x1e00
#endif
#define ACPIMMIO_BASE(bank) (AMD_SB_ACPI_MMIO_ADDR + ACPIMMIO_ ## bank ## _BANK)
#endif /* AMD_BLOCK_ACPIMMIO_MAP_H */

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@ -4,7 +4,7 @@
#define AOAC_DEVICE(DEV_NAME, DEV_ID, SX) \
PowerResource(DEV_NAME, SX, 0) { \
OperationRegion (AOAC, SystemMemory, ACPIMMIO_AOAC_BASE + 0x40 + (DEV_ID << 1), 2) \
OperationRegion (AOAC, SystemMemory, ACPIMMIO_BASE(AOAC) + 0x40 + (DEV_ID << 1), 2) \
Field (AOAC, ByteAcc, NoLock, Preserve) { \
/* \
* Target Device State \