soc/amd/common: Redo ACPIMMIO_BASE and _BANK
Change-Id: I31f2d04d9fc8bdd9e270fb3cb48d71f215999a50 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42894 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -5,12 +5,9 @@
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#include <amdblocks/acpimmio_map.h>
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#include <amdblocks/acpimmio.h>
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#define ACPI_BANK_PTR(bank) \
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(void *)(uintptr_t)(AMD_SB_ACPI_MMIO_ADDR + ACPIMMIO_ ## bank ## _BANK)
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#if CONSTANT_ACPIMMIO_BASE_ADDRESS
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#define DECLARE_ACPIMMIO(ptr, bank) \
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uint8_t *const ptr = ACPI_BANK_PTR(bank)
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uint8_t *const ptr = (void *)(uintptr_t)ACPIMMIO_BASE(bank)
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#else
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#define DECLARE_ACPIMMIO(ptr, bank) uint8_t *ptr
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#endif
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@ -95,13 +95,10 @@
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#define AMD_SB_ACPI_MMIO_ADDR 0xfed80000
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#ifdef __ACPI__
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/* ASL fails on additions. */
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/* ASL MemoryFixed32() fails if these are additions. */
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#define ACPIMMIO_MISC_BASE 0xfed80e00
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#define ACPIMMIO_GPIO0_BASE 0xfed81500
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#define ACPIMMIO_AOAC_BASE 0xfed81e00
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#else
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#endif
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#define ACPIMMIO_SM_PCI_BANK 0x0000
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#define ACPIMMIO_GPIO_100_BANK 0x0100
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@ -126,6 +123,6 @@
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#define ACPIMMIO_ACDCTMR_BANK 0x1d00
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#define ACPIMMIO_AOAC_BANK 0x1e00
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#endif
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#define ACPIMMIO_BASE(bank) (AMD_SB_ACPI_MMIO_ADDR + ACPIMMIO_ ## bank ## _BANK)
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#endif /* AMD_BLOCK_ACPIMMIO_MAP_H */
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@ -4,7 +4,7 @@
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#define AOAC_DEVICE(DEV_NAME, DEV_ID, SX) \
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PowerResource(DEV_NAME, SX, 0) { \
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OperationRegion (AOAC, SystemMemory, ACPIMMIO_AOAC_BASE + 0x40 + (DEV_ID << 1), 2) \
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OperationRegion (AOAC, SystemMemory, ACPIMMIO_BASE(AOAC) + 0x40 + (DEV_ID << 1), 2) \
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Field (AOAC, ByteAcc, NoLock, Preserve) { \
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/* \
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* Target Device State \
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