soc/intel/mtl: Add missing claimed memory regions
This CL adds claimed memory regions that were missing for the
resource allocator. See commit ca741055e6 ("soc/intel/adl: Add
missing claimed memory regions") for details.
TEST=Booted rex and saw the previously missing ranges getting added
from AP Log (with this CL):
SA MMIO resource: MCHBAR -> base = 0xfedc0000, size = 0x00020000
SA MMIO resource: DMIBAR -> base = 0xfeda0000, size = 0x00001000
SA MMIO resource: EPBAR -> base = 0xfeda1000, size = 0x00001000
SA MMIO resource: REGBAR -> base = 0xd0000000, size = 0x10000000
SA MMIO resource: EDRAMBAR -> base = 0xfed80000, size = 0x00004000
SA MMIO resource: CRAB_ABORT -> base = 0xfeb00000, size = 0x00080000
SA MMIO resource: LT_SECURITY -> base = 0xfed20000, size = 0x00060000
SA MMIO resource: APIC -> base = 0xfec00000, size = 0x00100000
SA MMIO resource: PCH_RESERVED -> base = 0xfd800000, size = 0x01000000
SA MMIO resource: MMCONF -> base = 0xc0000000, size = 0x10000000
SA MMIO resource: DSM -> base = 0x7c000000, size = 0x04000000
SA MMIO resource: TSEG -> base = 0x7b000000, size = 0x00800000
SA MMIO resource: GSM -> base = 0x7b800000, size = 0x00800000
dmesg:
BIOS-e820: [mem 0x0000000000000000-0x0000000000000fff] reserved
BIOS-e820: [mem 0x0000000000001000-0x000000000009ffff] usable
BIOS-e820: [mem 0x00000000000a0000-0x00000000000fffff] reserved
BIOS-e820: [mem 0x0000000000100000-0x00000000759c9fff] usable
BIOS-e820: [mem 0x00000000759ca000-0x000000007fffffff] reserved
BIOS-e820: [mem 0x00000000c0000000-0x00000000e0ffffff] reserved
BIOS-e820: [mem 0x00000000f8000000-0x00000000f9ffffff] reserved
BIOS-e820: [mem 0x00000000fd800000-0x00000000fe7fffff] reserved
BIOS-e820: [mem 0x00000000feb00000-0x00000000feb7ffff] reserved
BIOS-e820: [mem 0x00000000fec00000-0x00000000fecfffff] reserved
BIOS-e820: [mem 0x00000000fed20000-0x00000000fed83fff] reserved
BIOS-e820: [mem 0x00000000feda0000-0x00000000feda1fff] reserved
BIOS-e820: [mem 0x00000000fedc0000-0x00000000feddffff] reserved
BIOS-e820: [mem 0x00000000ff000000-0x00000000ffffffff] reserved
BIOS-e820: [mem 0x0000000100000000-0x000000027fffffff] usable
BIOS-e820: [mem 0x000003fff0aa0000-0x000003fff0aa1fff] reserved
Change-Id: I749e7b6e969f8d6314fcd2906acd7de69d4d9f9c
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit is contained in:
Eran Mitrani
Felix Held
parent
567c6be77a
commit
5f4f1b8558
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@ -42,4 +42,28 @@ static const struct sa_mmio_descriptor soc_vtd_resources[] = {
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#define V_P2SB_CFG_HBDF_DEV 30
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#define V_P2SB_CFG_HBDF_FUNC 6
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#define CRAB_ABORT_BASE_ADDR 0xFEB00000
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#define CRAB_ABORT_SIZE (512 * KiB)
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#define TPM_BASE_ADDRESS 0xFED40000
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#define TPM_SIZE (64 * KiB)
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#define LT_SECURITY_BASE_ADDR 0xFED20000
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#define LT_SECURITY_SIZE (384 * KiB)
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#define APIC_SIZE (1 * MiB)
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#define MASK_PCIEXBAR_LENGTH 0x0000000E // bits [3:1]
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#define PCIEXBAR_LENGTH_LSB 1 // used to shift right
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#define DSM_BASE_ADDR_REG 0xB0
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#define MASK_DSM_LENGTH 0xFF00 // [15:8]
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#define MASK_DSM_LENGTH_LSB 8 // used to shift right
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#define MASK_GSM_LENGTH 0xC0 // [7:6]
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#define MASK_GSM_LENGTH_LSB 6 // used to shift right
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#define DPR_REG 0x5C
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#define MASK_DPR_LENGTH 0xFF0 // [11:4]
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#define MASK_DPR_LENGTH_LSB 4 // used to shift right
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uint64_t get_mmcfg_size(const struct device *dev);
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uint64_t get_dsm_size(const struct device *dev);
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uint64_t get_gsm_size(const struct device *dev);
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uint64_t get_dpr_size(const struct device *dev);
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#endif
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@ -1,10 +1,14 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <arch/ioapic.h>
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#include <console/console.h>
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#include <cpu/x86/msr.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <delay.h>
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#include <intelblocks/cpulib.h>
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#include <intelblocks/msr.h>
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#include <intelblocks/power_limit.h>
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#include <intelblocks/systemagent.h>
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#include <soc/iomap.h>
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@ -20,12 +24,22 @@
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void soc_add_fixed_mmio_resources(struct device *dev, int *index)
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{
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static const struct sa_mmio_descriptor soc_fixed_resources[] = {
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{ PCIEXBAR, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH,
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"PCIEXBAR" },
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{ MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
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{ DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" },
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{ EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" },
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{ REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" },
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{ EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" },
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/* first field (sa_mmio_descriptor.index) is not used, setting to 0: */
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{ 0, CRAB_ABORT_BASE_ADDR, CRAB_ABORT_SIZE, "CRAB_ABORT" },
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{ 0, LT_SECURITY_BASE_ADDR, LT_SECURITY_SIZE, "LT_SECURITY" },
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{ 0, IO_APIC_ADDR, APIC_SIZE, "APIC" },
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// PCH_PRESERVERD covers:
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// TraceHub SW BAR, PMC MBAR, SPI BAR0, SerialIo BAR in ACPI mode
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// eSPI LGMR BAR, eSPI2 SEGMR BAR, TraceHub MTB BAR, TraceHub FW BAR
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// IOE PMC BAR, Tracehub RTIT BAR (SOC), HECI{1,2,3} BAR0
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// see fsp/ClientOneSiliconPkg/Fru/MtlSoc/Include/PchReservedResources.h
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{ 0, PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE, "PCH_RESERVED" },
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};
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sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources,
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@ -39,6 +53,98 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *index)
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ARRAY_SIZE(soc_vtd_resources));
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}
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/*
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* set MMIO resource's fields
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*/
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static void set_mmio_resource(
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struct sa_mmio_descriptor *resource,
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uint64_t base,
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uint64_t size,
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const char *description)
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{
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if (resource == NULL) {
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printk(BIOS_ERR, "%s: argument resource is NULL for %s\n",
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__func__, description);
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return;
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}
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resource->base = base;
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resource->size = size;
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resource->description = description;
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}
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int soc_get_uncore_prmmr_base_and_mask(uint64_t *prmrr_base,
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uint64_t *prmrr_mask)
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{
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msr_t msr;
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msr = rdmsr(MSR_PRMRR_BASE_0);
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*prmrr_base = (uint64_t)msr.hi << 32 | msr.lo;
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msr = rdmsr(MSR_PRMRR_PHYS_MASK);
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*prmrr_mask = (uint64_t)msr.hi << 32 | msr.lo;
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return 0;
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}
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/*
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* SoC implementation
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*
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* Add all known configurable memory ranges for Host Controller/Memory
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* controller.
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*/
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void soc_add_configurable_mmio_resources(struct device *dev, int *resource_cnt)
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{
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uint64_t size, base, tseg_base;
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int count = 0;
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struct sa_mmio_descriptor cfg_rsrc[6]; /* Increase size when adding more resources */
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/* MMCONF */
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size = get_mmcfg_size(dev);
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if (size > 0)
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set_mmio_resource(&(cfg_rsrc[count++]), CONFIG_ECAM_MMCONF_BASE_ADDRESS,
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size, "MMCONF");
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/* DSM */
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size = get_dsm_size(dev);
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if (size > 0) {
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base = pci_read_config32(dev, DSM_BASE_ADDR_REG) & 0xFFF00000;
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set_mmio_resource(&(cfg_rsrc[count++]), base, size, "DSM");
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}
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/* TSEG */
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size = sa_get_tseg_size();
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tseg_base = sa_get_tseg_base();
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if (size > 0)
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set_mmio_resource(&(cfg_rsrc[count++]), tseg_base, size, "TSEG");
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/* PMRR */
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size = get_valid_prmrr_size();
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if (size > 0) {
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uint64_t mask;
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if (soc_get_uncore_prmmr_base_and_mask(&base, &mask) == 0) {
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base &= mask;
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set_mmio_resource(&(cfg_rsrc[count++]), base, size, "PMRR");
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} else {
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printk(BIOS_ERR, "SA: Failed to get PRMRR base and mask\n");
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}
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}
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/* GSM */
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size = get_gsm_size(dev);
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if (size > 0) {
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base = sa_get_gsm_base();
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set_mmio_resource(&(cfg_rsrc[count++]), base, size, "GSM");
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}
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/* DPR */
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size = get_dpr_size(dev);
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if (size > 0) {
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/* DPR just below TSEG: */
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base = tseg_base - size;
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set_mmio_resource(&(cfg_rsrc[count++]), base, size, "DPR");
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}
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/* Add all the above */
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sa_add_fixed_mmio_resources(dev, resource_cnt, cfg_rsrc, count);
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}
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/*
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* SoC implementation
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*
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@ -100,3 +206,116 @@ uint32_t soc_systemagent_max_chan_capacity_mib(u8 capid0_a_ddrsz)
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return 65536;
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}
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}
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uint64_t get_mmcfg_size(const struct device *dev)
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{
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uint32_t pciexbar_reg;
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uint64_t mmcfg_length;
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if (!dev) {
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printk(BIOS_DEBUG, "%s : device is null\n", __func__);
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return 0;
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}
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pciexbar_reg = pci_read_config32(dev, PCIEXBAR);
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if (!(pciexbar_reg & (1 << 0))) {
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printk(BIOS_DEBUG, "%s : PCIEXBAR disabled\n", __func__);
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return 0;
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}
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switch ((pciexbar_reg & MASK_PCIEXBAR_LENGTH) >> PCIEXBAR_LENGTH_LSB) {
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case PCIEXBAR_LENGTH_4096MB:
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mmcfg_length = 4 * ((uint64_t)GiB);
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break;
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case PCIEXBAR_LENGTH_2048MB:
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mmcfg_length = 2 * ((uint64_t)GiB);
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break;
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case PCIEXBAR_LENGTH_1024MB:
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mmcfg_length = 1 * GiB;
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break;
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case PCIEXBAR_LENGTH_512MB:
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mmcfg_length = 512 * MiB;
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break;
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case PCIEXBAR_LENGTH_256MB:
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mmcfg_length = 256 * MiB;
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break;
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case PCIEXBAR_LENGTH_128MB:
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mmcfg_length = 128 * MiB;
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break;
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case PCIEXBAR_LENGTH_64MB:
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mmcfg_length = 64 * MiB;
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break;
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default:
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printk(BIOS_DEBUG, "%s : PCIEXBAR - invalid length (0x%x)\n", __func__,
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pciexbar_reg & MASK_PCIEXBAR_LENGTH);
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mmcfg_length = 0x0;
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break;
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}
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return mmcfg_length;
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}
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uint64_t get_dsm_size(const struct device *dev)
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{
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// - size : B0/D0/F0:R 50h [15:8]
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uint32_t reg32 = pci_read_config32(dev, GGC);
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uint64_t size;
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uint32_t size_field = (reg32 & MASK_DSM_LENGTH) >> MASK_DSM_LENGTH_LSB;
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if (size_field <= 0x10) { // 0x0 - 0x10
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size = size_field * 32 * MiB;
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} else if ((size_field >= 0xF0) && (size_field >= 0xFE)) {
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size = ((uint64_t)size_field - 0xEF) * 4 * MiB;
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} else {
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switch (size_field) {
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case 0x20:
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size = 1 * GiB;
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break;
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case 0x30:
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size = 1536 * MiB;
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break;
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case 0x40:
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size = 2 * (uint64_t)GiB;
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break;
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default:
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printk(BIOS_DEBUG, "%s : DSM - invalid length (0x%x)\n",
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__func__, size_field);
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size = 0x0;
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break;
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}
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}
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return size;
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}
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uint64_t get_gsm_size(const struct device *dev)
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{
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const u32 gsm_size = pci_read_config32(dev, GGC);
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uint64_t size;
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uint32_t size_field = (gsm_size & MASK_GSM_LENGTH) >> MASK_GSM_LENGTH_LSB;
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switch (size_field) {
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case 0x0:
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size = 0;
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break;
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case 0x1:
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size = 2 * MiB;
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break;
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case 0x2:
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size = 4 * MiB;
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break;
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case 0x3:
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size = 8 * MiB;
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break;
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default:
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size = 0;
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break;
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}
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return size;
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}
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uint64_t get_dpr_size(const struct device *dev)
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{
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uint64_t size;
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uint32_t dpr_reg = pci_read_config32(dev, DPR_REG);
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uint32_t size_field = (dpr_reg & MASK_DPR_LENGTH) >> MASK_DPR_LENGTH_LSB;
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size = (uint64_t)size_field * MiB;
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return size;
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}
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