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drop "arch/asm.h" and "arch/intel.h" and create "cpu/x86/post_code.h" 

(which could at some time hold global post code definitions, too)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5498 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer 2010-04-25 20:42:02 +00:00 committed by Stefan Reinauer
parent 53b0b50dc8
commit 5f5436f935
13 changed files with 76 additions and 117 deletions
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6
src/arch/i386/include/arch/asm.h
View File

@ -1,6 +0,0 @@
#ifndef ASM_H
#define ASM_H
#define ASSEMBLER 1
#endif /* ASM_H */

9
src/arch/i386/include/arch/cpu.h
View File

@ -28,6 +28,7 @@ struct cpuid_result {
uint32_t ecx;
uint32_t edx;
};
/*
* Generic CPUID function
*/
@ -44,7 +45,6 @@ static inline struct cpuid_result cpuid(int op)
return result;
}
/*
* CPUID functions returning a single datum
*/
@ -58,6 +58,7 @@ static inline unsigned int cpuid_eax(unsigned int op)
: "ebx", "ecx", "edx");
return eax;
}
static inline unsigned int cpuid_ebx(unsigned int op)
{
unsigned int eax, ebx;
@ -68,6 +69,7 @@ static inline unsigned int cpuid_ebx(unsigned int op)
: "ecx", "edx" );
return ebx;
}
static inline unsigned int cpuid_ecx(unsigned int op)
{
unsigned int eax, ecx;
@ -78,6 +80,7 @@ static inline unsigned int cpuid_ecx(unsigned int op)
: "ebx", "edx" );
return ecx;
}
static inline unsigned int cpuid_edx(unsigned int op)
{
unsigned int eax, edx;
@ -89,8 +92,6 @@ static inline unsigned int cpuid_edx(unsigned int op)
return edx;
}
#define X86_VENDOR_INVALID 0
#define X86_VENDOR_INTEL 1
#define X86_VENDOR_CYRIX 2
@ -112,6 +113,7 @@ struct cpu_device_id {
unsigned vendor;
unsigned device;
};
struct cpu_driver {
struct device_operations *ops;
struct cpu_device_id *id_table;
@ -141,7 +143,6 @@ static inline unsigned long cpu_index(void)
return ci->index;
}
struct cpuinfo_x86 {
uint8_t x86; /* CPU family */
uint8_t x86_vendor; /* CPU vendor */

52
src/arch/i386/include/arch/intel.h
View File

@ -1,52 +0,0 @@
/*
This software and ancillary information (herein called SOFTWARE )
called LinuxBIOS is made available under the terms described
here. The SOFTWARE has been approved for release with associated
LA-CC Number 00-34 . Unless otherwise indicated, this SOFTWARE has
been authored by an employee or employees of the University of
California, operator of the Los Alamos National Laboratory under
Contract No. W-7405-ENG-36 with the U.S. Department of Energy. The
U.S. Government has rights to use, reproduce, and distribute this
SOFTWARE. The public may copy, distribute, prepare derivative works
and publicly display this SOFTWARE without charge, provided that this
Notice and any statement of authorship are reproduced on all copies.
Neither the Government nor the University makes any warranty, express
or implied, or assumes any liability or responsibility for the use of
this SOFTWARE. If SOFTWARE is modified to produce derivative works,
such modified SOFTWARE should be clearly marked, so as not to confuse
it with the version available from LANL.
*/
/* Copyright 2000, Ron Minnich, Advanced Computing Lab, LANL
* rminnich@lanl.gov
*/
#ifndef ROM_INTEL_H
#define ROM_INTEL_H
/*
* Bootstrap code for the Intel
*
*/
#define RET_LABEL(label) \
jmp label##_done
#define CALL_LABEL(label) \
jmp label ;\
label##_done:
#define CALLSP(func) \
lea 0f, %esp ; \
jmp func ; \
0:
#define RETSP \
jmp *%esp
#define post_code(value) \
movb $value, %al; \
outb %al, $0x80
#endif /* ROM_INTEL_H */

51
src/arch/i386/init/bootblock_prologue.c
View File

@ -1,37 +1,28 @@
/* -*- asm -*-
* $ $
*
*/
/*
* Copyright (C) 1996-2002 Markus Franz Xaver Johannes Oberhumer
*
* This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* Originally this code was part of ucl the data compression library
* for upx the ``Ultimate Packer of eXecutables''.
*
* - Converted to gas assembly, and refitted to work with etherboot.
* Eric Biederman 20 Aug 2002
* - Merged the nrv2b decompressor into crt0.base of coreboot
* Eric Biederman 26 Sept 2002
*/
#include <arch/asm.h>
#include <arch/intel.h>
#include <console/loglevel.h>
/*
* This is the entry code the code in .reset section
* jumps to this address.
* This file is part of the coreboot project.
*
* Copyright (C) 2002 Eric Biederman
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <cpu/x86/post_code.h>
.section ".rom.data", "a", @progbits
.section ".rom.text", "ax", @progbits
post_code(0x01) /* delay for chipsets */
/* This is the entry codde. The code in the .reset section jumps here. */
post_code(0x01)

36
src/arch/i386/init/crt0_prologue.inc
View File

@ -1,22 +1,28 @@
/*
* Copyright 2002 Eric Biederman
*
* This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of the License.
*/
#include <arch/asm.h>
#include <arch/intel.h>
#include <console/loglevel.h>
/*
* This is the entry code.
* The code in the .reset section jumps to this address.
* This file is part of the coreboot project.
*
* Copyright (C) 2002 Eric Biederman
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <cpu/x86/post_code.h>
.section ".rom.data", "a", @progbits
.section ".rom.text", "ax", @progbits
post_code(0x01) /* delay for chipsets */
/* This is the entry code. The code in the .reset section jumps here. */
post_code(0x01)

3
src/arch/i386/lib/c_start.S
View File

@ -1,5 +1,4 @@
#include <arch/asm.h>
#include <arch/intel.h>
#include <cpu/x86/post_code.h>
.section ".text"
.code32

3
src/arch/i386/lib/cpu.c
View File

@ -238,7 +238,8 @@ void cpu_initialize(void)
get_fms(&c, cpu->device);
printk(BIOS_DEBUG, "CPU: family %02x, model %02x, stepping %02x\n", c.x86, c.x86_model, c.x86_mask);
printk(BIOS_DEBUG, "CPU: family %02x, model %02x, stepping %02x\n",
c.x86, c.x86_model, c.x86_mask);
/* Lookup the cpu's operations */
set_cpu_ops(cpu);

1
src/arch/i386/llshell/console.inc
View File

@ -1,4 +1,3 @@
// #include <loglevel.h>
jmp console0

17
src/arch/i386/llshell/llshell.inc
View File

@ -1,3 +1,20 @@
#define RET_LABEL(label) \
jmp label##_done
#define CALL_LABEL(label) \
jmp label ;\
label##_done:
#define CALLSP(func) \
lea 0f, %esp ; \
jmp func ; \
0:
#define RETSP \
jmp *%esp
#include "console.inc"
#include "pci.inc"
#include "ramtest.inc"

3
src/cpu/x86/lapic/secondary.S
View File

@ -1,7 +1,6 @@
#include <arch/asm.h>
#include <arch/intel.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/lapic_def.h>
.text
.globl _secondary_start, _secondary_start_end
.balign 4096

2
src/cpu/x86/smm/smmhandler.S
View File

@ -52,8 +52,6 @@
*
*/
#include <arch/asm.h>
#define LAPIC_ID 0xfee00020
/* SMM_HANDLER_OFFSET is the 16bit offset within the ASEG

4
src/cpu/x86/smm/smmrelocate.S
View File

@ -19,13 +19,13 @@
* MA 02110-1301 USA
*/
#include <arch/asm.h>
// Make sure no stage 2 code is included:
#define __PRE_RAM__
// FIXME: Is this piece of code southbridge specific, or
// can it be cleaned up so this include is not required?
// It's needed right now because we get our PM_BASE from
// here.
#include "../../../southbridge/intel/i82801gx/i82801gx.h"
#undef DEBUG_SMM_RELOCATION

6
src/include/cpu/x86/post_code.h Normal file
View File

@ -0,0 +1,6 @@
#define post_code(value) \
movb $value, %al; \
outb %al, $0x80