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asus/p2b, emu/qemu-i440fx: Use acpigen_write_processor_device() 

FADT duty_width/duty_offset fields, together with P_CNT (previously
P_BLK) IO address are provided with _PTC entry.

FADT p_lvl2/3_lat fields had values that disabled C2/C3 state
transitions so _CST entries are not required.

Change-Id: I629cd0793f6a64e955e197400efaa7d9d898e775
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Kyösti Mälkki 2023-04-14 01:06:22 +03:00 committed by Felix Held
parent d1211cb3de
commit 5fc0afbc17
2 changed files with 5 additions and 6 deletions
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8
src/southbridge/intel/i82371eb/acpi_tables.c
View File

@ -8,10 +8,12 @@
static void generate_cpu_entry(int cpu)
{
int pcontrol_blk = DEFAULT_PMBASE + PCNTRL, plen = 6;
acpigen_write_processor_device(cpu);
acpigen_write_processor(cpu, pcontrol_blk, plen);
acpigen_pop_len();
/* bit 1:3 in PCNTRL reg (pmbase+0x10) */
acpigen_write_PTC(3, 1, DEFAULT_PMBASE + PCNTRL);
acpigen_write_processor_device_end();
}
void generate_cpu_entries(const struct device *device)

3
src/southbridge/intel/i82371eb/fadt.c
View File

@ -29,9 +29,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->pm_tmr_len = 4;
fadt->gpe0_blk_len = 4;
fadt->duty_offset = 1; /* bit 1:3 in PCNTRL reg (pmbase+0x10) */
fadt->duty_width = 3; /* this width is in bits */
/*
* bit meaning
* 0 1: We have user-visible legacy devices