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soc/amd/common/include/spi: fix SPI_FIFO_LAST_BYTE define 

The last byte of the SPI FIFO SPI_FIFO_LAST_BYTE is at offset 0xc6 of
the SPI controller's MMIO region for Stoneyridge and Picasso. Both
SPI_FIFO_LAST_BYTE and SPI_FIFO_DEPTH had an off-by-one error that ended
up cancelling out each other, so the resulting value for SPI_FIFO_DEPTH
isn't changed.

TEST=Timeless build results in identical image for Mandolin.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1676be902ccf57e2e9f69d81251b4315866a0628
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Felix Held 2021-12-08 16:13:01 +01:00
parent 19ad39b7f2
commit 601a971545
1 changed files with 2 additions and 2 deletions
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4
src/soc/amd/common/block/include/amdblocks/spi.h
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@ -71,8 +71,8 @@ enum spi100_speed {
#define SPI_RD4DW_EN_HOST BIT(15) #define SPI_RD4DW_EN_HOST BIT(15)
#define SPI_FIFO 0x80 #define SPI_FIFO 0x80
#define SPI_FIFO_LAST_BYTE 0xc7 #define SPI_FIFO_LAST_BYTE 0xc6
#define SPI_FIFO_DEPTH (SPI_FIFO_LAST_BYTE - SPI_FIFO) #define SPI_FIFO_DEPTH (SPI_FIFO_LAST_BYTE - SPI_FIFO + 1)
struct spi_config { struct spi_config {
/* /*