- With Xeon cpus it seems best to use the tsc calibrated with timer2 as

the time source.  The apic timer also has a variable time base.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1711 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/cpu/intel/model_f2x/Config.lb

@@ -1,5 +1,3 @@
-uses CONFIG_UDELAY_TSC
-
 dir /cpu/x86/mtrr
 dir /cpu/x86/fpu
 dir /cpu/x86/mmx
@@ -10,8 +8,3 @@ dir /cpu/intel/microcode
 dir /cpu/intel/hyperthreading
 driver model_f2x_init.o
 
-if CONFIG_UDELAY_TSC
-	dir /cpu/x86/tsc
-else
-	object apic_timer.o
-end

src/cpu/intel/model_f2x/apic_timer.c

@@ -1,26 +0,0 @@
-#include <stdint.h>
-#include <delay.h>
-#include <cpu/x86/msr.h>
-#include <cpu/x86/lapic.h>
-
-void init_timer(void)
-{
-	/* Set the apic timer to no interrupts and periodic mode */
-	lapic_write(LAPIC_LVTT, (1 << 17)|(1<< 16)|(0 << 12)|(0 << 0));
-	/* Set the divider to 1, no divider */
-	lapic_write(LAPIC_TDCR, LAPIC_TDR_DIV_1);
-	/* Set the initial counter to 0xffffffff */
-	lapic_write(LAPIC_TMICT, 0xffffffff);
-}
-
-void udelay(unsigned usecs)
-{
-	uint32_t start, value, ticks;
-	/* Calculate the number of ticks to run, our FSB runs a 200Mhz */
-	ticks = usecs * 200;
-	start = lapic_read(LAPIC_TMCCT);
-	do {
-		value = lapic_read(LAPIC_TMCCT);
-	} while((start - value) < ticks);
-	
-}

src/mainboard/tyan/s2735/Options.lb

@@ -78,6 +78,12 @@ default HAVE_HARD_RESET=1
 #default HARD_RESET_DEVICE=4
 #default HARD_RESET_FUNCTION=0
 
+##
+## Delay timer options
+##
+default CONFIG_UDELAY_TSC=1
+default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
+
 ##
 ## Build code to export a programmable irq routing table
 ##