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nb/gm45/gma.c: Remove writes to DP, FDI registers 

Those registers are only used on more recent Intel platforms featuring a
PCH. The DP registers on G4X hardware are at a different offset.

Change-Id: Ib49e54d4e7d6595dc09fb1be35ac8178b80c7f71
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17110
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Arthur Heymans 2016-10-24 17:44:20 +02:00 committed by Martin Roth
parent 04be6b5949
commit 606b8bccb5
3 changed files with 0 additions and 47 deletions
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1
src/mainboard/lenovo/t400/devicetree.cb
View File

@ -4,7 +4,6 @@ chip northbridge/intel/gm45
register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
register "gfx.use_spread_spectrum_clock" = "1" register "gfx.use_spread_spectrum_clock" = "1"
register "gfx.link_frequency_270_mhz" = "1"
device cpu_cluster 0 on device cpu_cluster 0 on
chip cpu/intel/socket_BGA956 chip cpu/intel/socket_BGA956

1
src/mainboard/lenovo/x200/devicetree.cb
View File

@ -9,7 +9,6 @@ chip northbridge/intel/gm45
register "gpu_panel_power_backlight_off_delay" = "2500" # Tx: 250ms register "gpu_panel_power_backlight_off_delay" = "2500" # Tx: 250ms
register "gpu_panel_power_cycle_delay" = "3" # T4: 200ms register "gpu_panel_power_cycle_delay" = "3" # T4: 200ms
register "gfx.use_spread_spectrum_clock" = "1" register "gfx.use_spread_spectrum_clock" = "1"
register "gfx.link_frequency_270_mhz" = "1"
device cpu_cluster 0 on device cpu_cluster 0 on
chip cpu/intel/socket_BGA956 chip cpu/intel/socket_BGA956

45
src/northbridge/intel/gm45/gma.c
View File

@ -68,11 +68,6 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info,
u32 pixel_m1 = 1; u32 pixel_m1 = 1;
u32 pixel_m2 = 1; u32 pixel_m2 = 1;
u32 pixel_p2; u32 pixel_p2;
u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000;
u32 data_m1;
u32 data_n1 = 0x00800000;
u32 link_m1;
u32 link_n1 = 0x00080000;
vga_gr_write(0x18, 0); vga_gr_write(0x18, 0);
@ -190,10 +185,6 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info,
return; return;
} }
link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency;
data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock)
/ (link_frequency * 8 * 4);
printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n",
hactive, vactive); hactive, vactive);
printk(BIOS_DEBUG, "Borders %d x %d\n", printk(BIOS_DEBUG, "Borders %d x %d\n",
@ -210,12 +201,6 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info,
mode->lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); mode->lvds_dual_channel ? "Dual channel\n" : "Single channel\n");
printk(BIOS_DEBUG, "Polarities %d, %d\n", printk(BIOS_DEBUG, "Polarities %d, %d\n",
hpolarity, vpolarity); hpolarity, vpolarity);
printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n",
data_m1, data_n1);
printk(BIOS_DEBUG, "Link frequency %d kHz\n",
link_frequency);
printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n",
link_m1, link_n1);
printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n",
pixel_n, pixel_m1, pixel_m2, pixel_p1); pixel_n, pixel_m1, pixel_m2, pixel_p1);
printk(BIOS_DEBUG, "Pixel clock %d kHz\n", printk(BIOS_DEBUG, "Pixel clock %d kHz\n",
@ -298,13 +283,6 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info,
write32(mmio + PFIT_CONTROL, 0x80000000); write32(mmio + PFIT_CONTROL, 0x80000000);
} }
mdelay(1);
write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1);
write32(mmio + PIPE_DATA_N1(0), data_n1);
write32(mmio + PIPE_LINK_M1(0), link_m1);
write32(mmio + PIPE_LINK_N1(0), link_n1);
mdelay(1); mdelay(1);
write32(mmio + PIPECONF(0), PIPECONF_BPP_6); write32(mmio + PIPECONF(0), PIPECONF_BPP_6);
write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
@ -361,12 +339,6 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info,
u32 pixel_n = 1; u32 pixel_n = 1;
u32 pixel_m1 = 1; u32 pixel_m1 = 1;
u32 pixel_m2 = 1; u32 pixel_m2 = 1;
u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000;
u32 data_m1;
u32 data_n1 = 0x00800000;
u32 link_m1;
u32 link_n1 = 0x00040000;
vga_gr_write(0x18, 0); vga_gr_write(0x18, 0);
@ -491,10 +463,6 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info,
return; return;
} }
link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency;
data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock)
/ (link_frequency * 8 * 4);
printk(BIOS_INFO, "Bringing up panel at resolution %d x %d\n", printk(BIOS_INFO, "Bringing up panel at resolution %d x %d\n",
hactive, vactive); hactive, vactive);
printk(BIOS_SPEW, "Borders %d x %d\n", printk(BIOS_SPEW, "Borders %d x %d\n",
@ -509,12 +477,6 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info,
? "Spread spectrum clock\n" : "DREF clock\n")); ? "Spread spectrum clock\n" : "DREF clock\n"));
printk(BIOS_SPEW, "Polarities %d, %d\n", printk(BIOS_SPEW, "Polarities %d, %d\n",
hpolarity, vpolarity); hpolarity, vpolarity);
printk(BIOS_SPEW, "Data M1=%d, N1=%d\n",
data_m1, data_n1);
printk(BIOS_SPEW, "Link frequency %d kHz\n",
link_frequency);
printk(BIOS_SPEW, "Link M1=%d, N1=%d\n",
link_m1, link_n1);
printk(BIOS_SPEW, "Pixel N=%d, M1=%d, M2=%d, P1=%d, P2=%d\n", printk(BIOS_SPEW, "Pixel N=%d, M1=%d, M2=%d, P1=%d, P2=%d\n",
pixel_n, pixel_m1, pixel_m2, pixel_p1, pixel_p2); pixel_n, pixel_m1, pixel_m2, pixel_p1, pixel_p2);
printk(BIOS_SPEW, "Pixel clock %d kHz\n", printk(BIOS_SPEW, "Pixel clock %d kHz\n",
@ -585,13 +547,6 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info,
write32(mmio + PFIT_CONTROL, 0x80000000); write32(mmio + PFIT_CONTROL, 0x80000000);
} }
mdelay(1);
write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1);
write32(mmio + PIPE_DATA_N1(0), data_n1);
write32(mmio + PIPE_LINK_M1(0), link_m1);
write32(mmio + PIPE_LINK_N1(0), link_n1);
mdelay(1); mdelay(1);
write32(mmio + PIPECONF(0), PIPECONF_BPP_6); write32(mmio + PIPECONF(0), PIPECONF_BPP_6);
write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN);