soc/amd/*: Make mtrr decision based on syscfg

The syscfg has to option to automatically mark the range between 4G and
TOM2, which contains DRAM, as WB. Making it generally not necessary to
allocate MTRRs for memory above 4G if no PCI BARs are placed up there.

Change-Id: Ifbacae28e272ab2f39f268ad034354a9c590d035
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This commit is contained in:
Arthur Heymans 2022-05-31 21:33:43 +02:00 committed by Felix Held
parent 99d2d62fa1
commit 615818f5a9
4 changed files with 41 additions and 21 deletions

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@ -7,6 +7,7 @@
#include <assert.h>
#include <console/console.h>
#include <cpu/amd/microcode.h>
#include <cpu/amd/mtrr.h>
#include <cpu/cpu.h>
#include <cpu/x86/mp.h>
#include <cpu/x86/mtrr.h>
@ -31,7 +32,11 @@ _Static_assert(CONFIG_MAX_CPUS == 16, "Do not override MAX_CPUS. To reduce the n
*/
static void pre_mp_init(void)
{
x86_setup_mtrrs_with_detect_no_above_4gb();
const msr_t syscfg = rdmsr(SYSCFG_MSR);
if (syscfg.lo & SYSCFG_MSR_TOM2WB)
x86_setup_mtrrs_with_detect_no_above_4gb();
else
x86_setup_mtrrs_with_detect();
x86_mtrr_check();
}

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@ -1,24 +1,25 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
#include <amdblocks/cpu.h>
#include <amdblocks/mca.h>
#include <amdblocks/reset.h>
#include <amdblocks/smm.h>
#include <assert.h>
#include <cpu/cpu.h>
#include <cpu/x86/mp.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/smm.h>
#include <acpi/acpi.h>
#include <device/device.h>
#include <device/pci_ops.h>
#include <soc/pci_devs.h>
#include <soc/cpu.h>
#include <soc/smi.h>
#include <soc/iomap.h>
#include <console/console.h>
#include <cpu/amd/microcode.h>
#include <cpu/amd/mtrr.h>
#include <cpu/cpu.h>
#include <cpu/x86/mp.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h>
#include <device/device.h>
#include <device/pci_ops.h>
#include <soc/cpu.h>
#include <soc/iomap.h>
#include <soc/pci_devs.h>
#include <soc/smi.h>
#include <types.h>
_Static_assert(CONFIG_MAX_CPUS == 8, "Do not override MAX_CPUS. To reduce the number of "
@ -35,7 +36,11 @@ _Static_assert(CONFIG_MAX_CPUS == 8, "Do not override MAX_CPUS. To reduce the nu
*/
static void pre_mp_init(void)
{
x86_setup_mtrrs_with_detect_no_above_4gb();
const msr_t syscfg = rdmsr(SYSCFG_MSR);
if (syscfg.lo & SYSCFG_MSR_TOM2WB)
x86_setup_mtrrs_with_detect_no_above_4gb();
else
x86_setup_mtrrs_with_detect();
x86_mtrr_check();
}

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@ -9,6 +9,7 @@
#include <assert.h>
#include <console/console.h>
#include <cpu/amd/microcode.h>
#include <cpu/amd/mtrr.h>
#include <cpu/cpu.h>
#include <cpu/x86/mp.h>
#include <cpu/x86/mtrr.h>
@ -33,7 +34,11 @@ _Static_assert(CONFIG_MAX_CPUS == 8, "Do not override MAX_CPUS. To reduce the nu
*/
static void pre_mp_init(void)
{
x86_setup_mtrrs_with_detect_no_above_4gb();
const msr_t syscfg = rdmsr(SYSCFG_MSR);
if (syscfg.lo & SYSCFG_MSR_TOM2WB)
x86_setup_mtrrs_with_detect_no_above_4gb();
else
x86_setup_mtrrs_with_detect();
x86_mtrr_check();
}

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@ -3,20 +3,21 @@
#include <amdblocks/mca.h>
#include <amdblocks/reset.h>
#include <amdblocks/smm.h>
#include <console/console.h>
#include <cpu/amd/msr.h>
#include <cpu/amd/mtrr.h>
#include <cpu/cpu.h>
#include <cpu/x86/mp.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h>
#include <device/device.h>
#include <device/pci_ops.h>
#include <soc/pci_devs.h>
#include <soc/cpu.h>
#include <soc/northbridge.h>
#include <soc/smi.h>
#include <soc/iomap.h>
#include <console/console.h>
#include <soc/northbridge.h>
#include <soc/pci_devs.h>
#include <soc/smi.h>
#include <types.h>
/*
@ -32,7 +33,11 @@
*/
static void pre_mp_init(void)
{
x86_setup_mtrrs_with_detect();
const msr_t syscfg = rdmsr(SYSCFG_MSR);
if (syscfg.lo & SYSCFG_MSR_TOM2WB)
x86_setup_mtrrs_with_detect_no_above_4gb();
else
x86_setup_mtrrs_with_detect();
x86_mtrr_check();
}