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sb/amd/cimx: Fix some white spaces issues 

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Iba81be8ec48fa744f3263e340267a56158656a8f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Elyes Haouas 2022-07-16 09:50:29 +02:00 committed by Felix Held
parent 4d7285df1d
commit 616be8cd1f
8 changed files with 41 additions and 41 deletions
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6
src/southbridge/amd/cimx/sb800/Amd.h
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@ -25,13 +25,13 @@
#define OUT #define OUT
#ifndef Int16FromChar #ifndef Int16FromChar
#define Int16FromChar(a,b) ((a) << 0 | (b) << 8) #define Int16FromChar(a, b) ((a) << 0 | (b) << 8)
#endif #endif
#ifndef Int32FromChar #ifndef Int32FromChar
#define Int32FromChar(a,b,c,d) ((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24) #define Int32FromChar(a, b, c, d) ((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24)
#endif #endif
#define IMAGE_SIGNATURE Int32FromChar ('$', 'A', 'M', 'D') #define IMAGE_SIGNATURE Int32FromChar('$', 'A', 'M', 'D')
typedef unsigned int AGESA_STATUS; typedef unsigned int AGESA_STATUS;

8
src/southbridge/amd/cimx/sb800/AmdSbLib.h
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@ -5,9 +5,9 @@
#include <console/vtxprintf.h> #include <console/vtxprintf.h>
#pragma pack (push, 1) #pragma pack(push, 1)
#define IMAGE_ALIGN 32*1024 #define IMAGE_ALIGN 32 * 1024
#define NUM_IMAGE_LOCATION 32 #define NUM_IMAGE_LOCATION 32
//Entry Point Call //Entry Point Call
@ -104,7 +104,7 @@ typedef struct _CIMFILEHEADER
#ifndef BIT23 #ifndef BIT23
#define BIT23 (1 << 23) #define BIT23 (1 << 23)
#endif #endif
#ifndef BIT24 #ifndef BIT24
#define BIT24 (1 << 24) #define BIT24 (1 << 24)
#endif #endif
#ifndef BIT25 #ifndef BIT25
@ -129,7 +129,7 @@ typedef struct _CIMFILEHEADER
#define BIT31 (1 << 31) #define BIT31 (1 << 31)
#endif #endif
#pragma pack (pop) #pragma pack(pop)
typedef enum typedef enum
{ {

2
src/southbridge/amd/cimx/sb800/bootblock.c
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@ -55,7 +55,7 @@ static void enable_spi_fast_mode(void)
// set temp MMIO base // set temp MMIO base
volatile u32 *spi_base = (void *)0xa0000000; volatile u32 *spi_base = (void *)0xa0000000;
u32 save = pci_s_read_config32(dev, 0xa0); u32 save = pci_s_read_config32(dev, 0xa0);
pci_s_write_config32(dev, 0xa0, (u32) spi_base | 2); pci_s_write_config32(dev, 0xa0, (u32)spi_base | 2);
// early enable of SPI 33 MHz fast mode read // early enable of SPI 33 MHz fast mode read
dword = spi_base[3]; dword = spi_base[3];

38
src/southbridge/amd/cimx/sb800/fan.h
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@ -71,16 +71,16 @@ void init_sb800_MANUAL_fans(struct device *dev);
#define FREQ_11HZ 0xFF #define FREQ_11HZ 0xFF
/* IMC Fan Control Definitions */ /* IMC Fan Control Definitions */
#define IMC_MODE1_FAN_ENABLED ( 1 << 0 ) #define IMC_MODE1_FAN_ENABLED (1 << 0)
#define IMC_MODE1_FAN_IMC_CONTROLLED ( 1 << 2 ) #define IMC_MODE1_FAN_IMC_CONTROLLED (1 << 2)
#define IMC_MODE1_FAN_LINEAR_MODE ( 1 << 4 ) #define IMC_MODE1_FAN_LINEAR_MODE (1 << 4)
#define IMC_MODE1_FAN_STEP_MODE 0 /* ~( 1 << 4 ) */ #define IMC_MODE1_FAN_STEP_MODE 0 /* ~( 1 << 4 ) */
#define IMC_MODE1_NO_FANOUT 0 /* ~( 7 << 5 ) */ #define IMC_MODE1_NO_FANOUT 0 /* ~( 7 << 5 ) */
#define IMC_MODE1_FANOUT0 ( 1 << 5 ) #define IMC_MODE1_FANOUT0 (1 << 5)
#define IMC_MODE1_FANOUT1 ( 2 << 5 ) #define IMC_MODE1_FANOUT1 (2 << 5)
#define IMC_MODE1_FANOUT2 ( 3 << 5 ) #define IMC_MODE1_FANOUT2 (3 << 5)
#define IMC_MODE1_FANOUT3 ( 4 << 5 ) #define IMC_MODE1_FANOUT3 (4 << 5)
#define IMC_MODE1_FANOUT4 ( 5 << 5 ) #define IMC_MODE1_FANOUT4 (5 << 5)
#define IMC_MODE2_TEMPIN_NONE 0 /* ~( 7 << 0) */ #define IMC_MODE2_TEMPIN_NONE 0 /* ~( 7 << 0) */
#define IMC_MODE2_TEMPIN_0 1 #define IMC_MODE2_TEMPIN_0 1
@ -91,12 +91,12 @@ void init_sb800_MANUAL_fans(struct device *dev);
#define IMC_MODE2_TEMPIN_SB_TSI 6 #define IMC_MODE2_TEMPIN_SB_TSI 6
#define IMC_MODE2_TEMPIN_OTHER 7 #define IMC_MODE2_TEMPIN_OTHER 7
#define IMC_MODE2_FANIN_NONE 0 /* ~ (7 << 3) */ #define IMC_MODE2_FANIN_NONE 0 /* ~ (7 << 3) */
#define IMC_MODE2_FANIN0 ( 1 << 3 ) #define IMC_MODE2_FANIN0 (1 << 3)
#define IMC_MODE2_FANIN1 ( 2 << 3 ) #define IMC_MODE2_FANIN1 (2 << 3)
#define IMC_MODE2_FANIN2 ( 3 << 3 ) #define IMC_MODE2_FANIN2 (3 << 3)
#define IMC_MODE2_FANIN3 ( 4 << 3 ) #define IMC_MODE2_FANIN3 (4 << 3)
#define IMC_MODE2_FANIN4 ( 5 << 3 ) #define IMC_MODE2_FANIN4 (5 << 3)
#define IMC_MODE2_TEMP_AVERAGING_ENABLED ( 1 << 6 ) #define IMC_MODE2_TEMP_AVERAGING_ENABLED (1 << 6)
#define IMC_MODE2_TEMP_AVERAGING_DISABLED 0 /* ~( 1 << 6 ) */ #define IMC_MODE2_TEMP_AVERAGING_DISABLED 0 /* ~( 1 << 6 ) */
#define IMC_TEMP_SENSOR_ON_SMBUS_0 0 #define IMC_TEMP_SENSOR_ON_SMBUS_0 0
@ -113,17 +113,17 @@ void init_sb800_MANUAL_fans(struct device *dev);
#define IMC_TEMPIN_TUNING_DEFAULT_MODE 0 #define IMC_TEMPIN_TUNING_DEFAULT_MODE 0
#define IMC_TEMPIN_TUNING_HIGH_CURRENT_RATIO 1 #define IMC_TEMPIN_TUNING_HIGH_CURRENT_RATIO 1
#define IMC_TEMPIN_TUNING_HIGH_CURRENT 2 #define IMC_TEMPIN_TUNING_HIGH_CURRENT 2
#define IMC_TEMPIN_TUNING_DISABLE_FILTERING ( 1 << 2 ) #define IMC_TEMPIN_TUNING_DISABLE_FILTERING (1 << 2)
/* IMCFUNSupportBitMap - Zone enable values */ /* IMCFUNSupportBitMap - Zone enable values */
#define IMC_ENABLE_ZONE0 0x111 #define IMC_ENABLE_ZONE0 0x111
#define IMC_ENABLE_ZONE1 0x222 #define IMC_ENABLE_ZONE1 0x222
#define IMC_ENABLE_ZONE2 0x333 #define IMC_ENABLE_ZONE2 0x333
#define IMC_ENABLE_ZONE3 0x444 #define IMC_ENABLE_ZONE3 0x444
#define IMC_ENABLE_TEMPIN0 ( 1 << 12 ) #define IMC_ENABLE_TEMPIN0 (1 << 12)
#define IMC_ENABLE_TEMPIN1 ( 1 << 13 ) #define IMC_ENABLE_TEMPIN1 (1 << 13)
#define IMC_ENABLE_TEMPIN2 ( 1 << 14 ) #define IMC_ENABLE_TEMPIN2 (1 << 14)
#define IMC_ENABLE_TEMPIN3 ( 1 << 15 ) #define IMC_ENABLE_TEMPIN3 (1 << 15)
/* Array size settings */ /* Array size settings */
#define IMC_FAN_THRESHOLD_COUNT 9 #define IMC_FAN_THRESHOLD_COUNT 9

6
src/southbridge/amd/cimx/sb800/gpio_oem.h
View File

@ -13,9 +13,9 @@
#define SB_GPIO_REG28 28 #define SB_GPIO_REG28 28
/* FCH GPIO access helpers */ /* FCH GPIO access helpers */
#define FCH_IOMUX(gpio_nr) (*(u8*)((uintptr_t)ACPI_MMIO_BASE+IOMUX_BASE+(gpio_nr))) #define FCH_IOMUX(gpio_nr) (*(u8 *)((uintptr_t)ACPI_MMIO_BASE + IOMUX_BASE + (gpio_nr)))
#define FCH_PMIO(reg_nr) (*(u8*)((uintptr_t)ACPI_MMIO_BASE+PMIO_BASE+(reg_nr))) #define FCH_PMIO(reg_nr) (*(u8 *)((uintptr_t)ACPI_MMIO_BASE + PMIO_BASE + (reg_nr)))
#define FCH_GPIO(gpio_nr) (*(volatile u8*)((uintptr_t)ACPI_MMIO_BASE+GPIO_BASE+(gpio_nr))) #define FCH_GPIO(gpio_nr) (*(volatile u8 *)((uintptr_t)ACPI_MMIO_BASE + GPIO_BASE + (gpio_nr)))
static inline u8 fch_gpio_state(unsigned int gpio_nr) static inline u8 fch_gpio_state(unsigned int gpio_nr)
{ {

4
src/southbridge/amd/cimx/sb800/late.c
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@ -88,7 +88,7 @@ static void ahci_raid_init(struct device *dev)
caps = read32(bar5 + HOST_CAP); caps = read32(bar5 + HOST_CAP);
caps = (caps & 0x1F) + 1; caps = (caps & 0x1F) + 1;
ports= read32(bar5 + HOST_PORTS_IMPL); ports = read32(bar5 + HOST_PORTS_IMPL);
printk(BIOS_DEBUG, "Number of Ports: 0x%x, Port implemented(bit map): 0x%x\n", caps, ports); printk(BIOS_DEBUG, "Number of Ports: 0x%x, Port implemented(bit map): 0x%x\n", caps, ports);
/* make sure ahci is enabled */ /* make sure ahci is enabled */
@ -382,7 +382,7 @@ static void sb800_enable(struct device *dev)
{ {
struct device *device; struct device *device;
for (device = dev; device; device = device->sibling) { for (device = dev; device; device = device->sibling) {
if ((device->path.pci.devfn & ~3) != PCI_DEVFN(0x15,0)) break; if ((device->path.pci.devfn & ~3) != PCI_DEVFN(0x15, 0)) break;
sb_config->PORTCONFIG[device->path.pci.devfn & 3].PortCfg.PortPresent = device->enabled; sb_config->PORTCONFIG[device->path.pci.devfn & 3].PortCfg.PortPresent = device->enabled;
} }

4
src/southbridge/amd/cimx/sb800/reset.c
View File

@ -8,10 +8,10 @@
#include <reset.h> #include <reset.h>
#define HT_INIT_CONTROL 0x6c #define HT_INIT_CONTROL 0x6c
#define HTIC_BIOSR_Detect (1<<5) #define HTIC_BIOSR_Detect (1 << 5)
#define DEV_CDB 0x18 #define DEV_CDB 0x18
#define NODE_PCI(x, fn) (((DEV_CDB+x)<32)?(PCI_DEV(0,(DEV_CDB+x),fn)):(PCI_DEV((0-1),(DEV_CDB+x-32),fn))) #define NODE_PCI(x, fn) (((DEV_CDB + x) < 32) ? (PCI_DEV(0, (DEV_CDB + x), fn)) : (PCI_DEV((0 - 1), (DEV_CDB + x - 32), fn)))
void cf9_reset_prepare(void) void cf9_reset_prepare(void)
{ {

14
src/southbridge/amd/cimx/sb800/spi.c
View File

@ -29,7 +29,7 @@ static void execute_command(void)
write8((void *)(spibar + 2), read8((void *)(spibar + 2)) | 1); write8((void *)(spibar + 2), read8((void *)(spibar + 2)) | 1);
while ((read8((void *)(spibar + 2)) & 1) && while ((read8((void *)(spibar + 2)) & 1) &&
(read8((void *)(spibar+3)) & 0x80)); (read8((void *)(spibar + 3)) & 0x80));
} }
void spi_init(void) void spi_init(void)
@ -98,9 +98,9 @@ static void ImcSleep(void)
u8 reg0_val = 0; /* clear response register */ u8 reg0_val = 0; /* clear response register */
u8 reg1_val = 0xB4; /* request ownership flag */ u8 reg1_val = 0xB4; /* request ownership flag */
WriteECmsg (MSG_REG0, AccWidthUint8, &reg0_val); WriteECmsg(MSG_REG0, AccWidthUint8, &reg0_val);
WriteECmsg (MSG_REG1, AccWidthUint8, &reg1_val); WriteECmsg(MSG_REG1, AccWidthUint8, &reg1_val);
WriteECmsg (MSG_SYS_TO_IMC, AccWidthUint8, &cmd_val); WriteECmsg(MSG_SYS_TO_IMC, AccWidthUint8, &cmd_val);
WaitForEcLDN9MailboxCmdAck(); WaitForEcLDN9MailboxCmdAck();
} }
@ -111,9 +111,9 @@ static void ImcWakeup(void)
u8 reg0_val = 0; /* clear response register */ u8 reg0_val = 0; /* clear response register */
u8 reg1_val = 0xB5; /* release ownership flag */ u8 reg1_val = 0xB5; /* release ownership flag */
WriteECmsg (MSG_REG0, AccWidthUint8, &reg0_val); WriteECmsg(MSG_REG0, AccWidthUint8, &reg0_val);
WriteECmsg (MSG_REG1, AccWidthUint8, &reg1_val); WriteECmsg(MSG_REG1, AccWidthUint8, &reg1_val);
WriteECmsg (MSG_SYS_TO_IMC, AccWidthUint8, &cmd_val); WriteECmsg(MSG_SYS_TO_IMC, AccWidthUint8, &cmd_val);
WaitForEcLDN9MailboxCmdAck(); WaitForEcLDN9MailboxCmdAck();
} }