soc/amd: Make espi_configure_decodes private

This is only ever called after espi_setup.

55861 - AMD System Peripheral Bus Overview also says that io ranges
should be configured before enabling the BUS_MASTER bit.

BUG=b:183524609
TEST=Boot guybrush to OS

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I074e487d8768a578ee889a125b9948e3aa6c7269
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52059
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Raul E Rangel 2021-04-02 10:55:27 -06:00 committed by Raul Rangel
parent c988d0516c
commit 61ac1bc530
5 changed files with 15 additions and 18 deletions

View File

@ -70,6 +70,5 @@ void fch_early_init(void)
if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) { if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) {
espi_clear_decodes(); espi_clear_decodes();
espi_setup(); espi_setup();
espi_configure_decodes();
} }
} }

View File

@ -100,12 +100,6 @@ int espi_open_io_window(uint16_t base, size_t size);
*/ */
int espi_open_mmio_window(uint32_t base, size_t size); int espi_open_mmio_window(uint32_t base, size_t size);
/*
* Configure generic and standard I/O decode windows using the espi_config structure settings
* provided by mainboard in device tree.
*/
void espi_configure_decodes(void);
/* /*
* Clear all configured eSPI memory and I/O decode ranges. This is useful for changing * Clear all configured eSPI memory and I/O decode ranges. This is useful for changing
* the decodes, or if something else has previously setup decode windows that conflict * the decodes, or if something else has previously setup decode windows that conflict

View File

@ -298,19 +298,22 @@ static const struct espi_config *espi_get_config(void)
return &soc_cfg->espi_config; return &soc_cfg->espi_config;
} }
void espi_configure_decodes(void) static int espi_configure_decodes(const struct espi_config *cfg)
{ {
int i; int i, ret;
const struct espi_config *cfg = espi_get_config();
espi_enable_decode(cfg->std_io_decode_bitmap); espi_enable_decode(cfg->std_io_decode_bitmap);
for (i = 0; i < ESPI_GENERIC_IO_WIN_COUNT; i++) { for (i = 0; i < ESPI_GENERIC_IO_WIN_COUNT; i++) {
if (cfg->generic_io_range[i].size == 0) if (cfg->generic_io_range[i].size == 0)
continue; continue;
espi_open_generic_io_window(cfg->generic_io_range[i].base, ret = espi_open_generic_io_window(cfg->generic_io_range[i].base,
cfg->generic_io_range[i].size); cfg->generic_io_range[i].size);
if (ret)
return ret;
} }
return 0;
} }
#define ESPI_DN_TX_HDR0 0x00 #define ESPI_DN_TX_HDR0 0x00
@ -966,6 +969,11 @@ int espi_setup(void)
return -1; return -1;
} }
if (espi_configure_decodes(cfg) == -1) {
printk(BIOS_ERR, "Error: Configuring decodes failed!\n");
return -1;
}
/* Enable subtractive decode if configured */ /* Enable subtractive decode if configured */
espi_setup_subtractive_decode(cfg); espi_setup_subtractive_decode(cfg);

View File

@ -77,8 +77,6 @@ void fch_early_init(void)
if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING)) if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING))
lpc_disable_spi_rom_sharing(); lpc_disable_spi_rom_sharing();
if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) { if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI))
espi_setup(); espi_setup();
espi_configure_decodes();
}
} }

View File

@ -153,8 +153,6 @@ uint32_t verstage_soc_early_init(void)
void verstage_soc_init(void) void verstage_soc_init(void)
{ {
if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) { if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI))
espi_setup(); espi_setup();
espi_configure_decodes();
}
} }