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soc/intel/alderlake: Enable CSE Lite driver for ADL platform in romstage

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This patch sets up cse_fw_sync() call in the romstage. The cse_fw_sync()
must be called after DRAM initialization.

Test=Verified on Alderlake platform

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I6779f4a9e140deebf7f3cecd9fc5dac18813f246
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Sridhar Siricilla 2021-03-12 18:28:03 +05:30 committed by Patrick Georgi
parent 4248d8e7bb
commit 61dd05e010
1 changed files with 10 additions and 1 deletions
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11
src/soc/intel/alderlake/romstage/romstage.c
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@ -129,6 +129,15 @@ void mainboard_romstage_entry(void)
s3wake = pmc_fill_power_state(ps) == ACPI_S3; s3wake = pmc_fill_power_state(ps) == ACPI_S3;
fsp_memory_init(s3wake); fsp_memory_init(s3wake);
pmc_set_disb(); pmc_set_disb();
if (!s3wake) if (!s3wake) {
/*
* cse_fw_sync() must be called after DRAM initialization as
* HMRFPO_ENABLE HECI command (which is used by cse_fw_sync())
* is expected to be executed after DRAM initialization.
*/
if (CONFIG(SOC_INTEL_CSE_LITE_SKU))
cse_fw_sync();
save_dimm_info(); save_dimm_info();
}
} }