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nb/intel/haswell: Uniformize include guards 

Remove leading and trailing underscores and change `RAMINIT_H` to be
more consistent with other headers.

Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.

Change-Id: Ie20fcaa0f9393eb0a34054eda53b9bade63cc0d2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51890
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2021-03-27 21:13:44 +01:00 committed by Patrick Georgi
parent 9fa141898e
commit 6237175ed5
7 changed files with 21 additions and 21 deletions
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6
src/northbridge/intel/haswell/haswell.h
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@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__ #ifndef NORTHBRIDGE_INTEL_HASWELL_HASWELL_H
#define __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__ #define NORTHBRIDGE_INTEL_HASWELL_HASWELL_H
#include <device/device.h> #include <device/device.h>
#include <northbridge/intel/common/fixed_bars.h> #include <northbridge/intel/common/fixed_bars.h>
@ -68,4 +68,4 @@ struct acpi_rsdp;
unsigned long northbridge_write_acpi_tables(const struct device *device, unsigned long start, unsigned long northbridge_write_acpi_tables(const struct device *device, unsigned long start,
struct acpi_rsdp *rsdp); struct acpi_rsdp *rsdp);
#endif /* __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__ */ #endif /* NORTHBRIDGE_INTEL_HASWELL_HASWELL_H */

6
src/northbridge/intel/haswell/memmap.h
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@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __NORTHBRIDGE_INTEL_HASWELL_MEMMAP_H__ #ifndef NORTHBRIDGE_INTEL_HASWELL_MEMMAP_H
#define __NORTHBRIDGE_INTEL_HASWELL_MEMMAP_H__ #define NORTHBRIDGE_INTEL_HASWELL_MEMMAP_H
#define GFXVT_BASE_ADDRESS 0xfed90000ULL #define GFXVT_BASE_ADDRESS 0xfed90000ULL
#define GFXVT_BASE_SIZE 0x1000 #define GFXVT_BASE_SIZE 0x1000
@ -9,4 +9,4 @@
#define VTVC0_BASE_ADDRESS 0xfed91000ULL #define VTVC0_BASE_ADDRESS 0xfed91000ULL
#define VTVC0_BASE_SIZE 0x1000 #define VTVC0_BASE_SIZE 0x1000
#endif /* __NORTHBRIDGE_INTEL_HASWELL_MEMMAP_H__ */ #endif /* NORTHBRIDGE_INTEL_HASWELL_MEMMAP_H */

6
src/northbridge/intel/haswell/raminit.h
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@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#ifndef RAMINIT_H #ifndef NORTHBRIDGE_INTEL_HASWELL_RAMINIT_H
#define RAMINIT_H #define NORTHBRIDGE_INTEL_HASWELL_RAMINIT_H
#include <types.h> #include <types.h>
@ -17,4 +17,4 @@ void mb_get_spd_map(struct spd_info *spdi);
void perform_raminit(const int s3resume); void perform_raminit(const int s3resume);
#endif /* RAMINIT_H */ #endif /* NORTHBRIDGE_INTEL_HASWELL_RAMINIT_H */

6
src/northbridge/intel/haswell/registers/dmibar.h
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@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __HASWELL_REGISTERS_DMIBAR_H__ #ifndef HASWELL_REGISTERS_DMIBAR_H
#define __HASWELL_REGISTERS_DMIBAR_H__ #define HASWELL_REGISTERS_DMIBAR_H
#define DMIVCECH 0x000 /* 32bit */ #define DMIVCECH 0x000 /* 32bit */
#define DMIPVCCAP1 0x004 /* 32bit */ #define DMIPVCCAP1 0x004 /* 32bit */
@ -53,4 +53,4 @@
#define DMI_AFE_PM_TMR 0xc28 /* 32bit */ #define DMI_AFE_PM_TMR 0xc28 /* 32bit */
#endif /* __HASWELL_REGISTERS_DMIBAR_H__ */ #endif /* HASWELL_REGISTERS_DMIBAR_H */

6
src/northbridge/intel/haswell/registers/epbar.h
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@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __HASWELL_REGISTERS_EPBAR_H__ #ifndef HASWELL_REGISTERS_EPBAR_H
#define __HASWELL_REGISTERS_EPBAR_H__ #define HASWELL_REGISTERS_EPBAR_H
#define EPPVCCAP1 0x004 /* 32bit */ #define EPPVCCAP1 0x004 /* 32bit */
#define EPPVCCAP2 0x008 /* 32bit */ #define EPPVCCAP2 0x008 /* 32bit */
@ -25,4 +25,4 @@
#define EPLE4D 0x080 /* 32bit */ #define EPLE4D 0x080 /* 32bit */
#define EPLE4A 0x088 /* 64bit */ #define EPLE4A 0x088 /* 64bit */
#endif /* __HASWELL_REGISTERS_EPBAR_H__ */ #endif /* HASWELL_REGISTERS_EPBAR_H */

6
src/northbridge/intel/haswell/registers/host_bridge.h
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@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __HASWELL_REGISTERS_HOST_BRIDGE_H__ #ifndef HASWELL_REGISTERS_HOST_BRIDGE_H
#define __HASWELL_REGISTERS_HOST_BRIDGE_H__ #define HASWELL_REGISTERS_HOST_BRIDGE_H
#define EPBAR 0x40 #define EPBAR 0x40
#define MCHBAR 0x48 #define MCHBAR 0x48
@ -71,4 +71,4 @@
#define CAPID0_B 0xe8 #define CAPID0_B 0xe8
#endif /* __HASWELL_REGISTERS_HOST_BRIDGE_H__ */ #endif /* HASWELL_REGISTERS_HOST_BRIDGE_H */

6
src/northbridge/intel/haswell/registers/mchbar.h
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@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __HASWELL_REGISTERS_MCHBAR_H__ #ifndef HASWELL_REGISTERS_MCHBAR_H
#define __HASWELL_REGISTERS_MCHBAR_H__ #define HASWELL_REGISTERS_MCHBAR_H
/* Memory controller characteristics */ /* Memory controller characteristics */
#define NUM_CHANNELS 2 #define NUM_CHANNELS 2
@ -74,4 +74,4 @@
#define CRDTLCK 0x77fc #define CRDTLCK 0x77fc
#define MCARBLCK 0x7ffc #define MCARBLCK 0x7ffc
#endif /* __HASWELL_REGISTERS_MCHBAR_H__ */ #endif /* HASWELL_REGISTERS_MCHBAR_H */