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mb/ocp, soc/intel/xeon_sp: Use common ASL POST defines 

Use common ASL defines for POST code handling.

Change-Id: I5b4c11860a8c33e56edaea0f6de378cbaa63a8c5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63989
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2022-05-02 16:58:39 +02:00 committed by Felix Held
parent f0ed846cfc
commit 623e2b351c
3 changed files with 3 additions and 15 deletions
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8
src/mainboard/ocp/deltalake/acpi/platform.asl
View File

@ -21,13 +21,7 @@ Field (APMP, ByteAcc, NoLock, Preserve)
APMS, 8 // APM status
}
/* Port 80 POST */
OperationRegion (DBG0, SystemIO, 0x80, 0x02)
Field (DBG0, ByteAcc, Lock, Preserve)
{
IO80, 8,
IO81, 8
}
#include <arch/x86/acpi/post.asl>
/* IO-Trap at 0x800.
* This is the ACPI->SMI communication interface.

8
src/mainboard/ocp/tiogapass/acpi/platform.asl
View File

@ -21,13 +21,7 @@ Field (APMP, ByteAcc, NoLock, Preserve)
APMS, 8 // APM status
}
/* Port 80 POST */
OperationRegion (DBG0, SystemIO, 0x80, 0x02)
Field (DBG0, ByteAcc, Lock, Preserve)
{
IO80, 8,
IO81, 8
}
#include <arch/x86/acpi/post.asl>
/* IO-Trap at 0x800.
* This is the ACPI->SMI communication interface.

2
src/soc/intel/xeon_sp/acpi/iiostack.asl
View File

@ -58,7 +58,7 @@
{ \
/* indicate unrecognized UUID */ \
CDW1 |= 0x04 \
IO80 = 0xEE \
DBG0 = 0xEE \
Return (Arg3) \
} \
} \