arch/x86/acpi: Consolidate POST code handling

Move ASL POST code declarations into a common file to avoid redundancy.
Also, provide a dummy implementation when `POST_IO` is not enabled, as
the value of `CONFIG_POST_IO_PORT` can't be used.

Change-Id: I891bd8754f10f16d618e76e1ab88c26164776a50
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>

src/arch/x86/acpi/post.asl

@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#if CONFIG(POST_IO)
+
+/* POST code support, typically on port 80 */
+OperationRegion (POST, SystemIO, CONFIG_POST_IO_PORT, 1)
+Field (POST, ByteAcc, Lock, Preserve)
+{
+	DBG0, 8
+}
+
+#else
+
+/* Dummy placeholder to avoid issues */
+Name (DBG0, 0)
+
+#endif

src/mainboard/asus/p2b/dsdt.asl

@@ -22,13 +22,7 @@ DefinitionBlock (
 	#include <acpi/dsdt_top.asl>
 	/* \_SB scope defining the main processor is generated in SSDT. */
 
-	/* Port 80 POST */
-
-	OperationRegion (POST, SystemIO, 0x80, 1)
-	Field (POST, ByteAcc, Lock, Preserve)
-	{
-		DBG0, 8
-	}
+	#include <arch/x86/acpi/post.asl>
 
 	/*
 	 * Intel 82371EB (PIIX4E) datasheet, section 7.2.3, page 142

src/mainboard/intel/cedarisland_crb/acpi/platform.asl

@@ -9,13 +9,7 @@ Field (APMP, ByteAcc, NoLock, Preserve)
 	APMS, 8		// APM status
 }
 
-/* Port 80 POST */
-
-OperationRegion (POST, SystemIO, 0x80, 1)
-Field (POST, ByteAcc, Lock, Preserve)
-{
-	DBG0, 8
-}
+#include <arch/x86/acpi/post.asl>
 
 Name(\APC1, Zero) // IIO IOAPIC
 

src/soc/intel/common/acpi/platform.asl

@@ -7,13 +7,7 @@ External(\_SB.MWAK, MethodObj)
 External(\_SB.PCI0.EGPM, MethodObj)
 External(\_SB.PCI0.RGPM, MethodObj)
 
-/* Port 80 POST */
-
-OperationRegion (POST, SystemIO, CONFIG_POST_IO_PORT, 1)
-Field (POST, ByteAcc, Lock, Preserve)
-{
-	DBG0, 8
-}
+#include <arch/x86/acpi/post.asl>
 
 /*
  * The _PTS method (Prepare To Sleep) is called before the OS is

src/southbridge/intel/common/acpi/platform.asl

@@ -9,13 +9,7 @@ Field (APMP, ByteAcc, NoLock, Preserve)
 	APMS, 8		// APM status
 }
 
-/* Port 80 POST */
-
-OperationRegion (POST, SystemIO, 0x80, 1)
-Field (POST, ByteAcc, Lock, Preserve)
-{
-	DBG0, 8
-}
+#include <arch/x86/acpi/post.asl>
 
 #if CONFIG(ACPI_SOC_NVS)
 /* SMI I/O Trap */