mb/hp: Add new port compaq_8200_elite_sff
Add new port based on autoport. The board uses a NPCD378 SuperIO, that is full of custom hardware. The 8MiB flash SOIC-8 can be accessed after cutting of a part of the DIMM slot holder. The flash IC has no diode, powering a part of the board while flashing externaly, including the Standby-LED. The following have been tested and is working: * Native raminit with up to four DIMMs * Libgfxinit on DisplayPort * USB * EHCI debug * Serial on RS232 * Ethernet * PCIe on x4 * PCIe on x16 * SATA * Booting GNU Linux 4.14 using SeaBIOS 1.11.1 as payload * Flashing internaly * PS/2 is working Untested: * PCI slot * LPT port * VBIOS * S3 resume Not working: * PSU fan managment (runs at 100%) * Half of SuperIO functionality is unknown TODO: * Reverse engineer remaining SuperIO registers * Reverse engineer SMM Fixes on follow-up commits: * Added PSU fan control * Reverse engineered some of Super IO's HWM registers * Added SMBIOS tables for IPMI Change-Id: I4ee8da6349222fda8b6c30a7210ffdd65c183439 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/25385 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Patrick Rudolph
Patrick Rudolph
parent
21fa51475d
commit
6308e0e92f
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@ -0,0 +1,64 @@
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if BOARD_HEWLETT_PACKARD_HP_COMPAQ_8200_ELITE_SFF_PC
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select BOARD_ROMSIZE_KB_8192
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select CPU_INTEL_SOCKET_LGA1155
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select INTEL_INT15
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select NORTHBRIDGE_INTEL_SANDYBRIDGE
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select SERIRQ_CONTINUOUS_MODE
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select SOUTHBRIDGE_INTEL_BD82X6X
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select USE_NATIVE_RAMINIT
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select MAINBOARD_HAS_LPC_TPM
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select TPM
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select HAVE_OPTION_TABLE
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select HAVE_CMOS_DEFAULT
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select SUPERIO_NUVOTON_NPCD378
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select MAINBOARD_HAS_LIBGFXINIT
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config HAVE_IFD_BIN
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bool
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default n
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config HAVE_ME_BIN
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bool
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default n
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config MAINBOARD_DIR
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string
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default hp/compaq_8200_elite_sff
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config MAINBOARD_PART_NUMBER
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string
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default "HP Compaq 8200 Elite SFF PC"
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config VGA_BIOS_FILE
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string
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default "pci8086,0102.rom"
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config VGA_BIOS_ID
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string
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default "8086,0102"
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config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
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hex
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default 0x1495
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config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
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hex
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default 0x103c
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config DRAM_RESET_GATE_GPIO
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int
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default 60
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config MAX_CPUS
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int
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default 8
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config USBDEBUG_HCD_INDEX
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int
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default 2
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endif
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@ -0,0 +1,2 @@
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config BOARD_HEWLETT_PACKARD_HP_COMPAQ_8200_ELITE_SFF_PC
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bool "Compaq 8200 Elite SFF"
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@ -0,0 +1,2 @@
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romstage-y += gpio.c
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ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
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@ -0,0 +1,23 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2018 Patrick Rudolph <siro@das-labor.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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Method(_WAK,1)
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{
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Return(Package(){0,0})
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}
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Method(_PTS,1)
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{
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}
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@ -0,0 +1,25 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2018 Patrick Rudolph <siro@das-labor.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#undef SUPERIO_DEV
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#undef SUPERIO_PNP_BASE
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#define SUPERIO_DEV SIO0
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#define SUPERIO_PNP_BASE 0x2e
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#define SUPERIO_SHOW_SP2
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#define SUPERIO_SHOW_KBC
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#include <superio/nuvoton/npcd378/acpi/superio.asl>
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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* Copyright (C) 2014 Vladimir Serbinenko
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* Copyright (C) 2018 Patrick Rudolph <siro@das-labor.org>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <southbridge/intel/bd82x6x/nvs.h>
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void acpi_create_gnvs(global_nvs_t *gnvs)
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{
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/* Disable USB ports in S3 by default */
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gnvs->s3u0 = 0;
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gnvs->s3u1 = 0;
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/* Disable USB ports in S5 by default */
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gnvs->s5u0 = 0;
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gnvs->s5u1 = 0;
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gnvs->tcrt = 100;
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gnvs->tpsv = 90;
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}
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@ -0,0 +1,7 @@
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Category: desktop
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Board URL: https://support.hp.com/de-de/product/HP-Compaq-8200-Elite-Small-Form-Factor-PC/5037931
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ROM IC: MX25L6405
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ROM package: SOIC-8
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ROM socketed: no
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Flashrom support: yes
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Release year: 2013
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@ -0,0 +1,6 @@
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boot_option=Fallback
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debug_level=Spew
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power_on_after_fail=Enable
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nmi=Enable
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sata_mode=AHCI
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gfx_uma_size=32M
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@ -0,0 +1,112 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007-2008 coresystems GmbH
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## Copyright (C) 2014 Vladimir Serbinenko
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## Copyright (C) 2018 Patrick Rudolph <siro@das-labor.org>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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# -----------------------------------------------------------------
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entries
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# -----------------------------------------------------------------
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# Status Register A
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# -----------------------------------------------------------------
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# Status Register B
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# -----------------------------------------------------------------
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# Status Register C
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#96 4 r 0 status_c_rsvd
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#100 1 r 0 uf_flag
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#101 1 r 0 af_flag
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#102 1 r 0 pf_flag
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#103 1 r 0 irqf_flag
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# -----------------------------------------------------------------
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# Status Register D
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#104 7 r 0 status_d_rsvd
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#111 1 r 0 valid_cmos_ram
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# -----------------------------------------------------------------
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# Diagnostic Status Register
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#112 8 r 0 diag_rsvd1
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# -----------------------------------------------------------------
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0 120 r 0 reserved_memory
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#120 264 r 0 unused
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# -----------------------------------------------------------------
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# RTC_BOOT_BYTE (coreboot hardcoded)
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384 1 e 4 boot_option
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388 4 h 0 reboot_counter
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#390 2 r 0 unused?
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# -----------------------------------------------------------------
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# coreboot config options: console
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#392 3 r 0 unused
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395 4 e 6 debug_level
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#399 9 r 0 unused
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# coreboot config options: southbridge
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408 1 e 1 nmi
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409 2 e 7 power_on_after_fail
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#411 10 r 0 unused
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421 1 e 9 sata_mode
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#422 10 r 0 unused
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# coreboot config options: northbridge
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432 3 e 11 gfx_uma_size
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#435 549 r 0 unused
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# SandyBridge MRC Scrambler Seed values
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896 32 r 0 mrc_scrambler_seed
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928 32 r 0 mrc_scrambler_seed_s3
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960 16 r 0 mrc_scrambler_seed_chk
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# coreboot config options: check sums
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984 16 h 0 check_sum
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# -----------------------------------------------------------------
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enumerations
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#ID value text
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1 0 Disable
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1 1 Enable
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2 0 Enable
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2 1 Disable
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4 0 Fallback
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4 1 Normal
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6 0 Emergency
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6 1 Alert
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6 2 Critical
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6 3 Error
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6 4 Warning
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6 5 Notice
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6 6 Info
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6 7 Debug
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6 8 Spew
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7 0 Disable
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7 1 Enable
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7 2 Keep
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9 0 AHCI
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9 1 IDE
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11 0 32M
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11 1 64M
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11 2 96M
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11 3 128M
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11 4 160M
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11 5 192M
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11 6 224M
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# -----------------------------------------------------------------
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checksums
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checksum 392 415 984
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@ -0,0 +1,226 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2018 Patrick Rudolph <siro@das-labor.org>
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##
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## This program is free software; you can redistribute it and/or
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## modify it under the terms of the GNU General Public License as
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## published by the Free Software Foundation; version 2 of
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## the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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chip northbridge/intel/sandybridge
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register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }"
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register "gfx.link_frequency_270_mhz" = "0"
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register "gfx.ndid" = "3"
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register "gfx.use_spread_spectrum_clock" = "0"
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register "gpu_dp_b_hotplug" = "0"
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register "gpu_dp_c_hotplug" = "0"
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register "gpu_dp_d_hotplug" = "0"
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device cpu_cluster 0x0 on
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chip cpu/intel/socket_LGA1155
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device lapic 0x0 on
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end
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end
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chip cpu/intel/model_206ax
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register "c1_acpower" = "1"
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register "c1_battery" = "1"
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register "c2_acpower" = "3"
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register "c2_battery" = "3"
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register "c3_acpower" = "5"
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register "c3_battery" = "5"
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device lapic 0xacac off
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end
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end
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end
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register "pci_mmio_size" = "2048"
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device domain 0x0 on
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chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
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register "c2_latency" = "0x0065"
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register "docking_supported" = "0"
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register "gen1_dec" = "0x00fc0601"
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register "gen2_dec" = "0x00fc0801"
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register "p_cnt_throttling_supported" = "1"
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register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
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register "pcie_port_coalesce" = "1"
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register "sata_interface_speed_support" = "0x3"
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register "sata_port_map" = "0x13"
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register "spi_lvscc" = "0x2005"
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register "spi_uvscc" = "0x0"
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device pci 16.0 on # Management Engine Interface 1
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subsystemid 0x103c 0x1495
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end
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device pci 16.1 off # Management Engine Interface 2
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end
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device pci 16.2 off # Management Engine IDE-R
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end
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device pci 16.3 on # Management Engine KT
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subsystemid 0x103c 0x1495
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end
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device pci 19.0 on # Intel Gigabit Ethernet
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subsystemid 0x103c 0x1495
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end
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device pci 1a.0 on # USB2 EHCI #2
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subsystemid 0x103c 0x1495
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end
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device pci 1b.0 on # High Definition Audio Audio controller
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subsystemid 0x103c 0x1495
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end
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device pci 1c.0 on # PCIe Port #1
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subsystemid 0x103c 0x1495
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end
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device pci 1c.1 off # PCIe Port #2
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end
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device pci 1c.2 off # PCIe Port #3
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end
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device pci 1c.3 off # PCIe Port #4
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end
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device pci 1c.4 on # PCIe Port #5
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subsystemid 0x103c 0x1495
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end
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device pci 1c.5 off # PCIe Port #6
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end
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device pci 1c.6 on # PCIe Port #7
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subsystemid 0x103c 0x1495
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end
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device pci 1c.7 on # PCIe Port #8
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subsystemid 0x103c 0x1495
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end
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device pci 1d.0 on # USB2 EHCI #1
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subsystemid 0x103c 0x1495
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end
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device pci 1e.0 on # PCI bridge
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subsystemid 0x103c 0x1495
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end
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device pci 1f.0 on # LPC bridge PCI-LPC bridge
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subsystemid 0x103c 0x1495
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chip superio/nuvoton/npcd378
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device pnp 2e.0 off end # Floppy
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device pnp 2e.1 on # Parallel port
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# global
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# serialice: Vendor writes:
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irq 0x14 = 0x9c
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irq 0x1c = 0xa8
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irq 0x1d = 0x08
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irq 0x22 = 0x3f
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irq 0x1a = 0xb0
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# dumped from superiotool:
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irq 0x1b = 0x1e
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irq 0x27 = 0x04
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irq 0x2a = 0x00
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irq 0x2d = 0x01
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# parallel port
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io 0x60 = 0x378
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irq 0x70 = 0x07
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drq 0x74 = 0x01
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end
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device pnp 2e.2 off # COM1
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io 0x60 = 0x2f8
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irq 0x70 = 3
|
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end
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device pnp 2e.3 on # COM2, IR
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io 0x60 = 0x3f8
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irq 0x70 = 4
|
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end
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device pnp 2e.4 on # LED control
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io 0x60 = 0x600
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# IOBASE[0h] = bit0 LED red / green
|
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# IOBASE[0h] = bit1-4 LED PWM duty cycle
|
||||
# IOBASE[1h] = bit6 SWCC
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io 0x62 = 0x610
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# IOBASE [0h] = GPES
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# IOBASE [1h] = GPEE
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# IOBASE [4h:7h] = 32bit upcounter at 1Mhz
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# IOBASE [8h:bh] = GPS
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# IOBASE [ch:fh] = GPE
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||||
end
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device pnp 2e.5 on # Mouse
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irq 0x70 = 0xc
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end
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device pnp 2e.6 on # Keyboard
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io 0x60 = 0x0060
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io 0x62 = 0x0064
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irq 0x70 = 0x01
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||||
# serialice: Vendor writes:
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drq 0xf0 = 0x40
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||||
end
|
||||
device pnp 2e.7 on # WDT ?
|
||||
io 0x60 = 0x620
|
||||
end
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||||
device pnp 2e.8 on # HWM
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||||
io 0x60 = 0x800
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||||
# IOBASE[0h:feh] HWM page
|
||||
# IOBASE[ffh] bit0-bit3 page selector
|
||||
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||||
drq 0xf0 = 0x20
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||||
drq 0xf1 = 0x01
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||||
drq 0xf2 = 0x40
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||||
drq 0xf3 = 0x01
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||||
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||||
drq 0xf4 = 0x66
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||||
drq 0xf5 = 0x67
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||||
drq 0xf6 = 0x66
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||||
drq 0xf7 = 0x01
|
||||
end
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||||
device pnp 2e.f on # GPIO OD ?
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||||
drq 0xf1 = 0x97
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||||
drq 0xf2 = 0x01
|
||||
drq 0xf5 = 0x08
|
||||
drq 0xfe = 0x80
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||||
end
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||||
device pnp 2e.15 on # BUS ?
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||||
io 0x60 = 0x0680
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||||
io 0x62 = 0x0690
|
||||
end
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||||
device pnp 2e.1c on # Suspend Control ?
|
||||
io 0x60 = 0x640
|
||||
# writing to IOBASE[5h]
|
||||
# 0x0: Power off
|
||||
# 0x9: Power off and bricked until CMOS battery removed
|
||||
end
|
||||
device pnp 2e.1e on # GPIO ?
|
||||
io 0x60 = 0x660
|
||||
drq 0xf4 = 0x01
|
||||
# skip the following, as it
|
||||
# looks like remapped registers
|
||||
#drq 0xf5 = 0x06
|
||||
#drq 0xf6 = 0x60
|
||||
#drq 0xfe = 0x03
|
||||
end
|
||||
end
|
||||
end
|
||||
chip drivers/pc80/tpm
|
||||
device pnp 4e.0 on end # TPM module
|
||||
end
|
||||
device pci 1f.2 on # SATA Controller 1
|
||||
subsystemid 0x103c 0x1495
|
||||
end
|
||||
device pci 1f.3 on # SMBus
|
||||
subsystemid 0x103c 0x1495
|
||||
end
|
||||
device pci 1f.5 off # SATA Controller 2
|
||||
end
|
||||
device pci 1f.6 off # Thermal
|
||||
end
|
||||
end
|
||||
device pci 00.0 on # Host bridge Host bridge
|
||||
subsystemid 0x103c 0x1495
|
||||
end
|
||||
device pci 01.0 on # PCIe Bridge for discrete graphics
|
||||
subsystemid 0x103c 0x1495
|
||||
end
|
||||
device pci 02.0 on # Internal graphics VGA controller
|
||||
subsystemid 0x103c 0x1495
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2018 Patrick Rudolph <siro@das-labor.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
|
||||
#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
|
||||
#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
|
||||
DefinitionBlock(
|
||||
"dsdt.aml",
|
||||
"DSDT",
|
||||
0x03, // DSDT revision: ACPI v3.0
|
||||
"COREv4", // OEM id
|
||||
"COREBOOT", // OEM table id
|
||||
0x20141018 // OEM revision
|
||||
)
|
||||
{
|
||||
// Some generic macros
|
||||
#include "acpi/platform.asl"
|
||||
#include <cpu/intel/model_206ax/acpi/cpu.asl>
|
||||
#include <southbridge/intel/bd82x6x/acpi/platform.asl>
|
||||
/* global NVS and variables. */
|
||||
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
|
||||
#include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
|
||||
|
||||
Scope (\_SB) {
|
||||
Device (PCI0)
|
||||
{
|
||||
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
|
||||
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
|
||||
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
--
|
||||
-- Copyright (C) 2018 Patrick Rudolph <siro@das-labor.org>
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
|
||||
with HW.GFX.GMA;
|
||||
with HW.GFX.GMA.Display_Probing;
|
||||
|
||||
use HW.GFX.GMA;
|
||||
use HW.GFX.GMA.Display_Probing;
|
||||
|
||||
private package GMA.Mainboard is
|
||||
|
||||
ports : constant Port_List :=
|
||||
(DP2,
|
||||
HDMI2,
|
||||
Analog,
|
||||
others => Disabled);
|
||||
|
||||
end GMA.Mainboard;
|
||||
|
|
@ -0,0 +1,209 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008-2009 coresystems GmbH
|
||||
* Copyright (C) 2014 Vladimir Serbinenko
|
||||
* Copyright (C) 2018 Patrick Rudolph <siro@das-labor.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of
|
||||
* the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <southbridge/intel/common/gpio.h>
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_mode = {
|
||||
.gpio0 = GPIO_MODE_GPIO,
|
||||
.gpio1 = GPIO_MODE_GPIO,
|
||||
.gpio2 = GPIO_MODE_NATIVE,
|
||||
.gpio3 = GPIO_MODE_NATIVE,
|
||||
.gpio4 = GPIO_MODE_NATIVE,
|
||||
.gpio5 = GPIO_MODE_NATIVE,
|
||||
.gpio6 = GPIO_MODE_GPIO,
|
||||
.gpio7 = GPIO_MODE_GPIO,
|
||||
.gpio8 = GPIO_MODE_GPIO,
|
||||
.gpio9 = GPIO_MODE_NATIVE,
|
||||
.gpio10 = GPIO_MODE_NATIVE,
|
||||
.gpio11 = GPIO_MODE_NATIVE,
|
||||
.gpio12 = GPIO_MODE_NATIVE,
|
||||
.gpio13 = GPIO_MODE_GPIO,
|
||||
.gpio14 = GPIO_MODE_NATIVE,
|
||||
.gpio15 = GPIO_MODE_GPIO,
|
||||
.gpio16 = GPIO_MODE_GPIO,
|
||||
.gpio17 = GPIO_MODE_GPIO,
|
||||
.gpio18 = GPIO_MODE_NATIVE,
|
||||
.gpio19 = GPIO_MODE_GPIO,
|
||||
.gpio20 = GPIO_MODE_NATIVE,
|
||||
.gpio21 = GPIO_MODE_GPIO,
|
||||
.gpio22 = GPIO_MODE_GPIO,
|
||||
.gpio23 = GPIO_MODE_NATIVE,
|
||||
.gpio24 = GPIO_MODE_GPIO,
|
||||
.gpio25 = GPIO_MODE_NATIVE,
|
||||
.gpio26 = GPIO_MODE_NATIVE,
|
||||
.gpio27 = GPIO_MODE_GPIO,
|
||||
.gpio28 = GPIO_MODE_GPIO,
|
||||
.gpio29 = GPIO_MODE_GPIO,
|
||||
.gpio30 = GPIO_MODE_NATIVE,
|
||||
.gpio31 = GPIO_MODE_GPIO,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_direction = {
|
||||
.gpio0 = GPIO_DIR_INPUT,
|
||||
.gpio1 = GPIO_DIR_INPUT,
|
||||
.gpio6 = GPIO_DIR_INPUT,
|
||||
.gpio7 = GPIO_DIR_INPUT,
|
||||
.gpio8 = GPIO_DIR_INPUT,
|
||||
.gpio13 = GPIO_DIR_INPUT,
|
||||
.gpio15 = GPIO_DIR_OUTPUT,
|
||||
.gpio16 = GPIO_DIR_INPUT,
|
||||
.gpio17 = GPIO_DIR_OUTPUT,
|
||||
.gpio19 = GPIO_DIR_INPUT,
|
||||
.gpio21 = GPIO_DIR_INPUT,
|
||||
.gpio22 = GPIO_DIR_INPUT,
|
||||
.gpio24 = GPIO_DIR_INPUT,
|
||||
.gpio27 = GPIO_DIR_INPUT,
|
||||
.gpio28 = GPIO_DIR_OUTPUT,
|
||||
.gpio29 = GPIO_DIR_OUTPUT,
|
||||
.gpio31 = GPIO_DIR_INPUT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_level = {
|
||||
.gpio15 = GPIO_LEVEL_LOW,
|
||||
.gpio17 = GPIO_LEVEL_HIGH,
|
||||
.gpio28 = GPIO_LEVEL_LOW,
|
||||
.gpio29 = GPIO_LEVEL_HIGH,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_reset = {
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_invert = {
|
||||
.gpio0 = GPIO_INVERT,
|
||||
.gpio1 = GPIO_INVERT,
|
||||
.gpio6 = GPIO_INVERT,
|
||||
.gpio7 = GPIO_INVERT,
|
||||
.gpio13 = GPIO_INVERT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_blink = {
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_mode = {
|
||||
.gpio32 = GPIO_MODE_GPIO,
|
||||
.gpio33 = GPIO_MODE_GPIO,
|
||||
.gpio34 = GPIO_MODE_GPIO,
|
||||
.gpio35 = GPIO_MODE_GPIO,
|
||||
.gpio36 = GPIO_MODE_GPIO,
|
||||
.gpio37 = GPIO_MODE_GPIO,
|
||||
.gpio38 = GPIO_MODE_GPIO,
|
||||
.gpio39 = GPIO_MODE_GPIO,
|
||||
.gpio40 = GPIO_MODE_NATIVE,
|
||||
.gpio41 = GPIO_MODE_NATIVE,
|
||||
.gpio42 = GPIO_MODE_NATIVE,
|
||||
.gpio43 = GPIO_MODE_GPIO,
|
||||
.gpio44 = GPIO_MODE_NATIVE,
|
||||
.gpio45 = GPIO_MODE_NATIVE,
|
||||
.gpio46 = GPIO_MODE_GPIO,
|
||||
.gpio47 = GPIO_MODE_NATIVE,
|
||||
.gpio48 = GPIO_MODE_GPIO,
|
||||
.gpio49 = GPIO_MODE_GPIO,
|
||||
.gpio50 = GPIO_MODE_NATIVE,
|
||||
.gpio51 = GPIO_MODE_NATIVE,
|
||||
.gpio52 = GPIO_MODE_NATIVE,
|
||||
.gpio53 = GPIO_MODE_NATIVE,
|
||||
.gpio54 = GPIO_MODE_GPIO,
|
||||
.gpio55 = GPIO_MODE_NATIVE,
|
||||
.gpio56 = GPIO_MODE_NATIVE,
|
||||
.gpio57 = GPIO_MODE_GPIO,
|
||||
.gpio58 = GPIO_MODE_NATIVE,
|
||||
.gpio59 = GPIO_MODE_NATIVE,
|
||||
.gpio60 = GPIO_MODE_GPIO,
|
||||
.gpio61 = GPIO_MODE_GPIO,
|
||||
.gpio62 = GPIO_MODE_NATIVE,
|
||||
.gpio63 = GPIO_MODE_NATIVE,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_direction = {
|
||||
.gpio32 = GPIO_DIR_INPUT,
|
||||
.gpio33 = GPIO_DIR_INPUT,
|
||||
.gpio34 = GPIO_DIR_INPUT,
|
||||
.gpio35 = GPIO_DIR_INPUT,
|
||||
.gpio36 = GPIO_DIR_INPUT,
|
||||
.gpio37 = GPIO_DIR_INPUT,
|
||||
.gpio38 = GPIO_DIR_INPUT,
|
||||
.gpio39 = GPIO_DIR_INPUT,
|
||||
.gpio43 = GPIO_DIR_INPUT,
|
||||
.gpio46 = GPIO_DIR_INPUT,
|
||||
.gpio48 = GPIO_DIR_INPUT,
|
||||
.gpio49 = GPIO_DIR_INPUT,
|
||||
.gpio54 = GPIO_DIR_INPUT,
|
||||
.gpio57 = GPIO_DIR_INPUT,
|
||||
.gpio60 = GPIO_DIR_OUTPUT,
|
||||
.gpio61 = GPIO_DIR_OUTPUT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_level = {
|
||||
.gpio60 = GPIO_LEVEL_HIGH,
|
||||
.gpio61 = GPIO_LEVEL_HIGH,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_reset = {
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set3 pch_gpio_set3_mode = {
|
||||
.gpio64 = GPIO_MODE_NATIVE,
|
||||
.gpio65 = GPIO_MODE_NATIVE,
|
||||
.gpio66 = GPIO_MODE_NATIVE,
|
||||
.gpio67 = GPIO_MODE_NATIVE,
|
||||
.gpio68 = GPIO_MODE_GPIO,
|
||||
.gpio69 = GPIO_MODE_GPIO,
|
||||
.gpio70 = GPIO_MODE_GPIO,
|
||||
.gpio71 = GPIO_MODE_GPIO,
|
||||
.gpio72 = GPIO_MODE_GPIO,
|
||||
.gpio73 = GPIO_MODE_NATIVE,
|
||||
.gpio74 = GPIO_MODE_NATIVE,
|
||||
.gpio75 = GPIO_MODE_NATIVE,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set3 pch_gpio_set3_direction = {
|
||||
.gpio68 = GPIO_DIR_INPUT,
|
||||
.gpio69 = GPIO_DIR_INPUT,
|
||||
.gpio70 = GPIO_DIR_INPUT,
|
||||
.gpio71 = GPIO_DIR_INPUT,
|
||||
.gpio72 = GPIO_DIR_INPUT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set3 pch_gpio_set3_level = {
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set3 pch_gpio_set3_reset = {
|
||||
};
|
||||
|
||||
const struct pch_gpio_map mainboard_gpio_map = {
|
||||
.set1 = {
|
||||
.mode = &pch_gpio_set1_mode,
|
||||
.direction = &pch_gpio_set1_direction,
|
||||
.level = &pch_gpio_set1_level,
|
||||
.blink = &pch_gpio_set1_blink,
|
||||
.invert = &pch_gpio_set1_invert,
|
||||
.reset = &pch_gpio_set1_reset,
|
||||
},
|
||||
.set2 = {
|
||||
.mode = &pch_gpio_set2_mode,
|
||||
.direction = &pch_gpio_set2_direction,
|
||||
.level = &pch_gpio_set2_level,
|
||||
.reset = &pch_gpio_set2_reset,
|
||||
},
|
||||
.set3 = {
|
||||
.mode = &pch_gpio_set3_mode,
|
||||
.direction = &pch_gpio_set3_direction,
|
||||
.level = &pch_gpio_set3_level,
|
||||
.reset = &pch_gpio_set3_reset,
|
||||
},
|
||||
};
|
||||
|
|
@ -0,0 +1,76 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008-2009 coresystems GmbH
|
||||
* Copyright (C) 2014 Vladimir Serbinenko
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of
|
||||
* the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
0x10ec0662, /* Codec Vendor / Device ID: Realtek */
|
||||
0x103c1495, /* Subsystem ID */
|
||||
|
||||
0x0000000b, /* Number of 4 dword sets */
|
||||
/* NID 0x01: Subsystem ID. */
|
||||
AZALIA_SUBVENDOR(0x0, 0x103c1495),
|
||||
|
||||
/* NID 0x14. */
|
||||
AZALIA_PIN_CFG(0x0, 0x14, 0x01014010),
|
||||
|
||||
/* NID 0x15. */
|
||||
AZALIA_PIN_CFG(0x0, 0x15, 0x99130120),
|
||||
|
||||
/* NID 0x16. */
|
||||
AZALIA_PIN_CFG(0x0, 0x16, 0x411111f0),
|
||||
|
||||
/* NID 0x18. */
|
||||
AZALIA_PIN_CFG(0x0, 0x18, 0x01813c30),
|
||||
|
||||
/* NID 0x19. */
|
||||
AZALIA_PIN_CFG(0x0, 0x19, 0x02a11c3f),
|
||||
|
||||
/* NID 0x1a. */
|
||||
AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0),
|
||||
|
||||
/* NID 0x1b. */
|
||||
AZALIA_PIN_CFG(0x0, 0x1b, 0x0221101f),
|
||||
|
||||
/* NID 0x1c. */
|
||||
AZALIA_PIN_CFG(0x0, 0x1c, 0x411111f0),
|
||||
|
||||
/* NID 0x1d. */
|
||||
AZALIA_PIN_CFG(0x0, 0x1d, 0x40028101),
|
||||
|
||||
/* NID 0x1e. */
|
||||
AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0),
|
||||
0x80862805, /* Codec Vendor / Device ID: Intel */
|
||||
0x80861495, /* Subsystem ID */
|
||||
|
||||
0x00000004, /* Number of 4 dword sets */
|
||||
/* NID 0x01: Subsystem ID. */
|
||||
AZALIA_SUBVENDOR(0x3, 0x80861495),
|
||||
|
||||
/* NID 0x05. */
|
||||
AZALIA_PIN_CFG(0x3, 0x05, 0x58560010),
|
||||
|
||||
/* NID 0x06. */
|
||||
AZALIA_PIN_CFG(0x3, 0x06, 0x18560020),
|
||||
|
||||
/* NID 0x07. */
|
||||
AZALIA_PIN_CFG(0x3, 0x07, 0x58560030),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[0] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2014 Vladimir Serbinenko
|
||||
* Copyright (C) 2018 Patrick Rudolph <siro@das-labor.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of
|
||||
* the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
#include <device/device.h>
|
||||
#include <drivers/intel/gma/int15.h>
|
||||
#include <southbridge/intel/bd82x6x/pch.h>
|
||||
|
||||
static void mainboard_enable(struct device *dev)
|
||||
{
|
||||
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE,
|
||||
GMA_INT15_PANEL_FIT_DEFAULT,
|
||||
GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
.enable_dev = mainboard_enable,
|
||||
};
|
||||
|
|
@ -0,0 +1,84 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008-2009 coresystems GmbH
|
||||
* Copyright (C) 2014 Vladimir Serbinenko
|
||||
* Copyright (C) 2018 Patrick Rudolph <siro@das-labor.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of
|
||||
* the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <arch/byteorder.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <superio/nuvoton/npcd378/npcd378.h>
|
||||
#include <superio/nuvoton/common/nuvoton.h>
|
||||
#include "northbridge/intel/sandybridge/sandybridge.h"
|
||||
#include "northbridge/intel/sandybridge/raminit_native.h"
|
||||
#include "southbridge/intel/bd82x6x/pch.h"
|
||||
|
||||
#define SERIAL_DEV PNP_DEV(0x2e, NPCD378_SP2)
|
||||
|
||||
void pch_enable_lpc(void)
|
||||
{
|
||||
/*
|
||||
* Enable SuperIO, TPM, Keyboard, LPT, COMA
|
||||
* (COMB can be equip on expansion header)
|
||||
*/
|
||||
pci_write_config16(PCH_LPC_DEV, LPC_EN,
|
||||
CNF2_LPC_EN |CNF1_LPC_EN | KBC_LPC_EN | LPT_LPC_EN |
|
||||
COMB_LPC_EN | COMA_LPC_EN);
|
||||
|
||||
/* COMA: 3F8h, COMB: 2F8h */
|
||||
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
|
||||
}
|
||||
|
||||
void mainboard_rcba_config(void)
|
||||
{
|
||||
}
|
||||
|
||||
const struct southbridge_usb_port mainboard_usb_ports[] = {
|
||||
{ 1, 0, -1 },
|
||||
{ 1, 0, -1 },
|
||||
{ 1, 0, -1 },
|
||||
{ 1, 0, -1 },
|
||||
{ 1, 0, -1 },
|
||||
{ 1, 0, -1 },
|
||||
{ 1, 0, -1 },
|
||||
{ 1, 0, -1 },
|
||||
{ 1, 0, -1 },
|
||||
{ 1, 0, -1 },
|
||||
{ 1, 0, -1 },
|
||||
{ 1, 0, -1 },
|
||||
{ 1, 0, -1 },
|
||||
{ 1, 0, -1 },
|
||||
};
|
||||
|
||||
void mainboard_early_init(int s3resume)
|
||||
{
|
||||
}
|
||||
|
||||
void mainboard_config_superio(void)
|
||||
{
|
||||
if (IS_ENABLED(CONFIG_CONSOLE_SERIAL))
|
||||
nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
}
|
||||
|
||||
void mainboard_get_spd(spd_raw_data *spd, bool id_only)
|
||||
{
|
||||
/* BTX mainboard: Reversed mapping */
|
||||
read_spd(&spd[3], 0x50, id_only);
|
||||
read_spd(&spd[2], 0x51, id_only);
|
||||
read_spd(&spd[1], 0x52, id_only);
|
||||
read_spd(&spd[0], 0x53, id_only);
|
||||
}
|
||||
Loading…
Reference in New Issue