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mb/google/drallion: Implement touchscreen power sequencing 

For touchscreens on drallion, drive the enable GPIO high starting in
romstage while holding in reset, then disable the reset GPIO in
ramstage. This will allow coreboot to detect the presence of i2c
touchscreens during ACPI SSDT generation (implemented in a subsequent
commit).

BUG=b:121309055
TEST=tested with rest of patch train

Change-Id: I6825345f35a7415020e77edf781139f0c9b5f875
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Matt DeVillier 2022-12-21 14:17:54 -06:00 committed by Martin L Roth
parent 17a07b38a1
commit 631d77eca9
1 changed files with 10 additions and 4 deletions
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14
src/mainboard/google/drallion/variants/drallion/gpio.c
View File

@ -65,7 +65,7 @@ static const struct pad_config gpio_table[] = {
/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), /* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE),
/* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), /* HDD_FALL_INT (nostuff) */ /* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), /* HDD_FALL_INT (nostuff) */
/* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), /* GSPI1_CLK */ PAD_NC(GPP_B20, NONE),
/* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 0, DEEP), /* PCH_3.3V_TS_EN */ /* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 1, DEEP), /* PCH_3.3V_TS_EN */
/* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE), /* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE),
/* SML1ALERT# */ PAD_NC(GPP_B23, DN_20K), /* SML1ALERT# */ PAD_NC(GPP_B23, DN_20K),
@ -111,7 +111,7 @@ static const struct pad_config gpio_table[] = {
/* ISH_UART0_RXD */ PAD_CFG_NF(GPP_D13, UP_20K, DEEP, NF1), /* ISH_UART0_RXD */ PAD_CFG_NF(GPP_D13, UP_20K, DEEP, NF1),
/* ISH_CPU_UART0_TX */ /* ISH_CPU_UART0_TX */
/* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), /* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
/* ISH_UART0_RTS# */ PAD_CFG_GPO(GPP_D15, 0, DEEP), /* TS_RST */ /* ISH_UART0_RTS# */ PAD_CFG_GPO(GPP_D15, 1, DEEP), /* TS_RST */
/* ISH_UART0_CTS# */ PAD_CFG_GPI(GPP_D16, NONE, PLTRST), /* ISH_UART0_CTS# */ PAD_CFG_GPI(GPP_D16, NONE, PLTRST),
/* DMIC_CLK1 */ PAD_CFG_GPI(GPP_D17, NONE, PLTRST), /* KB_DET# */ /* DMIC_CLK1 */ PAD_CFG_GPI(GPP_D17, NONE, PLTRST), /* KB_DET# */
/* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, PLTRST, /* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, PLTRST,
@ -249,10 +249,16 @@ const struct pad_config *variant_early_gpio_table(size_t *num)
return early_gpio_table; return early_gpio_table;
} }
static const struct pad_config romstage_gpio_table[] = {
/* Enable touchscreen, hold in reset */
PAD_CFG_GPO(GPP_B21, 1, DEEP), /* PCH_3.3V_TS_EN */
PAD_CFG_GPO(GPP_D15, 0, DEEP), /* TS_RST */
};
const struct pad_config *variant_romstage_gpio_table(size_t *num) const struct pad_config *variant_romstage_gpio_table(size_t *num)
{ {
*num = 0; *num = ARRAY_SIZE(romstage_gpio_table);
return NULL; return romstage_gpio_table;
} }
static const struct cros_gpio cros_gpios[] = { static const struct cros_gpio cros_gpios[] = {