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mb/google/skyrim: Enable L1 ASPM substates for PCIe devices 

Enable both L1.1 and L1.2 substates for the WiFi, SD card reader,
and SSD (both NVMe and eMMC). If a given device does not support
a particular substate, then it will not be enabled during PCIe
enumeration by coreboot.

BUG=b:270690572

TEST=build/boot multiple skyrim/whiterun/frostflow SKUs with different
storage configs, verify WiFi/SD card/SSD all functional and have L1
substates enabled insofar as they are supported by the device.
BRANCH=skyrim

Change-Id: Ib84df8b9d97282ae696414e52c4a65cfb0a81194
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
This commit is contained in:
Matt DeVillier 2023-03-03 14:17:00 -06:00 committed by Martin L Roth
parent dcd7ec25cd
commit 6337180ba9
1 changed files with 6 additions and 0 deletions
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6
src/mainboard/google/skyrim/port_descriptors.c
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@ -20,6 +20,8 @@ static const fsp_dxio_descriptor skyrim_mdn_dxio_descriptors[] = {
.turn_off_unused_lanes = true, .turn_off_unused_lanes = true,
.link_aspm = ASPM_L1, .link_aspm = ASPM_L1,
.link_hotplug = 3, .link_hotplug = 3,
.link_aspm_L1_1 = true,
.link_aspm_L1_2 = true,
.clk_req = CLK_REQ2, .clk_req = CLK_REQ2,
}, },
{ /* SD */ { /* SD */
@ -33,6 +35,8 @@ static const fsp_dxio_descriptor skyrim_mdn_dxio_descriptors[] = {
.turn_off_unused_lanes = true, .turn_off_unused_lanes = true,
.link_aspm = ASPM_L1, .link_aspm = ASPM_L1,
.link_hotplug = 3, .link_hotplug = 3,
.link_aspm_L1_1 = true,
.link_aspm_L1_2 = true,
.gpio_group_id = GPIO_27, .gpio_group_id = GPIO_27,
.clk_req = CLK_REQ1, .clk_req = CLK_REQ1,
}, },
@ -47,6 +51,8 @@ static const fsp_dxio_descriptor skyrim_mdn_dxio_descriptors[] = {
.turn_off_unused_lanes = true, .turn_off_unused_lanes = true,
.link_aspm = ASPM_L1, .link_aspm = ASPM_L1,
.link_hotplug = 3, .link_hotplug = 3,
.link_aspm_L1_1 = true,
.link_aspm_L1_2 = true,
.gpio_group_id = GPIO_6, .gpio_group_id = GPIO_6,
.clk_req = CLK_REQ0, .clk_req = CLK_REQ0,
}, },