GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mainboard/google/reef: Set PL1 override to 12000mW 

Reef is using APL SoC SKU's with 6W TDP max. We've done
experiments and found the energy calculation is wrong with
the current VR solution. Experiments show that SoC TDP max
(6W) can be reached when RAPL PL1 is set to 12W. Therefore,
we've inserted 12W override after reading the fused value (6W)
so that the system can reach the right performance level.

BUG=chrome-os-partner:56922
TEST=webGL performance(fps) not impacted before and after S3.

Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>

Change-Id: I21c278e82b82d805f6925f4d9c82187825fd0aa0
Reviewed-on: https://review.coreboot.org/17029
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Venkateswarlu Vinjamuri 2016-10-14 15:29:33 -07:00 committed by Aaron Durbin
parent a247d8e53c
commit 63583f0987
1 changed files with 5 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
src/mainboard/google/reef/variants/baseboard/devicetree.cb
View File

@ -49,6 +49,11 @@ chip soc/intel/apollolake
# Enable DPTF # Enable DPTF
register "dptf_enable" = "1" register "dptf_enable" = "1"
# PL1 override 12000 mW: the energy calculation is wrong with the
# current VR solution. Experiments show that SoC TDP max (6W) can
# be reached when RAPL PL1 is set to 12W.
register "tdp_pl1_override_mw" = "12000"
# Enable Audio Clock and Power gating # Enable Audio Clock and Power gating
register "hdaudio_clk_gate_enable" = "1" register "hdaudio_clk_gate_enable" = "1"
register "hdaudio_pwr_gate_enable" = "1" register "hdaudio_pwr_gate_enable" = "1"