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soc/intel/{icl,jsl,tgl}: Remove SkipMpInit UPD as deprecated 

FSP default UPD for SkipMpInit is set to 0 which refers to run CPU
feature programming on all cores (BSP + APs).

Setting SkipMpInit=1 is not recommended as it will only limit CPU
feature programming on BSP.

TEST=Able to perform CPU feature programming by FSP on all cores
using external MP PPI services.

Change-Id: I22e70f5f15e53c5fabd78cc3698c4d718b607af6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
This commit is contained in:
Subrata Banik 2020-07-30 11:31:55 +05:30
parent 46f8073249
commit 6362de3829
3 changed files with 2 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/soc/intel/icelake/fsp_params.c
View File

@ -73,8 +73,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
/* Mandatory to make use of CpuMpPpi implementation from ICL onwards */ /* Mandatory to make use of CpuMpPpi implementation from ICL onwards */
params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data();
/* TODO: Remove me as SkipMpInit is getting deprecated */
params->SkipMpInit = 0;
mainboard_silicon_init_params(params); mainboard_silicon_init_params(params);

6
src/soc/intel/jasperlake/fsp_params.c
View File

@ -96,12 +96,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_dev_enabled(dev); params->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_dev_enabled(dev);
/* Use coreboot MP PPI services if Kconfig is enabled */ /* Use coreboot MP PPI services if Kconfig is enabled */
if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) { if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI))
params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data();
params->SkipMpInit = 0;
} else {
params->SkipMpInit = !CONFIG(USE_INTEL_FSP_MP_INIT);
}
/* Chipset Lockdown */ /* Chipset Lockdown */
if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) { if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) {

6
src/soc/intel/tigerlake/fsp_params.c
View File

@ -104,12 +104,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_dev_enabled(dev); params->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_dev_enabled(dev);
/* Use coreboot MP PPI services if Kconfig is enabled */ /* Use coreboot MP PPI services if Kconfig is enabled */
if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) { if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI))
params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data();
params->SkipMpInit = 0;
} else {
params->SkipMpInit = !CONFIG(USE_INTEL_FSP_MP_INIT);
}
/* D3Hot and D3Cold for TCSS */ /* D3Hot and D3Cold for TCSS */
params->D3HotEnable = !config->TcssD3HotDisable; params->D3HotEnable = !config->TcssD3HotDisable;