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mb/google/zork: Update SPI mode to 100MHz, 1-2-2 

Change SPI speed from 66MHz, mode 1-1-2 to 100MHz mode 1-2-2.

“1-2-2" means command, address and data are transmitted
through 1 wire, 2 wire and 2 wire, respectively.

BUG=b:160603142
TEST=Boot on trembyle, verify register settings.

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I14f96e3c085126c70e64ef3a3f5b7b54ce6cbffe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43306
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Martin Roth 2020-07-06 20:02:36 -06:00 committed by Patrick Georgi
parent 45b51e0180
commit 637f941f66
1 changed files with 3 additions and 3 deletions
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6
src/mainboard/google/zork/variants/baseboard/devicetree.cb
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@ -140,11 +140,11 @@ chip soc/amd/picasso
# SPI Configuration
register "common_config.spi_config" = "{
.normal_speed = SPI_SPEED_66M, /* MHz */
.fast_speed = SPI_SPEED_66M, /* MHz */
.normal_speed = SPI_SPEED_100M, /* MHz */
.fast_speed = SPI_SPEED_100M, /* MHz */
.altio_speed = SPI_SPEED_66M, /* MHz */
.tpm_speed = SPI_SPEED_66M, /* MHz */
.read_mode = SPI_READ_MODE_DUAL112,
.read_mode = SPI_READ_MODE_DUAL122,
}"
# eSPI Configuration