mb/google/zork: Update SPI mode to 100MHz, 1-2-2
Change SPI speed from 66MHz, mode 1-1-2 to 100MHz mode 1-2-2. “1-2-2" means command, address and data are transmitted through 1 wire, 2 wire and 2 wire, respectively. BUG=b:160603142 TEST=Boot on trembyle, verify register settings. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I14f96e3c085126c70e64ef3a3f5b7b54ce6cbffe Reviewed-on: https://review.coreboot.org/c/coreboot/+/43306 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -140,11 +140,11 @@ chip soc/amd/picasso
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# SPI Configuration
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register "common_config.spi_config" = "{
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.normal_speed = SPI_SPEED_66M, /* MHz */
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.fast_speed = SPI_SPEED_66M, /* MHz */
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.normal_speed = SPI_SPEED_100M, /* MHz */
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.fast_speed = SPI_SPEED_100M, /* MHz */
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.altio_speed = SPI_SPEED_66M, /* MHz */
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.tpm_speed = SPI_SPEED_66M, /* MHz */
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.read_mode = SPI_READ_MODE_DUAL112,
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.read_mode = SPI_READ_MODE_DUAL122,
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}"
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# eSPI Configuration
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