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mb/siemens/chili: Drop ineffective `SaGv` setting 

SaGv is only available on ULT/ULX processors, which use PCH-LP. Given
that the Siemens Chili board selects `SOC_INTEL_CANNONLAKE_PCH_H`, it
does not use ULT/ULX processors, and thus does not support SaGv. Drop
the `SaGv` setting from the devicetrees, as it has no effect.

Change-Id: I5be518cce08206ad149efd1665e44a7111b24202
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56205
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2021-07-12 10:53:25 +02:00 committed by Patrick Georgi
parent 06bc2c8498
commit 6386cc9973
2 changed files with 0 additions and 2 deletions
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1
src/mainboard/siemens/chili/variants/base/devicetree.cb
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@ -2,7 +2,6 @@
chip soc/intel/cannonlake
# FSP configuration
register "SaGv" = "SaGv_Enabled"
register "RMT" = "0"
register "PchHdaDspEnable" = "0"

1
src/mainboard/siemens/chili/variants/chili/devicetree.cb
View File

@ -2,7 +2,6 @@
chip soc/intel/cannonlake
# FSP configuration
register "SaGv" = "SaGv_Enabled"
register "RMT" = "0"
register "PchHdaDspEnable" = "0"