Add support for the ASRock E350M1, an AMD family 14h Fusion board.
A video option rom must be added for UMA graphics support. It can be extracted from the supplied UEFI BIOS. ASRock E350M1 support is based on the AMD persimmon project. The major differences are SIO model and DIMM SDP addressing. With this coreboot and seabios, the board can boot DOS from a SATA drive and can boot WinPE from a USB flash drive. I was unable to get Windows setup to run. The board has a socketed SPI flash BIOS chip and a serial port header. The SIO is Nuvoton NCT5572D. Using coreboot's existing Winbond w83627hf is a good enough match to get the serial port and keyboard working. Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Peter Stuge <peter@stuge.se> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6382 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Scott Duplichan
parent
199c694f49
commit
63896e75b4
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@ -23,10 +23,12 @@ choice
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config BOARD_ASROCK_939A785GMH
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config BOARD_ASROCK_939A785GMH
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bool "939A785GMH/128M"
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bool "939A785GMH/128M"
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config BOARD_ASROCK_E350M1
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bool "E350M1"
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endchoice
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endchoice
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source "src/mainboard/asrock/939a785gmh/Kconfig"
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source "src/mainboard/asrock/e350m1/Kconfig"
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config MAINBOARD_VENDOR
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config MAINBOARD_VENDOR
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string
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string
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@ -17,7 +17,7 @@
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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#
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#
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if BOARD_AMD_PERSIMMON
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if BOARD_ASROCK_E350M1
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config BOARD_SPECIFIC_OPTIONS # dummy
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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def_bool y
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@ -28,7 +28,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14_ROOT_COMPLEX
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select NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14_ROOT_COMPLEX
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select NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14
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select NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14
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select SOUTHBRIDGE_AMD_CIMX_WRAPPER_SB800
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select SOUTHBRIDGE_AMD_CIMX_WRAPPER_SB800
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select SUPERIO_FINTEK_F81865F
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select SUPERIO_WINBOND_W83627HF
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select BOARD_HAS_FADT
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select BOARD_HAS_FADT
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select HAVE_BUS_CONFIG
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select HAVE_BUS_CONFIG
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select HAVE_OPTION_TABLE
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select HAVE_OPTION_TABLE
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@ -56,7 +56,7 @@ config AMD_CIMX_SB800
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config MAINBOARD_DIR
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config MAINBOARD_DIR
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string
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string
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default amd/persimmon
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default asrock/e350m1
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config APIC_ID_OFFSET
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config APIC_ID_OFFSET
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hex
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hex
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@ -64,7 +64,7 @@ config APIC_ID_OFFSET
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config MAINBOARD_PART_NUMBER
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config MAINBOARD_PART_NUMBER
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string
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string
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default "Persimmon"
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default "E350M1"
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config HW_MEM_HOLE_SIZEK
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config HW_MEM_HOLE_SIZEK
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hex
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hex
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@ -132,16 +132,15 @@ config RAMBASE
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config SIO_PORT
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config SIO_PORT
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hex
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hex
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default 0x4e
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default 0x2e
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config ONBOARD_VGA_IS_PRIMARY
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config ONBOARD_VGA_IS_PRIMARY
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bool
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bool
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default y
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default y
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#define CONFIG_VGA_BIOS_ID "1002,9804"
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config VGA_BIOS_ID
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config VGA_BIOS_ID
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string
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string
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default "1002,9804"
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default "1002,9802"
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config DRIVERS_PS2_KEYBOARD
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config DRIVERS_PS2_KEYBOARD
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bool
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bool
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@ -151,5 +150,5 @@ config WARNINGS_ARE_ERRORS
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bool
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bool
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default n
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default n
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endif # BOARD_AMD_PERSIMMON
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endif # BOARD_ASROCK_E350M1
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@ -1,84 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
|
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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DefinitionBlock ("SSDT2.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440)
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{
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Scope (_SB)
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{
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External (DADD, MethodObj)
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External (GHCE, MethodObj)
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External (GHCN, MethodObj)
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External (GHCL, MethodObj)
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External (GHCD, MethodObj)
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External (GNUS, MethodObj)
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External (GIOR, MethodObj)
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External (GMEM, MethodObj)
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External (GWBN, MethodObj)
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External (GBUS, MethodObj)
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External (PICF)
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External (\_SB.PCI0.LNKA, DeviceObj)
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External (\_SB.PCI0.LNKB, DeviceObj)
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External (\_SB.PCI0.LNKC, DeviceObj)
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External (\_SB.PCI0.LNKD, DeviceObj)
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Device (PCIX)
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{
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// BUS ? Second HT Chain
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Name (HCIN, 0xcc) // HC2 0x01
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Name (_UID, 0xdd) // HC 0x03
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Name (_HID, "PNP0A03")
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Method (_ADR, 0, NotSerialized) //Fake bus should be 0
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{
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Return (DADD(GHCN(HCIN), 0x00000000))
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}
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Method (_BBN, 0, NotSerialized)
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{
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Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
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}
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Method (_STA, 0, NotSerialized)
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{
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Return (\_SB.GHCE(HCIN))
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}
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Method (_CRS, 0, NotSerialized)
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{
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Name (BUF0, ResourceTemplate () { })
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Store( GHCN(HCIN), Local4)
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Store( GHCL(HCIN), Local5)
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Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
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Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
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Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
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Return (Local3)
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}
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#include "acpi/pci2_hc.asl"
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}
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}
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}
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@ -1,84 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
|
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
|
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||||||
* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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DefinitionBlock ("SSDT3.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440)
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{
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Scope (_SB)
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{
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External (DADD, MethodObj)
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External (GHCE, MethodObj)
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External (GHCN, MethodObj)
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External (GHCL, MethodObj)
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External (GHCD, MethodObj)
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External (GNUS, MethodObj)
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External (GIOR, MethodObj)
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External (GMEM, MethodObj)
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External (GWBN, MethodObj)
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External (GBUS, MethodObj)
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External (PICF)
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||||||
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External (\_SB.PCI0.LNKA, DeviceObj)
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External (\_SB.PCI0.LNKB, DeviceObj)
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||||||
External (\_SB.PCI0.LNKC, DeviceObj)
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||||||
External (\_SB.PCI0.LNKD, DeviceObj)
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||||||
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Device (PCIX)
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{
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// BUS ? Second HT Chain
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Name (HCIN, 0xcc) // HC2 0x01
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||||||
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||||||
Name (_UID, 0xdd) // HC 0x03
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|
||||||
|
|
||||||
Name (_HID, "PNP0A03")
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||||||
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Method (_ADR, 0, NotSerialized) //Fake bus should be 0
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|
||||||
{
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|
||||||
Return (DADD(GHCN(HCIN), 0x00000000))
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|
||||||
}
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|
||||||
|
|
||||||
Method (_BBN, 0, NotSerialized)
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|
||||||
{
|
|
||||||
Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
|
|
||||||
}
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|
||||||
|
|
||||||
Method (_STA, 0, NotSerialized)
|
|
||||||
{
|
|
||||||
Return (\_SB.GHCE(HCIN))
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|
||||||
}
|
|
||||||
|
|
||||||
Method (_CRS, 0, NotSerialized)
|
|
||||||
{
|
|
||||||
Name (BUF0, ResourceTemplate () { })
|
|
||||||
Store( GHCN(HCIN), Local4)
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|
||||||
Store( GHCL(HCIN), Local5)
|
|
||||||
|
|
||||||
Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
|
|
||||||
Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
|
|
||||||
Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
|
|
||||||
Return (Local3)
|
|
||||||
}
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|
||||||
|
|
||||||
#include "acpi/pci3_hc.asl"
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|
||||||
}
|
|
||||||
}
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|
||||||
|
|
||||||
}
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|
||||||
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|
||||||
|
|
@ -1,84 +0,0 @@
|
||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU General Public License
|
|
||||||
* along with this program; if not, write to the Free Software
|
|
||||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
|
||||||
*/
|
|
||||||
|
|
||||||
DefinitionBlock ("SSDT4.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440)
|
|
||||||
{
|
|
||||||
Scope (_SB)
|
|
||||||
{
|
|
||||||
External (DADD, MethodObj)
|
|
||||||
External (GHCE, MethodObj)
|
|
||||||
External (GHCN, MethodObj)
|
|
||||||
External (GHCL, MethodObj)
|
|
||||||
External (GHCD, MethodObj)
|
|
||||||
External (GNUS, MethodObj)
|
|
||||||
External (GIOR, MethodObj)
|
|
||||||
External (GMEM, MethodObj)
|
|
||||||
External (GWBN, MethodObj)
|
|
||||||
External (GBUS, MethodObj)
|
|
||||||
|
|
||||||
External (PICF)
|
|
||||||
|
|
||||||
External (\_SB.PCI0.LNKA, DeviceObj)
|
|
||||||
External (\_SB.PCI0.LNKB, DeviceObj)
|
|
||||||
External (\_SB.PCI0.LNKC, DeviceObj)
|
|
||||||
External (\_SB.PCI0.LNKD, DeviceObj)
|
|
||||||
|
|
||||||
Device (PCIX)
|
|
||||||
{
|
|
||||||
|
|
||||||
// BUS ? Second HT Chain
|
|
||||||
Name (HCIN, 0xcc) // HC2 0x01
|
|
||||||
|
|
||||||
Name (_UID, 0xdd) // HC 0x03
|
|
||||||
|
|
||||||
Name (_HID, "PNP0A03")
|
|
||||||
|
|
||||||
Method (_ADR, 0, NotSerialized) //Fake bus should be 0
|
|
||||||
{
|
|
||||||
Return (DADD(GHCN(HCIN), 0x00000000))
|
|
||||||
}
|
|
||||||
|
|
||||||
Method (_BBN, 0, NotSerialized)
|
|
||||||
{
|
|
||||||
Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
|
|
||||||
}
|
|
||||||
|
|
||||||
Method (_STA, 0, NotSerialized)
|
|
||||||
{
|
|
||||||
Return (\_SB.GHCE(HCIN))
|
|
||||||
}
|
|
||||||
|
|
||||||
Method (_CRS, 0, NotSerialized)
|
|
||||||
{
|
|
||||||
Name (BUF0, ResourceTemplate () { })
|
|
||||||
Store( GHCN(HCIN), Local4)
|
|
||||||
Store( GHCL(HCIN), Local5)
|
|
||||||
|
|
||||||
Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
|
|
||||||
Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
|
|
||||||
Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
|
|
||||||
Return (Local3)
|
|
||||||
}
|
|
||||||
|
|
||||||
#include "acpi/pci4_hc.asl"
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
@ -1,85 +0,0 @@
|
||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU General Public License
|
|
||||||
* along with this program; if not, write to the Free Software
|
|
||||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
DefinitionBlock ("SSDT5.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440)
|
|
||||||
{
|
|
||||||
Scope (_SB)
|
|
||||||
{
|
|
||||||
External (DADD, MethodObj)
|
|
||||||
External (GHCE, MethodObj)
|
|
||||||
External (GHCN, MethodObj)
|
|
||||||
External (GHCL, MethodObj)
|
|
||||||
External (GHCD, MethodObj)
|
|
||||||
External (GNUS, MethodObj)
|
|
||||||
External (GIOR, MethodObj)
|
|
||||||
External (GMEM, MethodObj)
|
|
||||||
External (GWBN, MethodObj)
|
|
||||||
External (GBUS, MethodObj)
|
|
||||||
|
|
||||||
External (PICF)
|
|
||||||
|
|
||||||
External (\_SB.PCI0.LNKA, DeviceObj)
|
|
||||||
External (\_SB.PCI0.LNKB, DeviceObj)
|
|
||||||
External (\_SB.PCI0.LNKC, DeviceObj)
|
|
||||||
External (\_SB.PCI0.LNKD, DeviceObj)
|
|
||||||
|
|
||||||
Device (PCIX)
|
|
||||||
{
|
|
||||||
|
|
||||||
// BUS ? Second HT Chain
|
|
||||||
Name (HCIN, 0xcc) // HC2 0x01
|
|
||||||
|
|
||||||
Name (_UID, 0xdd) // HC 0x03
|
|
||||||
|
|
||||||
Name (_HID, "PNP0A03")
|
|
||||||
|
|
||||||
Method (_ADR, 0, NotSerialized) //Fake bus should be 0
|
|
||||||
{
|
|
||||||
Return (DADD(GHCN(HCIN), 0x00000000))
|
|
||||||
}
|
|
||||||
|
|
||||||
Method (_BBN, 0, NotSerialized)
|
|
||||||
{
|
|
||||||
Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
|
|
||||||
}
|
|
||||||
|
|
||||||
Method (_STA, 0, NotSerialized)
|
|
||||||
{
|
|
||||||
Return (\_SB.GHCE(HCIN))
|
|
||||||
}
|
|
||||||
|
|
||||||
Method (_CRS, 0, NotSerialized)
|
|
||||||
{
|
|
||||||
Name (BUF0, ResourceTemplate () { })
|
|
||||||
Store( GHCN(HCIN), Local4)
|
|
||||||
Store( GHCL(HCIN), Local5)
|
|
||||||
|
|
||||||
Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
|
|
||||||
Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
|
|
||||||
Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
|
|
||||||
Return (Local3)
|
|
||||||
}
|
|
||||||
|
|
||||||
#include "acpi/pci5_hc.asl"
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
@ -55,30 +55,46 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex
|
||||||
device pci 14.1 on end # IDE 0x439c
|
device pci 14.1 on end # IDE 0x439c
|
||||||
device pci 14.2 on end # HDA 0x4383
|
device pci 14.2 on end # HDA 0x4383
|
||||||
device pci 14.3 on # LPC 0x439d
|
device pci 14.3 on # LPC 0x439d
|
||||||
chip superio/fintek/f81865f
|
chip superio/winbond/w83627hf
|
||||||
device pnp 4e.0 off # Floppy
|
device pnp 2e.0 off # Floppy
|
||||||
io 0x60 = 0x3f0
|
io 0x60 = 0x3f0
|
||||||
irq 0x70 = 6
|
irq 0x70 = 6
|
||||||
drq 0x74 = 2
|
drq 0x74 = 2
|
||||||
end
|
end
|
||||||
device pnp 4e.3 off end # Parallel Port
|
device pnp 2e.1 off # Parallel Port
|
||||||
device pnp 4e.4 off end # Hardware Monitor
|
io 0x60 = 0x378
|
||||||
device pnp 4e.5 on # Keyboard
|
irq 0x70 = 7
|
||||||
io 0x60 = 0x60
|
|
||||||
io 0x62 = 0x64
|
|
||||||
irq 0x70 = 1
|
|
||||||
end
|
end
|
||||||
device pnp 4e.6 off end # GPIO
|
device pnp 2e.2 on # Com1
|
||||||
device pnp 4e.a off end # PME
|
|
||||||
device pnp 4e.10 on # COM1
|
|
||||||
io 0x60 = 0x3f8
|
io 0x60 = 0x3f8
|
||||||
irq 0x70 = 4
|
irq 0x70 = 4
|
||||||
end
|
end
|
||||||
device pnp 4e.11 off # COM2
|
device pnp 2e.3 off # Com2
|
||||||
io 0x60 = 0x2f8
|
io 0x60 = 0x2f8
|
||||||
irq 0x70 = 3
|
irq 0x70 = 3
|
||||||
end
|
end
|
||||||
end # f81865f
|
device pnp 2e.5 on # Keyboard
|
||||||
|
io 0x60 = 0x60
|
||||||
|
io 0x62 = 0x64
|
||||||
|
irq 0x70 = 1
|
||||||
|
irq 0x72 = 12
|
||||||
|
end
|
||||||
|
device pnp 2e.6 off # CIR
|
||||||
|
io 0x60 = 0x100
|
||||||
|
end
|
||||||
|
device pnp 2e.7 off # GAME_MIDI_GIPO1
|
||||||
|
io 0x60 = 0x220
|
||||||
|
io 0x62 = 0x300
|
||||||
|
irq 0x70 = 9
|
||||||
|
end
|
||||||
|
device pnp 2e.8 off end # GPIO2
|
||||||
|
device pnp 2e.9 off end # GPIO3
|
||||||
|
device pnp 2e.a off end # ACPI
|
||||||
|
device pnp 2e.b on # HW Monitor
|
||||||
|
io 0x60 = 0x290
|
||||||
|
irq 0x70 = 5
|
||||||
|
end
|
||||||
|
end
|
||||||
end #LPC
|
end #LPC
|
||||||
device pci 14.4 on end # PCI 0x4384
|
device pci 14.4 on end # PCI 0x4384
|
||||||
device pci 14.5 on end # USB 2
|
device pci 14.5 on end # USB 2
|
||||||
|
|
|
||||||
|
|
@ -34,8 +34,8 @@ static const UINT8 spdAddressLookup [2] [2] [4] = // socket, channel, dimm
|
||||||
{
|
{
|
||||||
// socket 0
|
// socket 0
|
||||||
{
|
{
|
||||||
{0xA0, 0xA2}, // channel 0 dimms
|
{0xA0, 0xA4}, // channel 0 dimms
|
||||||
{0xA4, 0xA8}, // channel 1 dimms
|
{0x00, 0x00}, // channel 1 dimms
|
||||||
},
|
},
|
||||||
// socket 1
|
// socket 1
|
||||||
{
|
{
|
||||||
|
|
|
||||||
|
|
@ -22,8 +22,8 @@ DefinitionBlock (
|
||||||
"DSDT.AML", /* Output filename */
|
"DSDT.AML", /* Output filename */
|
||||||
"DSDT", /* Signature */
|
"DSDT", /* Signature */
|
||||||
0x02, /* DSDT Revision, needs to be 2 for 64bit */
|
0x02, /* DSDT Revision, needs to be 2 for 64bit */
|
||||||
"AMD ", /* OEMID */
|
"ASROCK", /* OEMID */
|
||||||
"PERSIMMO", /* TABLE ID */
|
"E350M1 ", /* TABLE ID */
|
||||||
0x00010001 /* OEM Revision */
|
0x00010001 /* OEM Revision */
|
||||||
)
|
)
|
||||||
{ /* Start of ASL file */
|
{ /* Start of ASL file */
|
||||||
|
|
|
||||||
|
|
@ -49,11 +49,11 @@ void set_pcie_dereset(void)
|
||||||
uint64_t uma_memory_base, uma_memory_size;
|
uint64_t uma_memory_base, uma_memory_size;
|
||||||
|
|
||||||
/*************************************************
|
/*************************************************
|
||||||
* enable the dedicated function in persimmon board.
|
* enable the dedicated function in e350m1 board.
|
||||||
*************************************************/
|
*************************************************/
|
||||||
static void persimmon_enable(device_t dev)
|
static void e350m1_enable(device_t dev)
|
||||||
{
|
{
|
||||||
printk(BIOS_INFO, "Mainboard Persimmon Enable. dev=0x%p\n", dev);
|
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
|
||||||
#if (CONFIG_GFXUMA == 1)
|
#if (CONFIG_GFXUMA == 1)
|
||||||
msr_t msr, msr2;
|
msr_t msr, msr2;
|
||||||
uint32_t sys_mem;
|
uint32_t sys_mem;
|
||||||
|
|
@ -110,6 +110,6 @@ int add_mainboard_resources(struct lb_memory *mem)
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
struct chip_operations mainboard_ops = {
|
struct chip_operations mainboard_ops = {
|
||||||
CHIP_NAME("AMD PERSIMMON Mainboard")
|
CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard")
|
||||||
.enable_dev = persimmon_enable,
|
.enable_dev = e350m1_enable,
|
||||||
};
|
};
|
||||||
|
|
|
||||||
|
|
@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v)
|
||||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||||
|
|
||||||
mptable_init(mc, LAPIC_ADDR);
|
mptable_init(mc, LAPIC_ADDR);
|
||||||
memcpy(mc->mpc_oem, "AMD ", 8);
|
memcpy(mc->mpc_oem, "ASROCK ", 8);
|
||||||
|
|
||||||
smp_write_processors(mc);
|
smp_write_processors(mc);
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -31,7 +31,7 @@
|
||||||
#include <console/loglevel.h>
|
#include <console/loglevel.h>
|
||||||
#include "agesawrapper.h"
|
#include "agesawrapper.h"
|
||||||
#include "cpu/x86/bist.h"
|
#include "cpu/x86/bist.h"
|
||||||
#include "superio/fintek/f81865f/f81865f_early_serial.c"
|
#include "superio/winbond/w83627hf/early_serial.c"
|
||||||
#include "cpu/x86/lapic/boot_cpu.c"
|
#include "cpu/x86/lapic/boot_cpu.c"
|
||||||
#include "pc80/i8254.c"
|
#include "pc80/i8254.c"
|
||||||
#include "pc80/i8259.c"
|
#include "pc80/i8259.c"
|
||||||
|
|
@ -40,7 +40,7 @@
|
||||||
|
|
||||||
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
|
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
|
||||||
|
|
||||||
#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1)
|
#define SERIAL_DEV PNP_DEV(CONFIG_SIO_PORT, W83627HF_SP1)
|
||||||
|
|
||||||
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||||
{
|
{
|
||||||
|
|
@ -52,7 +52,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||||
sb_poweron_init();
|
sb_poweron_init();
|
||||||
|
|
||||||
post_code(0x31);
|
post_code(0x31);
|
||||||
f81865f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||||
uart_init();
|
uart_init();
|
||||||
console_init();
|
console_init();
|
||||||
}
|
}
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue