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mb/lenovo/t520: Remove superfluous comments related to PCI devices 

Since all devicetrees from lenovo/t520 are using the reference names for
PCI devices now, remove the equivalent comments documenting their
function.

Change-Id: I307dbf7a7d6fc9086e868d8315ba7a66b94a24e7
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
This commit is contained in:
Felix Singer 2024-01-13 23:05:42 +01:00 committed by Felix Singer
parent edf122a8cb
commit 63e77650d6
3 changed files with 25 additions and 25 deletions
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44
src/mainboard/lenovo/t520/devicetree.cb
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@ -18,11 +18,11 @@ chip northbridge/intel/sandybridge
device domain 0 on device domain 0 on
subsystemid 0x17aa 0x21cf inherit subsystemid 0x17aa 0x21cf inherit
device ref host_bridge on end # host bridge device ref host_bridge on end
device ref peg10 on end # NVIDIA Copcie_rporation GF119M [NVS 4200M] device ref peg10 on end # NVIDIA Copcie_rporation GF119M [NVS 4200M]
device ref igd on device ref igd on
subsystemid 0x17aa 0x21d1 subsystemid 0x17aa 0x21d1
end # vga controller end
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
# GPI routing # GPI routing
@ -50,27 +50,27 @@ chip northbridge/intel/sandybridge
register "spi_uvscc" = "0x2005" register "spi_uvscc" = "0x2005"
register "spi_lvscc" = "0x2005" register "spi_lvscc" = "0x2005"
device ref mei1 on end # Management Engine Interface 1 device ref mei1 on end
device ref mei2 off end device ref mei2 off end
device ref me_ide_r off end device ref me_ide_r off end
device ref me_kt off end device ref me_kt off end
device ref gbe on # Intel Gigabit Ethernet device ref gbe on
subsystemid 0x17aa 0x21ce subsystemid 0x17aa 0x21ce
end end
device ref ehci2 on end # USB2 EHCI #2 device ref ehci2 on end
device ref hda on end # High Definition Audio device ref hda on end
device ref pcie_rp1 off end # PCIe Port #1 device ref pcie_rp1 off end
device ref pcie_rp2 on end # PCIe Port #2 Integrated Wireless LAN device ref pcie_rp2 on end # Integrated Wireless LAN
device ref pcie_rp3 off end # PCIe Port #3 device ref pcie_rp3 off end
device ref pcie_rp4 on device ref pcie_rp4 on
smbios_slot_desc "7" "3" "ExpressCard Slot" "8" smbios_slot_desc "7" "3" "ExpressCard Slot" "8"
end # PCIe Port #4 Express Card end
device ref pcie_rp5 on end # PCIe Port #5 MMC/SDXC + IEEE1394 device ref pcie_rp5 on end # MMC/SDXC + IEEE1394
device ref pcie_rp6 off end # PCIe Port #6 Intel Ethernet PHY device ref pcie_rp6 off end # Intel Ethernet PHY
device ref pcie_rp7 off end # PCIe Port #7 device ref pcie_rp7 off end
device ref pcie_rp8 off end # PCIe Port #8 device ref pcie_rp8 off end
device ref ehci1 on end # USB2 EHCI #1 device ref ehci1 on end
device ref lpc on #LPC bridge device ref lpc on
chip ec/lenovo/pmh7 chip ec/lenovo/pmh7
device pnp ff.1 on end # dummy device pnp ff.1 on end # dummy
register "backlight_enable" = "true" register "backlight_enable" = "true"
@ -129,9 +129,9 @@ chip northbridge/intel/sandybridge
register "has_thinker1" = "1" register "has_thinker1" = "1"
end end
end # LPC bridge end
device ref sata1 on end # SATA Controller 1 device ref sata1 on end
device ref smbus on # SMBUS controller device ref smbus on
# eeprom, 8 virtual devices, same chip # eeprom, 8 virtual devices, same chip
chip drivers/i2c/at24rf08c chip drivers/i2c/at24rf08c
device i2c 54 on end device i2c 54 on end
@ -143,9 +143,9 @@ chip northbridge/intel/sandybridge
device i2c 5e on end device i2c 5e on end
device i2c 5f on end device i2c 5f on end
end end
end # SMBus end
device ref sata2 off end # IDE controller device ref sata2 off end
device ref thermal off end # Thermal controller device ref thermal off end
end end
end end
end end

4
src/mainboard/lenovo/t520/variants/t520/overridetree.cb
View File

@ -2,14 +2,14 @@ chip northbridge/intel/sandybridge
register "spd_addresses" = "{0x50, 0, 0x51, 0}" register "spd_addresses" = "{0x50, 0, 0x51, 0}"
device domain 0 on device domain 0 on
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
device ref lpc on # LPC bridge device ref lpc on
chip ec/lenovo/h8 chip ec/lenovo/h8
device pnp ff.2 on end # dummy device pnp ff.2 on end # dummy
register "has_wwan_detection" = "1" register "has_wwan_detection" = "1"
register "wwan_gpio_num" = "70" register "wwan_gpio_num" = "70"
register "wwan_gpio_lvl" = "0" register "wwan_gpio_lvl" = "0"
end end
end # LPC bridge end
end end
end end
end end

2
src/mainboard/lenovo/t520/variants/w520/overridetree.cb
View File

@ -2,7 +2,7 @@ chip northbridge/intel/sandybridge
register "spd_addresses" = "{0x50, 0x52, 0x51, 0x53}" register "spd_addresses" = "{0x50, 0x52, 0x51, 0x53}"
device domain 0 on device domain 0 on
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
device ref pcie_rp7 on end # PCIe Port #7 USB 3.0 device ref pcie_rp7 on end # USB 3.0
end end
end end
end end