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mb/google/kahlee/treeya: Update STAPM parameters for Treeya 

Change stapm percentage to 80 and time to 2000 seconds make
DUT meets Lenovo spec and pass CTS respectively.

BUG=b:147333429
TEST=build firmware and install it to DUT and run CTS relevant
     test, check temperature whether meets spec.

Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I6a2f059fbd5c89f897cfb46d1f7a82b0923edb17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38443
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Peichao Wang 2020-01-16 11:24:26 +08:00 committed by Martin Roth
parent a988091d39
commit 63fd650e2e
1 changed files with 2 additions and 2 deletions
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4
src/mainboard/google/kahlee/variants/treeya/devicetree.cb
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@ -20,8 +20,8 @@ chip soc/amd/stoneyridge
register "dram_clear_on_reset" = "DRAM_CONTENTS_KEEP" register "dram_clear_on_reset" = "DRAM_CONTENTS_KEEP"
register "uma_mode" = "UMAMODE_SPECIFIED_SIZE" register "uma_mode" = "UMAMODE_SPECIFIED_SIZE"
register "uma_size" = "16 * MiB" register "uma_size" = "16 * MiB"
register "stapm_percent" = "68" register "stapm_percent" = "80"
register "stapm_time_ms" = "900000" register "stapm_time_ms" = "2000000"
register "stapm_power_mw" = "7800" register "stapm_power_mw" = "7800"
register "lvds_poseq_varybl_to_blon" = "0x5" register "lvds_poseq_varybl_to_blon" = "0x5"
register "lvds_poseq_blon_to_varybl" = "0x5" register "lvds_poseq_blon_to_varybl" = "0x5"