GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel/baytrail: Fix 16-bit read/write PCI_COMMAND register 

Change-Id: I9b15b5458bb8140fa9bb6b0ffb6b9c78e8d8a93b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Elyes HAOUAS 2020-04-29 10:22:42 +02:00 committed by Patrick Georgi
parent f87ad9225c
commit 6468d87dde
2 changed files with 11 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/soc/intel/baytrail/smihandler.c
View File

@ -58,7 +58,7 @@ static void busmaster_disable_on_bus(int bus)
for (slot = 0; slot < 0x20; slot++) { for (slot = 0; slot < 0x20; slot++) {
for (func = 0; func < 8; func++) { for (func = 0; func < 8; func++) {
u32 reg32; u16 reg16;
pci_devfn_t dev = PCI_DEV(bus, slot, func); pci_devfn_t dev = PCI_DEV(bus, slot, func);
val = pci_read_config32(dev, PCI_VENDOR_ID); val = pci_read_config32(dev, PCI_VENDOR_ID);
@ -68,9 +68,9 @@ static void busmaster_disable_on_bus(int bus)
continue; continue;
/* Disable Bus Mastering for this one device */ /* Disable Bus Mastering for this one device */
reg32 = pci_read_config32(dev, PCI_COMMAND); reg16 = pci_read_config16(dev, PCI_COMMAND);
reg32 &= ~PCI_COMMAND_MASTER; reg16 &= ~PCI_COMMAND_MASTER;
pci_write_config32(dev, PCI_COMMAND, reg32); pci_write_config16(dev, PCI_COMMAND, reg16);
/* If this is a bridge, then follow it. */ /* If this is a bridge, then follow it. */
hdr = pci_read_config8(dev, PCI_HEADER_TYPE); hdr = pci_read_config8(dev, PCI_HEADER_TYPE);

16
src/soc/intel/baytrail/southcluster.c
View File

@ -328,9 +328,9 @@ static void hda_work_around(struct device *dev)
* that requires setting up the 64-bit BAR. */ * that requires setting up the 64-bit BAR. */
pci_write_config32(dev, PCI_BASE_ADDRESS_0, TEMP_BASE_ADDRESS); pci_write_config32(dev, PCI_BASE_ADDRESS_0, TEMP_BASE_ADDRESS);
pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0); pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0);
pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
write32(gctl, read32(gctl) | 0x1); write32(gctl, read32(gctl) | 0x1);
pci_write_config8(dev, PCI_COMMAND, 0); pci_write_config16(dev, PCI_COMMAND, 0);
pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0); pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0);
} }
@ -452,7 +452,7 @@ static int place_device_in_d3hot(struct device *dev)
/* Common PCI device function disable. */ /* Common PCI device function disable. */
void southcluster_enable_dev(struct device *dev) void southcluster_enable_dev(struct device *dev)
{ {
uint32_t reg32; uint16_t reg16;
if (!dev->enabled) { if (!dev->enabled) {
int slot = PCI_SLOT(dev->path.pci.devfn); int slot = PCI_SLOT(dev->path.pci.devfn);
@ -461,10 +461,10 @@ void southcluster_enable_dev(struct device *dev)
dev_path(dev), slot, func); dev_path(dev), slot, func);
/* Ensure memory, io, and bus master are all disabled */ /* Ensure memory, io, and bus master are all disabled */
reg32 = pci_read_config32(dev, PCI_COMMAND); reg16 = pci_read_config16(dev, PCI_COMMAND);
reg32 &= ~(PCI_COMMAND_MASTER | reg16 &= ~(PCI_COMMAND_MASTER |
PCI_COMMAND_MEMORY | PCI_COMMAND_IO); PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
pci_write_config32(dev, PCI_COMMAND, reg32); pci_write_config16(dev, PCI_COMMAND, reg16);
/* Place device in D3Hot */ /* Place device in D3Hot */
if (place_device_in_d3hot(dev) < 0) { if (place_device_in_d3hot(dev) < 0) {
@ -477,9 +477,7 @@ void southcluster_enable_dev(struct device *dev)
sc_disable_devfn(dev); sc_disable_devfn(dev);
} else { } else {
/* Enable SERR */ /* Enable SERR */
reg32 = pci_read_config32(dev, PCI_COMMAND); pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR);
reg32 |= PCI_COMMAND_SERR;
pci_write_config32(dev, PCI_COMMAND, reg32);
} }
} }