intel/kblrvp: Update mainboard configuration
Update devicetree.cb as per RVP3 mainboard. * Enable & configure PCIE ports, * Enable & configure USB ports, * Enable SSIC for WWAN, * Disable unused I2C ports, * Disable deep S5, * Disable HDA, * Update VR config, Updated gpio.h to disable pull down for SoC power button. Change-Id: I235a1d44dabef16ded2aaad13aef36ca57f37c8e Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17247 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Naresh G Solanki
Martin Roth
parent
f338fa1f31
commit
647d39f2c7
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@ -1,14 +1,14 @@
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chip soc/intel/skylake
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# Enable deep Sx states
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register "deep_s5_enable" = "1"
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register "deep_s5_enable" = "0"
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register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
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# GPE configuration
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# Note that GPE events called out in ASL code rely on this
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# route. i.e. If this route changes then the affected GPE
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# offset bits also need to be changed.
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register "gpe0_dw0" = "GPP_B"
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register "gpe0_dw0" = "GPP_C"
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register "gpe0_dw1" = "GPP_D"
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register "gpe0_dw2" = "GPP_E"
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@ -23,9 +23,6 @@ chip soc/intel/skylake
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register "dptf_enable" = "1"
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# FSP Configuration
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register "EnableAzalia" = "1"
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register "DspEnable" = "1"
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register "IoBufferOwnership" = "3"
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register "SmbusEnable" = "1"
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register "ScsEmmcEnabled" = "1"
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register "ScsEmmcHs400Enabled" = "1"
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@ -67,7 +64,7 @@ chip soc/intel/skylake
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#| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT |
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#+----------------+-------+-------+-------------+-------------+-------+
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#| Psi1Threshold | 20A | 20A | 20A | 20A | 20A |
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#| Psi2Threshold | 4A | 5A | 5A | 5A | 5A |
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#| Psi2Threshold | 5A | 5A | 5A | 5A | 5A |
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#| Psi3Threshold | 1A | 1A | 1A | 1A | 1A |
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#| Psi3Enable | 1 | 1 | 1 | 1 | 1 |
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#| Psi4Enable | 1 | 1 | 1 | 1 | 1 |
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@ -79,7 +76,7 @@ chip soc/intel/skylake
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register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
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.vr_config_enable = 1, \
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.psi1threshold = 0x50, \
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.psi2threshold = 0x10, \
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.psi2threshold = 0x14, \
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.psi3threshold = 0x4, \
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.psi3enable = 1, \
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.psi4enable = 1, \
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@ -142,29 +139,56 @@ chip soc/intel/skylake
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register "FspSkipMpInit" = "1"
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# Enable Root port 1 and 5.
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# Enable Root ports.
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# PCIE Port 1 x4 -> SLOT1
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register "PcieRpEnable[0]" = "1"
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register "PcieRpEnable[4]" = "1"
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# Enable CLKREQ#
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register "PcieRpClkReqSupport[0]" = "1"
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register "PcieRpClkReqNumber[0]" = "2"
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# PCIE Port 5 x1 -> SLOT2/LAN
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register "PcieRpEnable[4]" = "1"
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register "PcieRpClkReqSupport[4]" = "1"
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# RP 1 uses SRCCLKREQ1# while RP 5 uses SRCCLKREQ2#
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register "PcieRpClkReqNumber[0]" = "1"
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register "PcieRpClkReqNumber[4]" = "2"
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register "PcieRpClkReqNumber[4]" = "3"
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register "usb2_ports[0]" = "USB2_PORT_TYPE_C" # Type-C Port 1
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register "usb2_ports[1]" = "USB2_PORT_TYPE_C" # Type-C Port 2
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register "usb2_ports[2]" = "USB2_PORT_MID" # Bluetooth
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register "usb2_ports[4]" = "USB2_PORT_MID" # Type-A Port (card)
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register "usb2_ports[6]" = "USB2_PORT_FLEX" # Camera
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register "usb2_ports[8]" = "USB2_PORT_LONG" # Type-A Port (board)
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# PCIE Port 6 x1 -> SLOT3
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register "PcieRpEnable[5]" = "1"
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register "PcieRpClkReqSupport[5]" = "1"
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register "PcieRpClkReqNumber[5]" = "1"
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT" # Type-C Port 1
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT" # Type-C Port 2
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT" # Type-A Port (card)
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register "usb3_ports[3]" = "USB3_PORT_DEFAULT" # Type-A Port (board)
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# PCIE Port 7 Disabled
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# PCIE Port 8 Disabled
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# PCIE Port 9 x1 -> WLAN
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register "PcieRpEnable[8]" = "1"
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register "PcieRpClkReqSupport[8]" = "1"
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register "PcieRpClkReqNumber[8]" = "5"
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register "i2c[4].voltage" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
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# PCIE Port 10 x1 -> WiGig
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register "PcieRpEnable[9]" = "1"
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register "PcieRpClkReqSupport[9]" = "1"
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register "PcieRpClkReqNumber[9]" = "4"
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# USB 2.0 Enable all ports
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register "usb2_ports[0]" = "USB2_PORT_MAX" # TYPE-A Port
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register "usb2_ports[1]" = "USB2_PORT_MAX" # TYPE-A Port
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register "usb2_ports[2]" = "USB2_PORT_MAX" # Bluetooth
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register "usb2_ports[4]" = "USB2_PORT_MAX" # Type-A Port
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register "usb2_ports[5]" = "USB2_PORT_MAX" # TYPE-A Port
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register "usb2_ports[6]" = "USB2_PORT_MAX" # TYPE-A Port
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register "usb2_ports[7]" = "USB2_PORT_MAX" # TYPE-A Port
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register "usb2_ports[8]" = "USB2_PORT_MAX" # TYPE-A Port
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register "usb2_ports[9]" = "USB2_PORT_MAX" # TYPE-A Port
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register "usb2_ports[10]" = "USB2_PORT_MAX" # TYPE-A Port
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register "usb2_ports[11]" = "USB2_PORT_MAX" # TYPE-A Port
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# USB 3.0 Enable Port 1-4. Port 5 & 6 Disabled
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT" # TYPE-A Port
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT" # TYPE-A Port
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT" # TYPE-A Port
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register "usb3_ports[3]" = "USB3_PORT_DEFAULT" # TYPE-A Port
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register "usb3_ports[4]" = "USB3_PORT_EMPTY" # Disabled
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register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Disabled
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register "SsicPortEnable" = "1" # Enable SSIC for WWAN
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# Must leave UART0 enabled or SD/eMMC will not work as PCI
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register "SerialIoDevMode" = "{ \
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@ -181,18 +205,12 @@ chip soc/intel/skylake
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[PchSerialIoIndexUart2] = PchSerialIoSkipInit, \
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}"
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# PL2 override 25W
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register "tdp_pl2_override" = "25"
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# Send an extra VR mailbox command for the PS4 exit issue
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register "SendVrMbxCmd" = "2"
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# Enable/Disable VMX feature
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register "VmxEnable" = "0"
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# Use default SD card detect GPIO configuration
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register "sdcard_cd_gpio_default" = "GPP_A7"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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@ -202,23 +220,8 @@ chip soc/intel/skylake
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device pci 14.0 on end # USB xHCI
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device pci 14.1 off end # USB xDCI (OTG)
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device pci 14.2 on end # Thermal Subsystem
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device pci 15.0 on
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chip drivers/i2c/generic
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register "hid" = ""ELAN0001""
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register "desc" = ""ELAN Touchscreen""
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register "irq" = "IRQ_EDGE_LOW(GPP_E7_IRQ)"
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device i2c 10 on end
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end
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end # I2C #0
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device pci 15.1 on
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chip drivers/i2c/generic
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register "hid" = ""ELAN0000""
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register "desc" = ""ELAN Touchpad""
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register "irq" = "IRQ_EDGE_LOW(GPP_B3_IRQ)"
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register "wake" = "GPE0_DW0_05"
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device i2c 15 on end
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end
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end # I2C #1
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device pci 15.0 on end # I2C #0
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device pci 15.1 on end # I2C #1
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device pci 15.2 off end # I2C #2
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device pci 15.3 off end # I2C #3
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device pci 16.0 on end # Management Engine Interface 1
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@ -229,61 +232,14 @@ chip soc/intel/skylake
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device pci 17.0 off end # SATA
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device pci 19.0 on end # UART #2
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device pci 19.1 off end # I2C #5
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device pci 19.2 on
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chip drivers/i2c/nau8825
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register "irq" = "IRQ_LEVEL_LOW(GPP_F10_IRQ)"
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register "jkdet_enable" = "1"
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register "jkdet_pull_enable" = "1"
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register "jkdet_pull_up" = "1"
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register "jkdet_polarity" = "1" # ActiveLow
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register "vref_impedance" = "2" # 125kOhm
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register "micbias_voltage" = "6" # 2.754
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register "sar_threshold_num" = "4"
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register "sar_threshold[0]" = "0x08"
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register "sar_threshold[1]" = "0x12"
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register "sar_threshold[2]" = "0x26"
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register "sar_threshold[3]" = "0x73"
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register "sar_hysteresis" = "0"
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register "sar_voltage" = "6"
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register "sar_compare_time" = "1" # 1us
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register "sar_sampling_time" = "1" # 4us
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register "short_key_debounce" = "3" # 30ms
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register "jack_insert_debounce" = "7" # 512ms
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register "jack_eject_debounce" = "0"
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device i2c 1a on end
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end
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chip drivers/i2c/generic
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register "hid" = ""INT343B""
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register "desc" = ""SSM4567 Left Speaker Amp""
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register "uid" = "0"
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register "device_present_gpio" = "GPP_E3"
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device i2c 34 on end
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end
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chip drivers/i2c/generic
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register "hid" = ""INT343B""
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register "desc" = ""SSM4567 Right Speaker Amp""
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register "uid" = "1"
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register "device_present_gpio" = "GPP_E3"
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device i2c 35 on end
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end
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end # I2C #4
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device pci 1c.0 on
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chip drivers/intel/wifi
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register "wake" = "GPE0_DW0_16"
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device pci 00.0 on end
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end
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end # PCI Express Port 1
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device pci 1c.1 off end # PCI Express Port 2
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device pci 1c.2 off end # PCI Express Port 3
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device pci 1c.3 off end # PCI Express Port 4
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device pci 1c.4 on end # PCI Express Port 5
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device pci 1c.5 off end # PCI Express Port 6
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device pci 19.2 on end
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device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1
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device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN
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device pci 1c.5 on end # PCI Express Port 6 x1 SLOT3
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device pci 1c.6 off end # PCI Express Port 7
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device pci 1c.7 off end # PCI Express Port 8
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device pci 1d.0 off end # PCI Express Port 9
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device pci 1d.1 off end # PCI Express Port 10
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device pci 1d.2 off end # PCI Express Port 11
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device pci 1d.3 off end # PCI Express Port 12
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device pci 1d.0 on end # PCI Express Port 9 x1 WLAN
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device pci 1d.1 on end # PCI Express Port 10 x1 WIGIG
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device pci 1e.0 on end # UART #0
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device pci 1e.1 off end # UART #1
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device pci 1e.2 off end # GSPI #0
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@ -291,24 +247,10 @@ chip soc/intel/skylake
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device pci 1e.4 on end # eMMC
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device pci 1e.5 off end # SDIO
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device pci 1e.6 on end # SDCard
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device pci 1f.0 on
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chip drivers/pc80/tpm
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device pnp 0c31.0 on end
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end
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chip ec/google/chromeec
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device pnp 0c09.0 on end
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end
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end # LPC Interface
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device pci 1f.0 on end # LPC Interface
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device pci 1f.1 on end # P2SB
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device pci 1f.2 on end # Power Management Controller
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device pci 1f.3 on
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chip drivers/generic/max98357a
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register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)"
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register "device_present_gpio" = "GPP_E3"
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register "device_present_gpio_invert" = "1"
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device generic 0 on end
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end
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end # Intel HDA
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device pci 1f.3 on end # Intel HDA
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device pci 1f.4 on end # SMBus
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device pci 1f.5 on end # PCH SPI
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device pci 1f.6 off end # GbE
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@ -185,7 +185,7 @@ static const struct pad_config gpio_table[] = {
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/* PCH_BATLOW */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
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/* AC_PRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
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/* PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
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/* PCH_PWRBTN */ PAD_CFG_NF(GPD3, 20K_PD, DEEP, NF1),
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/* PCH_PWRBTN */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1),
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/* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
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/* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
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/* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
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@ -204,4 +204,4 @@ static const struct pad_config early_gpio_table[] = {
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#endif
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#endif
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#endif
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