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mb/google/rex: add dptf settings for 2+4 SOC SKU 

This patches privides settings based on 2+8 15w.

BUG=b:306543967
TEST=boot on rex with 2+4 SOC and power limit settings are overridden
correctly in variant_update_cpu_power_limits

Change-Id: I0560e44ce8e0d91bb5fb9c7cc9ffe68ab050bf00
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78688
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit is contained in:
Kane Chen 2023-10-27 12:38:22 +08:00 committed by Matt DeVillier
parent 6feb1de20a
commit 648ed149a1
1 changed files with 18 additions and 0 deletions
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18
src/mainboard/google/rex/variants/baseboard/rex/ramstage.c
View File

@ -20,6 +20,15 @@ const struct cpu_tdp_power_limits performance_efficient_limits[] = {
.pl2_max_power = 57000,
.pl4_power = 114000
},
{
.mch_id = PCI_DID_INTEL_MTL_P_ID_5,
.cpu_tdp = 15,
.pl1_min_power = 10000,
.pl1_max_power = 15000,
.pl2_min_power = 57000,
.pl2_max_power = 57000,
.pl4_power = 114000
},
};
const struct cpu_tdp_power_limits power_optimized_limits[] = {
@ -32,6 +41,15 @@ const struct cpu_tdp_power_limits power_optimized_limits[] = {
.pl2_max_power = 57000,
.pl4_power = 64000
},
{
.mch_id = PCI_DID_INTEL_MTL_P_ID_5,
.cpu_tdp = 15,
.pl1_min_power = 10000,
.pl1_max_power = 15000,
.pl2_min_power = 57000,
.pl2_max_power = 57000,
.pl4_power = 64000
},
};
void variant_devtree_update(void)