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tegra/nyan*: sdram updates 

nyan_big: Add 204MHz BCT for bringup, use 1.2V for VDD_CPU
Reviewed-on: https://chromium-review.googlesource.com/183939
(cherry picked from commit a6df76afb5342b805baca749abb8265e15748dc1)

nyan_big: Add initial 792MHz BCT
Reviewed-on: https://chromium-review.googlesource.com/183975
(cherry picked from commit 61d0122fdce6dc9479666bb0a5bc079c6389f78a)

nyan_big: use RAM_CODE[3:2] for ram code
Reviewed-on: https://chromium-review.googlesource.com/184076
(cherry picked from commit 35e5c5e473f871cdc897473a31586afbececd716)

tegra124: support tri-state Board Id
Reviewed-on: https://chromium-review.googlesource.com/183855
(cherry picked from commit 1a9d1bd73aa2cd0c36203b247976ad0d00a360e4)

nyan*: Fix SPI pinmux configuration
Reviewed-on: https://chromium-review.googlesource.com/184281
(cherry picked from commit ac4106b673c285af66d72392bd4a8522aba98489)

nyan_big: Add 4GB 204/792MHz BCTs
Reviewed-on: https://chromium-review.googlesource.com/184159
(cherry picked from commit 5ff002d09f8db0543b58962f6c0d24627fb0937e)

tegra124: Add function for obtaining DRAM size via MC regs
Reviewed-on: https://chromium-review.googlesource.com/184535
(cherry picked from commit d4580c46de649903a266a99eb11c9126ba385b48)

tegra124/nyan*: Obtain DRAM size dynamically
Reviewed-on: https://chromium-review.googlesource.com/184431
(cherry picked from commit a7db71744771decc04cf1966efba70bf4897cfa3)

tegra124: Rearrange iRAM layout to allow more space for romstage
Reviewed-on: https://chromium-review.googlesource.com/184240
(cherry picked from commit 6bdaabbc068146a4516c724b71d31bb777dabcfc)

tegra124: Fix MemoryType field name in SDRAM parameters.
Reviewed-on: https://chromium-review.googlesource.com/185113
(cherry picked from commit 9caccd1e86a8c683402fab87d9f3a49b87496e97)

nyan_big: Initialize SDRAM without BootROM.
Reviewed-on: https://chromium-review.googlesource.com/183624
(cherry picked from commit a1cbc00aa80ec1ea52e833a8e31c8e4b27160e70)

tegra124: move FB_SIZE_MB to a more appropriate location
Reviewed-on: https://chromium-review.googlesource.com/184930
(cherry picked from commit ddea486fd4410394417c4e59039d46a324918bdc)

nyan: Initialize SDRAM without BootROM.
Reviewed-on: https://chromium-review.googlesource.com/185114
(cherry picked from commit 1ff51b580b28553919f91b11b443251b048cf26b)

tegra124: Save SDRAM parameters to PMC registers for LP0
Reviewed-on: https://chromium-review.googlesource.com/182928
(cherry picked from commit 7476b4bd0ecdc312476cce871d22f57915a0bd86)

tegra124: Rewrite SDRAM parameter saving code to be more efficient
Reviewed-on: https://chromium-review.googlesource.com/184388
(cherry picked from commit 25084bd0407624e4b2ff82388c32af1198c501a6)

nyan: Slightly change the way SDRAM parameter files are set up
Reviewed-on: https://chromium-review.googlesource.com/185286
(cherry picked from commit a31887b804f23e031c395113db582cd71f3d1b6d)

Squashed 16 commits for SDRAM support on nyan and nyan_big.

Change-Id: I07419985376277083d62400dd14fe8273f6d5ca8
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6949
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
This commit is contained in:
Tom Warren 2014-01-23 13:37:50 -07:00 committed by Marc Jones
parent b3f08c61f1
commit 64982c5002
46 changed files with 3259 additions and 1502 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
src/mainboard/google/nyan/Kconfig
View File

@ -39,10 +39,6 @@ config MAINBOARD_PART_NUMBER
string string
default "Nyan" default "Nyan"
config DRAM_SIZE_MB
int
default 2048
config DRAM_DMA_START config DRAM_DMA_START
hex hex
default 0x90000000 default 0x90000000
@ -89,18 +85,4 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS
hex hex
default 1 default 1
choice
prompt "BCT sdram configuration"
default NYAN_BCT_SDRAM_792
help
The SDRAM configuration to put in the BCT.
config NYAN_BCT_SDRAM_792
bool "792 MHz"
config NYAN_BCT_SDRAM_924
bool "924 MHz"
endchoice
endif # BOARD_GOOGLE_NYAN endif # BOARD_GOOGLE_NYAN

1
src/mainboard/google/nyan/Makefile.inc
View File

@ -32,6 +32,7 @@ bootblock-y += bootblock.c
bootblock-y += pmic.c bootblock-y += pmic.c
romstage-y += romstage.c romstage-y += romstage.c
romstage-y += sdram_configs.c
romstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-$(CONFIG_CHROMEOS) += chromeos.c
ramstage-y += mainboard.c ramstage-y += mainboard.c

6
src/mainboard/google/nyan/bct/Makefile.inc
View File

@ -20,5 +20,7 @@
bct-cfg-$(CONFIG_NYAN_BCT_CFG_EMMC) += emmc.cfg bct-cfg-$(CONFIG_NYAN_BCT_CFG_EMMC) += emmc.cfg
bct-cfg-$(CONFIG_NYAN_BCT_CFG_SPI) += spi.cfg bct-cfg-$(CONFIG_NYAN_BCT_CFG_SPI) += spi.cfg
bct-cfg-y += odmdata.cfg bct-cfg-y += odmdata.cfg
bct-cfg-$(CONFIG_NYAN_BCT_SDRAM_924) += sdram-924.cfg
bct-cfg-$(CONFIG_NYAN_BCT_SDRAM_792) += sdram-792.cfg # Note when SDRAM config (sdram-*.cfg) files are changed, we have to regenerate
# the include files (sdram-*.inc) by running "./cfg2inc.sh sdram-*.cfg".
# TODO(hungte) Change cfg2inc.sh to NVIDIA's official tool in cbootimage.

34
src/mainboard/google/nyan/bct/cfg2inc.sh Executable file
View File

@ -0,0 +1,34 @@
#!/bin/sh
#
# This file is part of the coreboot project.
#
# Copyright 2014 Google Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
bct_cfg2inc() {
local in_file="$1"
local out_file="$2"
echo "{ /* generated from ${in_file}; do not edit. */" >"${out_file}"
# Note currently we can only handle DDR3 type memory, even in C
# implementation.
sed "/^#.*$/d; s/^SDRAM.0./ /; s/;$/,/;" \
"${in_file}" >> "${out_file}"
echo "}," >>"${out_file}"
}
for file in $@; do
echo "Generating $file => ${file%cfg}inc..."
bct_cfg2inc "${file}" "${file%cfg}inc"
done

346
src/mainboard/google/nyan/bct/sdram-792.cfg
View File

@ -1,346 +0,0 @@
# CFG Version 07
# Do not edit. Generated by gen_sdram_cfg V4.0.7. Command:
# gen_sdram_cfg -i ddr3_256Mx16x4_H5TC4G63AFR_RDA.par 1.262 -dram_board_cfg 10 -fly_by_time_ps 1650
# -b PM358/PM358_792MHz_emc_reg.txt -o PM358_Hynix_2GB_H5TC4G63AFR_RDA_792Mhz.cfg
# Parameter file: ddr3_256Mx16x4_H5TC4G63AFR_RDA.par, tck = 1.26 ns (792.39 MHz)
# bkv file: PM358/PM358_792MHz_emc_reg.txt
SDRAM[0].MemoryType = NvBootMemoryType_Ddr3;
SDRAM[0].PllMInputDivider = 0x00000001;
SDRAM[0].PllMFeedbackDivider = 0x00000042;
SDRAM[0].PllMStableTime = 0x0000012c;
SDRAM[0].PllMSetupControl = 0x00000000;
SDRAM[0].PllMSelectDiv2 = 0x00000000;
SDRAM[0].PllMPDLshiftPh45 = 0x00000001;
SDRAM[0].PllMPDLshiftPh90 = 0x00000001;
SDRAM[0].PllMPDLshiftPh135 = 0x00000001;
SDRAM[0].PllMKCP = 0x00000000;
SDRAM[0].PllMKVCO = 0x00000000;
SDRAM[0].EmcBctSpare0 = 0x00000000;
SDRAM[0].EmcBctSpare1 = 0x00000000;
SDRAM[0].EmcBctSpare2 = 0x00000000;
SDRAM[0].EmcBctSpare3 = 0x00000000;
SDRAM[0].EmcBctSpare4 = 0x00000000;
SDRAM[0].EmcBctSpare5 = 0x00000000;
SDRAM[0].EmcBctSpare6 = 0x00000000;
SDRAM[0].EmcBctSpare7 = 0x00000000;
SDRAM[0].EmcBctSpare8 = 0x00000000;
SDRAM[0].EmcBctSpare9 = 0x00000000;
SDRAM[0].EmcBctSpare10 = 0x00000000;
SDRAM[0].EmcBctSpare11 = 0x00000000;
SDRAM[0].EmcClockSource = 0x80000000;
SDRAM[0].EmcAutoCalInterval = 0x001fffff;
SDRAM[0].EmcAutoCalConfig = 0xa1430000;
SDRAM[0].EmcAutoCalConfig2 = 0x00000000;
SDRAM[0].EmcAutoCalConfig3 = 0x00000000;
SDRAM[0].EmcAutoCalWait = 0x00000190;
SDRAM[0].EmcAdrCfg = 0x00000000;
SDRAM[0].EmcPinProgramWait = 0x00000001;
SDRAM[0].EmcPinExtraWait = 0x00000000;
SDRAM[0].EmcTimingControlWait = 0x00000000;
SDRAM[0].EmcRc = 0x00000025;
SDRAM[0].EmcRfc = 0x000000cd;
SDRAM[0].EmcRfcSlr = 0x00000000;
SDRAM[0].EmcRas = 0x00000019;
SDRAM[0].EmcRp = 0x0000000a;
SDRAM[0].EmcR2r = 0x00000000;
SDRAM[0].EmcW2w = 0x00000000;
SDRAM[0].EmcR2w = 0x00000007;
SDRAM[0].EmcW2r = 0x0000000d;
SDRAM[0].EmcR2p = 0x00000004;
SDRAM[0].EmcW2p = 0x00000013;
SDRAM[0].EmcRdRcd = 0x0000000a;
SDRAM[0].EmcWrRcd = 0x0000000a;
SDRAM[0].EmcRrd = 0x00000003;
SDRAM[0].EmcRext = 0x00000002;
SDRAM[0].EmcWext = 0x00000000;
SDRAM[0].EmcWdv = 0x00000006;
SDRAM[0].EmcWdvMask = 0x00000006;
SDRAM[0].EmcQUse = 0x0000000b;
SDRAM[0].EmcQuseWidth = 0x00000002;
SDRAM[0].EmcIbdly = 0x00000000;
SDRAM[0].EmcEInput = 0x00000003;
SDRAM[0].EmcEInputDuration = 0x0000000c;
SDRAM[0].EmcPutermExtra = 0x00090000;
SDRAM[0].EmcPutermWidth = 0x00000004;
SDRAM[0].EmcPutermAdj = 0x00000000;
SDRAM[0].EmcCdbCntl1 = 0x00000000;
SDRAM[0].EmcCdbCntl2 = 0x00000000;
SDRAM[0].EmcCdbCntl3 = 0x00000000;
SDRAM[0].EmcQRst = 0x00000002;
SDRAM[0].EmcQSafe = 0x00000011;
SDRAM[0].EmcRdv = 0x00000017;
SDRAM[0].EmcRdvMask = 0x00000019;
SDRAM[0].EmcQpop = 0x0000000f;
SDRAM[0].EmcCtt = 0x00000000;
SDRAM[0].EmcCttDuration = 0x00000004;
SDRAM[0].EmcRefresh = 0x000017eb;
SDRAM[0].EmcBurstRefreshNum = 0x00000000;
SDRAM[0].EmcPreRefreshReqCnt = 0x000005fa;
SDRAM[0].EmcPdEx2Wr = 0x00000003;
SDRAM[0].EmcPdEx2Rd = 0x00000003;
SDRAM[0].EmcPChg2Pden = 0x00000001;
SDRAM[0].EmcAct2Pden = 0x00000000;
SDRAM[0].EmcAr2Pden = 0x000000c7;
SDRAM[0].EmcRw2Pden = 0x00000018;
SDRAM[0].EmcTxsr = 0x000000d7;
SDRAM[0].EmcTxsrDll = 0x00000200;
SDRAM[0].EmcTcke = 0x00000005;
SDRAM[0].EmcTckesr = 0x00000006;
SDRAM[0].EmcTpd = 0x00000005;
SDRAM[0].EmcTfaw = 0x0000001d;
SDRAM[0].EmcTrpab = 0x00000000;
SDRAM[0].EmcTClkStable = 0x00000008;
SDRAM[0].EmcTClkStop = 0x00000008;
SDRAM[0].EmcTRefBw = 0x0000182c;
SDRAM[0].EmcFbioCfg5 = 0x104ab898;
SDRAM[0].EmcFbioCfg6 = 0x00000002;
SDRAM[0].EmcFbioSpare = 0x00000000;
SDRAM[0].EmcCfgRsv = 0xff00ff00;
SDRAM[0].EmcMrs = 0x80001d71;
SDRAM[0].EmcEmrs = 0x80100002;
SDRAM[0].EmcEmrs2 = 0x80200018;
SDRAM[0].EmcEmrs3 = 0x80300000;
SDRAM[0].EmcMrw1 = 0x00000000;
SDRAM[0].EmcMrw2 = 0x00000000;
SDRAM[0].EmcMrw3 = 0x00000000;
SDRAM[0].EmcMrw4 = 0x00000000;
SDRAM[0].EmcMrwExtra = 0x00000000;
SDRAM[0].EmcWarmBootMrwExtra = 0x00000000;
SDRAM[0].EmcWarmBootExtraModeRegWriteEnable = 0x00000000;
SDRAM[0].EmcExtraModeRegWriteEnable = 0x00000000;
SDRAM[0].EmcMrwResetCommand = 0x00000000;
SDRAM[0].EmcMrwResetNInitWait = 0x00000000;
SDRAM[0].EmcMrsWaitCnt = 0x00f7000e;
SDRAM[0].EmcMrsWaitCnt2 = 0x00f7000e;
SDRAM[0].EmcCfg = 0x73300000;
SDRAM[0].EmcCfg2 = 0x0000089d;
SDRAM[0].EmcCfgPipe = 0x000040a0;
SDRAM[0].EmcDbg = 0x01000c00;
SDRAM[0].EmcCmdQ = 0x10004408;
SDRAM[0].EmcMc2EmcQ = 0x06000404;
SDRAM[0].EmcDynSelfRefControl = 0x80003025;
SDRAM[0].AhbArbitrationXbarCtrlMemInitDone = 0x00000001;
SDRAM[0].EmcCfgDigDll = 0xe00701b1;
SDRAM[0].EmcCfgDigDllPeriod = 0x00008000;
SDRAM[0].EmcDevSelect = 0x00000002;
SDRAM[0].EmcSelDpdCtrl = 0x00040000;
SDRAM[0].EmcDllXformDqs0 = 0x00000008;
SDRAM[0].EmcDllXformDqs1 = 0x00000008;
SDRAM[0].EmcDllXformDqs2 = 0x00000008;
SDRAM[0].EmcDllXformDqs3 = 0x00000008;
SDRAM[0].EmcDllXformDqs4 = 0x00000008;
SDRAM[0].EmcDllXformDqs5 = 0x00000008;
SDRAM[0].EmcDllXformDqs6 = 0x00000008;
SDRAM[0].EmcDllXformDqs7 = 0x00000008;
SDRAM[0].EmcDllXformDqs8 = 0x00000008;
SDRAM[0].EmcDllXformDqs9 = 0x00000008;
SDRAM[0].EmcDllXformDqs10 = 0x00000008;
SDRAM[0].EmcDllXformDqs11 = 0x00000008;
SDRAM[0].EmcDllXformDqs12 = 0x00000008;
SDRAM[0].EmcDllXformDqs13 = 0x00000008;
SDRAM[0].EmcDllXformDqs14 = 0x00000008;
SDRAM[0].EmcDllXformDqs15 = 0x00000008;
SDRAM[0].EmcDllXformQUse0 = 0x00000000;
SDRAM[0].EmcDllXformQUse1 = 0x00000000;
SDRAM[0].EmcDllXformQUse2 = 0x00000000;
SDRAM[0].EmcDllXformQUse3 = 0x00000000;
SDRAM[0].EmcDllXformQUse4 = 0x00000000;
SDRAM[0].EmcDllXformQUse5 = 0x00000000;
SDRAM[0].EmcDllXformQUse6 = 0x00000000;
SDRAM[0].EmcDllXformQUse7 = 0x00000000;
SDRAM[0].EmcDllXformAddr0 = 0x0000000e;
SDRAM[0].EmcDllXformAddr1 = 0x0000000e;
SDRAM[0].EmcDllXformAddr2 = 0x00000000;
SDRAM[0].EmcDllXformAddr3 = 0x0000000e;
SDRAM[0].EmcDllXformAddr4 = 0x00000000;
SDRAM[0].EmcDllXformAddr5 = 0x00000000;
SDRAM[0].EmcDllXformQUse8 = 0x00000000;
SDRAM[0].EmcDllXformQUse9 = 0x00000000;
SDRAM[0].EmcDllXformQUse10 = 0x00000000;
SDRAM[0].EmcDllXformQUse11 = 0x00000000;
SDRAM[0].EmcDllXformQUse12 = 0x00000000;
SDRAM[0].EmcDllXformQUse13 = 0x00000000;
SDRAM[0].EmcDllXformQUse14 = 0x00000000;
SDRAM[0].EmcDllXformQUse15 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs0 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs1 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs2 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs3 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs4 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs5 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs6 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs7 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs8 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs9 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs10 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs11 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs12 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs13 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs14 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs15 = 0x00000000;
SDRAM[0].EmcDllXformDq0 = 0x0000000b;
SDRAM[0].EmcDllXformDq1 = 0x0000000b;
SDRAM[0].EmcDllXformDq2 = 0x0000000b;
SDRAM[0].EmcDllXformDq3 = 0x0000000b;
SDRAM[0].EmcDllXformDq4 = 0x0000000b;
SDRAM[0].EmcDllXformDq5 = 0x0000000b;
SDRAM[0].EmcDllXformDq6 = 0x0000000b;
SDRAM[0].EmcDllXformDq7 = 0x0000000b;
SDRAM[0].WarmBootWait = 0x00000002;
SDRAM[0].EmcCttTermCtrl = 0x00000802;
SDRAM[0].EmcOdtWrite = 0x00000000;
SDRAM[0].EmcOdtRead = 0x00000000;
SDRAM[0].EmcZcalInterval = 0x00020000;
SDRAM[0].EmcZcalWaitCnt = 0x00000042;
SDRAM[0].EmcZcalMrwCmd = 0x80000000;
SDRAM[0].EmcMrsResetDll = 0x00000000;
SDRAM[0].EmcZcalInitDev0 = 0x80000011;
SDRAM[0].EmcZcalInitDev1 = 0x00000000;
SDRAM[0].EmcZcalInitWait = 0x00000001;
SDRAM[0].EmcZcalWarmColdBootEnables = 0x00000003;
SDRAM[0].EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab;
SDRAM[0].EmcZqCalDdr3WarmBoot = 0x00000000;
SDRAM[0].EmcZcalWarmBootWait = 0x00000001;
SDRAM[0].EmcMrsWarmBootEnable = 0x00000001;
SDRAM[0].EmcMrsResetDllWait = 0x00000000;
SDRAM[0].EmcMrsExtra = 0x80001d71;
SDRAM[0].EmcWarmBootMrsExtra = 0x80100002;
SDRAM[0].EmcEmrsDdr2DllEnable = 0x00000000;
SDRAM[0].EmcMrsDdr2DllReset = 0x00000000;
SDRAM[0].EmcEmrsDdr2OcdCalib = 0x00000000;
SDRAM[0].EmcDdr2Wait = 0x00000000;
SDRAM[0].EmcClkenOverride = 0x00000000;
SDRAM[0].McDisExtraSnapLevels = 0x00000000;
SDRAM[0].EmcExtraRefreshNum = 0x00000002;
SDRAM[0].EmcClkenOverrideAllWarmBoot = 0x00000000;
SDRAM[0].McClkenOverrideAllWarmBoot = 0x00000000;
SDRAM[0].EmcCfgDigDllPeriodWarmBoot = 0x00000003;
SDRAM[0].PmcVddpSel = 0x00000002;
SDRAM[0].PmcVddpSelWait = 0x00000002;
SDRAM[0].PmcDdrPwr = 0x00000003;
SDRAM[0].PmcDdrCfg = 0x00002002;
SDRAM[0].PmcIoDpd3Req = 0x4fff2f97;
SDRAM[0].PmcIoDpd3ReqWait = 0x00000000;
SDRAM[0].PmcRegShort = 0x00000000;
SDRAM[0].PmcNoIoPower = 0x00000000;
SDRAM[0].PmcPorDpdCtrlWait = 0x00000000;
SDRAM[0].EmcXm2CmdPadCtrl = 0x100002a0;
SDRAM[0].EmcXm2CmdPadCtrl2 = 0x770c0000;
SDRAM[0].EmcXm2CmdPadCtrl3 = 0x050c0000;
SDRAM[0].EmcXm2CmdPadCtrl4 = 0x00000000;
SDRAM[0].EmcXm2CmdPadCtrl5 = 0x00111111;
SDRAM[0].EmcXm2DqsPadCtrl = 0x770c1414;
SDRAM[0].EmcXm2DqsPadCtrl2 = 0x0020013d;
SDRAM[0].EmcXm2DqsPadCtrl3 = 0x61861820;
SDRAM[0].EmcXm2DqsPadCtrl4 = 0x00514514;
SDRAM[0].EmcXm2DqsPadCtrl5 = 0x00514514;
SDRAM[0].EmcXm2DqsPadCtrl6 = 0x61861800;
SDRAM[0].EmcXm2DqPadCtrl = 0x770c2990;
SDRAM[0].EmcXm2DqPadCtrl2 = 0x00000000;
SDRAM[0].EmcXm2DqPadCtrl3 = 0x00000000;
SDRAM[0].EmcXm2ClkPadCtrl = 0x77ffc085;
SDRAM[0].EmcXm2ClkPadCtrl2 = 0x00000707;
SDRAM[0].EmcXm2CompPadCtrl = 0x81f1f108;
SDRAM[0].EmcXm2VttGenPadCtrl = 0x07070004;
SDRAM[0].EmcXm2VttGenPadCtrl2 = 0x00000000;
SDRAM[0].EmcXm2VttGenPadCtrl3 = 0x017fffff;
SDRAM[0].EmcAcpdControl = 0x00000000;
SDRAM[0].EmcSwizzleRank0ByteCfg = 0x00003120;
SDRAM[0].EmcSwizzleRank0Byte0 = 0x25143067;
SDRAM[0].EmcSwizzleRank0Byte1 = 0x45367102;
SDRAM[0].EmcSwizzleRank0Byte2 = 0x47106253;
SDRAM[0].EmcSwizzleRank0Byte3 = 0x04362175;
SDRAM[0].EmcSwizzleRank1ByteCfg = 0x00003120;
SDRAM[0].EmcSwizzleRank1Byte0 = 0x71546032;
SDRAM[0].EmcSwizzleRank1Byte1 = 0x35104276;
SDRAM[0].EmcSwizzleRank1Byte2 = 0x27043615;
SDRAM[0].EmcSwizzleRank1Byte3 = 0x72306145;
SDRAM[0].EmcDsrVttgenDrv = 0x0505003f;
SDRAM[0].EmcTxdsrvttgen = 0x00000000;
SDRAM[0].EmcBgbiasCtl0 = 0x00000000;
SDRAM[0].McEmemAdrCfg = 0x00000000;
SDRAM[0].McEmemAdrCfgDev0 = 0x00080303;
SDRAM[0].McEmemAdrCfgDev1 = 0x00080303;
SDRAM[0].McEmemAdrCfgBankMask0 = 0x00001248;
SDRAM[0].McEmemAdrCfgBankMask1 = 0x00002490;
SDRAM[0].McEmemAdrCfgBankMask2 = 0x00000920;
SDRAM[0].McEmemAdrCfgBankSwizzle3 = 0x00000001;
SDRAM[0].McEmemCfg = 0x00000800;
SDRAM[0].McEmemArbCfg = 0x0e00000b;
SDRAM[0].McEmemArbOutstandingReq = 0x80000040;
SDRAM[0].McEmemArbTimingRcd = 0x00000004;
SDRAM[0].McEmemArbTimingRp = 0x00000005;
SDRAM[0].McEmemArbTimingRc = 0x00000013;
SDRAM[0].McEmemArbTimingRas = 0x0000000c;
SDRAM[0].McEmemArbTimingFaw = 0x0000000f;
SDRAM[0].McEmemArbTimingRrd = 0x00000002;
SDRAM[0].McEmemArbTimingRap2Pre = 0x00000003;
SDRAM[0].McEmemArbTimingWap2Pre = 0x0000000c;
SDRAM[0].McEmemArbTimingR2R = 0x00000002;
SDRAM[0].McEmemArbTimingW2W = 0x00000002;
SDRAM[0].McEmemArbTimingR2W = 0x00000005;
SDRAM[0].McEmemArbTimingW2R = 0x00000008;
SDRAM[0].McEmemArbDaTurns = 0x08050202;
SDRAM[0].McEmemArbDaCovers = 0x00170e13;
SDRAM[0].McEmemArbMisc0 = 0x736c2414;
SDRAM[0].McEmemArbMisc1 = 0x70000f02;
SDRAM[0].McEmemArbRing1Throttle = 0x001f0000;
SDRAM[0].McEmemArbOverride = 0x10000000;
SDRAM[0].McEmemArbOverride1 = 0x00000000;
SDRAM[0].McEmemArbRsv = 0xff00ff00;
SDRAM[0].McClkenOverride = 0x00000000;
SDRAM[0].McStatControl = 0x00000000;
SDRAM[0].McDisplaySnapRing = 0x00000003;
SDRAM[0].McVideoProtectBom = 0xfff00000;
SDRAM[0].McVideoProtectBomAdrHi = 0x00000000;
SDRAM[0].McVideoProtectSizeMb = 0x00000000;
SDRAM[0].McVideoProtectVprOverride = 0xe4bac743;
SDRAM[0].McVideoProtectVprOverride1 = 0x00000013;
SDRAM[0].McVideoProtectGpuOverride0 = 0x00000000;
SDRAM[0].McVideoProtectGpuOverride1 = 0x00000000;
SDRAM[0].McSecCarveoutBom = 0xfff00000;
SDRAM[0].McSecCarveoutAdrHi = 0x00000000;
SDRAM[0].McSecCarveoutSizeMb = 0x00000000;
SDRAM[0].McVideoProtectWriteAccess = 0x00000000;
SDRAM[0].McSecCarveoutProtectWriteAccess = 0x00000000;
SDRAM[0].EmcCaTrainingEnable = 0x00000000;
SDRAM[0].EmcCaTrainingTimingCntl1 = 0x1f7df7df;
SDRAM[0].EmcCaTrainingTimingCntl2 = 0x0000001f;
SDRAM[0].SwizzleRankByteEncode = 0x0000006f;
SDRAM[0].BootRomPatchControl = 0x00000000;
SDRAM[0].BootRomPatchData = 0x00000000;
SDRAM[0].McMtsCarveoutBom = 0xfff00000;
SDRAM[0].McMtsCarveoutAdrHi = 0x00000000;
SDRAM[0].McMtsCarveoutSizeMb = 0x00000000;
SDRAM[0].McMtsCarveoutRegCtrl = 0x00000000;
#@ MC_MLL_MPCORER_PTSA_RATE {0x7001944c} = 0x00000013;
#@ MC_PTSA_GRANT_DECREMENT {0x70019960} = 0x0000017c;
#@ MC_LATENCY_ALLOWANCE_XUSB_0 {0x7001937c} = 0x00810038;
#@ MC_LATENCY_ALLOWANCE_XUSB_1 {0x70019380} = 0x00810038;
#@ MC_LATENCY_ALLOWANCE_TSEC_0 {0x70019390} = 0x0081003c;
#@ MC_LATENCY_ALLOWANCE_SDMMCA_0 {0x700193b8} = 0x00810090;
#@ MC_LATENCY_ALLOWANCE_SDMMCAA_0 {0x700193bc} = 0x00810041;
#@ MC_LATENCY_ALLOWANCE_SDMMC_0 {0x700193c0} = 0x00810090;
#@ MC_LATENCY_ALLOWANCE_SDMMCAB_0 {0x700193c4} = 0x00810041;
#@ MC_LATENCY_ALLOWANCE_PPCS_0 {0x70019344} = 0x00270049;
#@ MC_LATENCY_ALLOWANCE_PPCS_1 {0x70019348} = 0x00810080;
#@ MC_LATENCY_ALLOWANCE_MPCORE_0 {0x70019320} = 0x00810004;
#@ MC_LATENCY_ALLOWANCE_MPCORELP_0 {0x70019324} = 0x00810004;
#@ MC_LATENCY_ALLOWANCE_HC_0 {0x70019310} = 0x00080016;
#@ MC_LATENCY_ALLOWANCE_HC_1 {0x70019314} = 0x00000081;
#@ MC_LATENCY_ALLOWANCE_AVPC_0 {0x700192e4} = 0x00810004;
#@ MC_LATENCY_ALLOWANCE_GPU_0 {0x700193ac} = 0x00810019;
#@ MC_LATENCY_ALLOWANCE_MSENC_0 {0x70019328} = 0x00810018;
#@ MC_LATENCY_ALLOWANCE_HDA_0 {0x70019318} = 0x00810024;
#@ MC_LATENCY_ALLOWANCE_VIC_0 {0x70019394} = 0x0081001c;
#@ MC_LATENCY_ALLOWANCE_VI2_0 {0x70019398} = 0x00000081;
#@ MC_LATENCY_ALLOWANCE_ISP2_0 {0x70019370} = 0x00000036;
#@ MC_LATENCY_ALLOWANCE_ISP2_1 {0x70019374} = 0x00810081;
#@ MC_LATENCY_ALLOWANCE_ISP2B_0 {0x70019384} = 0x00000036;
#@ MC_LATENCY_ALLOWANCE_ISP2B_1 {0x70019388} = 0x00810081;
#@ MC_LATENCY_ALLOWANCE_VDE_0 {0x70019354} = 0x00d400ff;
#@ MC_LATENCY_ALLOWANCE_VDE_1 {0x70019358} = 0x00510029;
#@ MC_LATENCY_ALLOWANCE_VDE_2 {0x7001935c} = 0x00810081;
#@ MC_LATENCY_ALLOWANCE_VDE_3 {0x70019360} = 0x00810081;
#@ MC_LATENCY_ALLOWANCE_SATA_0 {0x70019350} = 0x00810065;
#@ MC_LATENCY_ALLOWANCE_AFI_0 {0x700192e0} = 0x0081001c;

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src/mainboard/google/nyan/bct/sdram-924.cfg
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@ -1,346 +0,0 @@
# CFG Version 11
# Do not edit. Generated by gen_sdram_cfg V5.0.1. Command:
# gen_sdram_cfg -i ddr3_256Mx16x4_H5TC4G63AFR_RDA.par 1.082 -dram_board_cfg 10 -fly_by_time_ps 1650
# -b PM358/PM358_924MHz_emc_reg.txt -o PM358_Hynix_2GB_H5TC4G63AFR_RDA_924Mhz.cfg
# Parameter file: ddr3_256Mx16x4_H5TC4G63AFR_RDA.par, tck = 1.08 ns (924.21 MHz)
# bkv file: PM358/PM358_924MHz_emc_reg.txt
SDRAM[0].MemoryType = NvBootMemoryType_Ddr3;
SDRAM[0].PllMInputDivider = 0x00000001;
SDRAM[0].PllMFeedbackDivider = 0x0000004d;
SDRAM[0].PllMStableTime = 0x0000012c;
SDRAM[0].PllMSetupControl = 0x00000000;
SDRAM[0].PllMSelectDiv2 = 0x00000000;
SDRAM[0].PllMPDLshiftPh45 = 0x00000001;
SDRAM[0].PllMPDLshiftPh90 = 0x00000001;
SDRAM[0].PllMPDLshiftPh135 = 0x00000001;
SDRAM[0].PllMKCP = 0x00000000;
SDRAM[0].PllMKVCO = 0x00000000;
SDRAM[0].EmcBctSpare0 = 0x00000000;
SDRAM[0].EmcBctSpare1 = 0x00000000;
SDRAM[0].EmcBctSpare2 = 0x00000000;
SDRAM[0].EmcBctSpare3 = 0x00000000;
SDRAM[0].EmcBctSpare4 = 0x00000000;
SDRAM[0].EmcBctSpare5 = 0x00000000;
SDRAM[0].EmcBctSpare6 = 0x00000000;
SDRAM[0].EmcBctSpare7 = 0x00000000;
SDRAM[0].EmcBctSpare8 = 0x00000000;
SDRAM[0].EmcBctSpare9 = 0x00000000;
SDRAM[0].EmcBctSpare10 = 0x00000000;
SDRAM[0].EmcBctSpare11 = 0x00000000;
SDRAM[0].EmcClockSource = 0x80000000;
SDRAM[0].EmcAutoCalInterval = 0x001fffff;
SDRAM[0].EmcAutoCalConfig = 0xa1430404;
SDRAM[0].EmcAutoCalConfig2 = 0x00000000;
SDRAM[0].EmcAutoCalConfig3 = 0x00000000;
SDRAM[0].EmcAutoCalWait = 0x00000190;
SDRAM[0].EmcAdrCfg = 0x00000000;
SDRAM[0].EmcPinProgramWait = 0x00000001;
SDRAM[0].EmcPinExtraWait = 0x00000000;
SDRAM[0].EmcTimingControlWait = 0x00000000;
SDRAM[0].EmcRc = 0x0000002b;
SDRAM[0].EmcRfc = 0x000000ef;
SDRAM[0].EmcRfcSlr = 0x00000000;
SDRAM[0].EmcRas = 0x0000001e;
SDRAM[0].EmcRp = 0x0000000b;
SDRAM[0].EmcR2r = 0x00000000;
SDRAM[0].EmcW2w = 0x00000000;
SDRAM[0].EmcR2w = 0x00000008;
SDRAM[0].EmcW2r = 0x0000000f;
SDRAM[0].EmcR2p = 0x00000005;
SDRAM[0].EmcW2p = 0x00000016;
SDRAM[0].EmcRdRcd = 0x0000000b;
SDRAM[0].EmcWrRcd = 0x0000000b;
SDRAM[0].EmcRrd = 0x00000004;
SDRAM[0].EmcRext = 0x00000002;
SDRAM[0].EmcWext = 0x00000000;
SDRAM[0].EmcWdv = 0x00000006;
SDRAM[0].EmcWdvMask = 0x00000006;
SDRAM[0].EmcQUse = 0x0000000c;
SDRAM[0].EmcQuseWidth = 0x00000002;
SDRAM[0].EmcIbdly = 0x00000000;
SDRAM[0].EmcEInput = 0x00000002;
SDRAM[0].EmcEInputDuration = 0x0000000e;
SDRAM[0].EmcPutermExtra = 0x000a0000;
SDRAM[0].EmcPutermWidth = 0x00000004;
SDRAM[0].EmcPutermAdj = 0x00000000;
SDRAM[0].EmcCdbCntl1 = 0x00000000;
SDRAM[0].EmcCdbCntl2 = 0x00000000;
SDRAM[0].EmcCdbCntl3 = 0x00000000;
SDRAM[0].EmcQRst = 0x00000001;
SDRAM[0].EmcQSafe = 0x00000015;
SDRAM[0].EmcRdv = 0x0000001b;
SDRAM[0].EmcRdvMask = 0x0000001d;
SDRAM[0].EmcQpop = 0x00000010;
SDRAM[0].EmcCtt = 0x00000000;
SDRAM[0].EmcCttDuration = 0x00000004;
SDRAM[0].EmcRefresh = 0x00001be9;
SDRAM[0].EmcBurstRefreshNum = 0x00000000;
SDRAM[0].EmcPreRefreshReqCnt = 0x000006fa;
SDRAM[0].EmcPdEx2Wr = 0x00000004;
SDRAM[0].EmcPdEx2Rd = 0x00000015;
SDRAM[0].EmcPChg2Pden = 0x00000001;
SDRAM[0].EmcAct2Pden = 0x00000000;
SDRAM[0].EmcAr2Pden = 0x000000e6;
SDRAM[0].EmcRw2Pden = 0x0000001b;
SDRAM[0].EmcTxsr = 0x000000fa;
SDRAM[0].EmcTxsrDll = 0x00000200;
SDRAM[0].EmcTcke = 0x00000006;
SDRAM[0].EmcTckesr = 0x00000007;
SDRAM[0].EmcTpd = 0x00000006;
SDRAM[0].EmcTfaw = 0x00000022;
SDRAM[0].EmcTrpab = 0x00000000;
SDRAM[0].EmcTClkStable = 0x0000000a;
SDRAM[0].EmcTClkStop = 0x0000000a;
SDRAM[0].EmcTRefBw = 0x00001c29;
SDRAM[0].EmcFbioCfg5 = 0x104ab898;
SDRAM[0].EmcFbioCfg6 = 0x00000002;
SDRAM[0].EmcFbioSpare = 0x00000000;
SDRAM[0].EmcCfgRsv = 0xff00ff00;
SDRAM[0].EmcMrs = 0x80000f15;
SDRAM[0].EmcEmrs = 0x80100002;
SDRAM[0].EmcEmrs2 = 0x80200020;
SDRAM[0].EmcEmrs3 = 0x80300000;
SDRAM[0].EmcMrw1 = 0x00000000;
SDRAM[0].EmcMrw2 = 0x00000000;
SDRAM[0].EmcMrw3 = 0x00000000;
SDRAM[0].EmcMrw4 = 0x00000000;
SDRAM[0].EmcMrwExtra = 0x00000000;
SDRAM[0].EmcWarmBootMrwExtra = 0x00000000;
SDRAM[0].EmcWarmBootExtraModeRegWriteEnable = 0x00000000;
SDRAM[0].EmcExtraModeRegWriteEnable = 0x00000000;
SDRAM[0].EmcMrwResetCommand = 0x00000000;
SDRAM[0].EmcMrwResetNInitWait = 0x00000000;
SDRAM[0].EmcMrsWaitCnt = 0x00ce000e;
SDRAM[0].EmcMrsWaitCnt2 = 0x00ce000e;
SDRAM[0].EmcCfg = 0x73300000;
SDRAM[0].EmcCfg2 = 0x000008a5;
SDRAM[0].EmcCfgPipe = 0x00000000;
SDRAM[0].EmcDbg = 0x01000c00;
SDRAM[0].EmcCmdQ = 0x10004408;
SDRAM[0].EmcMc2EmcQ = 0x06000404;
SDRAM[0].EmcDynSelfRefControl = 0x800037ed;
SDRAM[0].AhbArbitrationXbarCtrlMemInitDone = 0x00000001;
SDRAM[0].EmcCfgDigDll = 0xe00401b1;
SDRAM[0].EmcCfgDigDllPeriod = 0x00008000;
SDRAM[0].EmcDevSelect = 0x00000002;
SDRAM[0].EmcSelDpdCtrl = 0x00040000;
SDRAM[0].EmcDllXformDqs0 = 0x00000005;
SDRAM[0].EmcDllXformDqs1 = 0x00000005;
SDRAM[0].EmcDllXformDqs2 = 0x00000005;
SDRAM[0].EmcDllXformDqs3 = 0x00000005;
SDRAM[0].EmcDllXformDqs4 = 0x00000005;
SDRAM[0].EmcDllXformDqs5 = 0x00000005;
SDRAM[0].EmcDllXformDqs6 = 0x00000005;
SDRAM[0].EmcDllXformDqs7 = 0x00000005;
SDRAM[0].EmcDllXformDqs8 = 0x00000005;
SDRAM[0].EmcDllXformDqs9 = 0x00000005;
SDRAM[0].EmcDllXformDqs10 = 0x00000005;
SDRAM[0].EmcDllXformDqs11 = 0x00000005;
SDRAM[0].EmcDllXformDqs12 = 0x00000005;
SDRAM[0].EmcDllXformDqs13 = 0x00000005;
SDRAM[0].EmcDllXformDqs14 = 0x00000005;
SDRAM[0].EmcDllXformDqs15 = 0x00000005;
SDRAM[0].EmcDllXformQUse0 = 0x00000000;
SDRAM[0].EmcDllXformQUse1 = 0x00000000;
SDRAM[0].EmcDllXformQUse2 = 0x00000000;
SDRAM[0].EmcDllXformQUse3 = 0x00000000;
SDRAM[0].EmcDllXformQUse4 = 0x00000000;
SDRAM[0].EmcDllXformQUse5 = 0x00000000;
SDRAM[0].EmcDllXformQUse6 = 0x00000000;
SDRAM[0].EmcDllXformQUse7 = 0x00000000;
SDRAM[0].EmcDllXformAddr0 = 0x0000400e;
SDRAM[0].EmcDllXformAddr1 = 0x0000400e;
SDRAM[0].EmcDllXformAddr2 = 0x00000000;
SDRAM[0].EmcDllXformAddr3 = 0x0000400e;
SDRAM[0].EmcDllXformAddr4 = 0x0000400e;
SDRAM[0].EmcDllXformAddr5 = 0x00000000;
SDRAM[0].EmcDllXformQUse8 = 0x00000000;
SDRAM[0].EmcDllXformQUse9 = 0x00000000;
SDRAM[0].EmcDllXformQUse10 = 0x00000000;
SDRAM[0].EmcDllXformQUse11 = 0x00000000;
SDRAM[0].EmcDllXformQUse12 = 0x00000000;
SDRAM[0].EmcDllXformQUse13 = 0x00000000;
SDRAM[0].EmcDllXformQUse14 = 0x00000000;
SDRAM[0].EmcDllXformQUse15 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs0 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs1 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs2 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs3 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs4 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs5 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs6 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs7 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs8 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs9 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs10 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs11 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs12 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs13 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs14 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs15 = 0x00000000;
SDRAM[0].EmcDllXformDq0 = 0x00000006;
SDRAM[0].EmcDllXformDq1 = 0x00000006;
SDRAM[0].EmcDllXformDq2 = 0x00000006;
SDRAM[0].EmcDllXformDq3 = 0x00000006;
SDRAM[0].EmcDllXformDq4 = 0x00000006;
SDRAM[0].EmcDllXformDq5 = 0x00000006;
SDRAM[0].EmcDllXformDq6 = 0x00000006;
SDRAM[0].EmcDllXformDq7 = 0x00000006;
SDRAM[0].WarmBootWait = 0x00000002;
SDRAM[0].EmcCttTermCtrl = 0x00000802;
SDRAM[0].EmcOdtWrite = 0x00000000;
SDRAM[0].EmcOdtRead = 0x00000000;
SDRAM[0].EmcZcalInterval = 0x00020000;
SDRAM[0].EmcZcalWaitCnt = 0x0000004c;
SDRAM[0].EmcZcalMrwCmd = 0x80000000;
SDRAM[0].EmcMrsResetDll = 0x00000000;
SDRAM[0].EmcZcalInitDev0 = 0x80000011;
SDRAM[0].EmcZcalInitDev1 = 0x00000000;
SDRAM[0].EmcZcalInitWait = 0x00000001;
SDRAM[0].EmcZcalWarmColdBootEnables = 0x00000003;
SDRAM[0].EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab;
SDRAM[0].EmcZqCalDdr3WarmBoot = 0x00000000;
SDRAM[0].EmcZcalWarmBootWait = 0x00000001;
SDRAM[0].EmcMrsWarmBootEnable = 0x00000001;
SDRAM[0].EmcMrsResetDllWait = 0x00000000;
SDRAM[0].EmcMrsExtra = 0x80000f15;
SDRAM[0].EmcWarmBootMrsExtra = 0x80100002;
SDRAM[0].EmcEmrsDdr2DllEnable = 0x00000000;
SDRAM[0].EmcMrsDdr2DllReset = 0x00000000;
SDRAM[0].EmcEmrsDdr2OcdCalib = 0x00000000;
SDRAM[0].EmcDdr2Wait = 0x00000000;
SDRAM[0].EmcClkenOverride = 0x00000000;
SDRAM[0].McDisExtraSnapLevels = 0x00000000;
SDRAM[0].EmcExtraRefreshNum = 0x00000002;
SDRAM[0].EmcClkenOverrideAllWarmBoot = 0x00000000;
SDRAM[0].McClkenOverrideAllWarmBoot = 0x00000000;
SDRAM[0].EmcCfgDigDllPeriodWarmBoot = 0x00000003;
SDRAM[0].PmcVddpSel = 0x00000002;
SDRAM[0].PmcVddpSelWait = 0x00000002;
SDRAM[0].PmcDdrPwr = 0x00000003;
SDRAM[0].PmcDdrCfg = 0x00002002;
SDRAM[0].PmcIoDpd3Req = 0x4fff2f97;
SDRAM[0].PmcIoDpd3ReqWait = 0x00000000;
SDRAM[0].PmcRegShort = 0x00000000;
SDRAM[0].PmcNoIoPower = 0x00000000;
SDRAM[0].PmcPorDpdCtrlWait = 0x00000000;
SDRAM[0].EmcXm2CmdPadCtrl = 0x100002a0;
SDRAM[0].EmcXm2CmdPadCtrl2 = 0x770c0000;
SDRAM[0].EmcXm2CmdPadCtrl3 = 0x050c0000;
SDRAM[0].EmcXm2CmdPadCtrl4 = 0x00000000;
SDRAM[0].EmcXm2CmdPadCtrl5 = 0x00111111;
SDRAM[0].EmcXm2DqsPadCtrl = 0x770c1414;
SDRAM[0].EmcXm2DqsPadCtrl2 = 0x0020013d;
SDRAM[0].EmcXm2DqsPadCtrl3 = 0x55555520;
SDRAM[0].EmcXm2DqsPadCtrl4 = 0x003cf3cf;
SDRAM[0].EmcXm2DqsPadCtrl5 = 0x003cf3cf;
SDRAM[0].EmcXm2DqsPadCtrl6 = 0x55555500;
SDRAM[0].EmcXm2DqPadCtrl = 0x770c2990;
SDRAM[0].EmcXm2DqPadCtrl2 = 0x00000000;
SDRAM[0].EmcXm2DqPadCtrl3 = 0x00000000;
SDRAM[0].EmcXm2ClkPadCtrl = 0x77ffc085;
SDRAM[0].EmcXm2ClkPadCtrl2 = 0x00000303;
SDRAM[0].EmcXm2CompPadCtrl = 0x81f1f108;
SDRAM[0].EmcXm2VttGenPadCtrl = 0x07070004;
SDRAM[0].EmcXm2VttGenPadCtrl2 = 0x00000000;
SDRAM[0].EmcXm2VttGenPadCtrl3 = 0x016eeeee;
SDRAM[0].EmcAcpdControl = 0x00000000;
SDRAM[0].EmcSwizzleRank0ByteCfg = 0x00003120;
SDRAM[0].EmcSwizzleRank0Byte0 = 0x25143067;
SDRAM[0].EmcSwizzleRank0Byte1 = 0x45367102;
SDRAM[0].EmcSwizzleRank0Byte2 = 0x47106253;
SDRAM[0].EmcSwizzleRank0Byte3 = 0x04362175;
SDRAM[0].EmcSwizzleRank1ByteCfg = 0x00003120;
SDRAM[0].EmcSwizzleRank1Byte0 = 0x71546032;
SDRAM[0].EmcSwizzleRank1Byte1 = 0x35104276;
SDRAM[0].EmcSwizzleRank1Byte2 = 0x27043615;
SDRAM[0].EmcSwizzleRank1Byte3 = 0x72306145;
SDRAM[0].EmcDsrVttgenDrv = 0x0606003f;
SDRAM[0].EmcTxdsrvttgen = 0x00000000;
SDRAM[0].EmcBgbiasCtl0 = 0x00000000;
SDRAM[0].McEmemAdrCfg = 0x00000000;
SDRAM[0].McEmemAdrCfgDev0 = 0x00080303;
SDRAM[0].McEmemAdrCfgDev1 = 0x00080303;
SDRAM[0].McEmemAdrCfgBankMask0 = 0x00001248;
SDRAM[0].McEmemAdrCfgBankMask1 = 0x00002490;
SDRAM[0].McEmemAdrCfgBankMask2 = 0x00000920;
SDRAM[0].McEmemAdrCfgBankSwizzle3 = 0x00000001;
SDRAM[0].McEmemCfg = 0x00000800;
SDRAM[0].McEmemArbCfg = 0x0e00000d;
SDRAM[0].McEmemArbOutstandingReq = 0x80000040;
SDRAM[0].McEmemArbTimingRcd = 0x00000005;
SDRAM[0].McEmemArbTimingRp = 0x00000006;
SDRAM[0].McEmemArbTimingRc = 0x00000016;
SDRAM[0].McEmemArbTimingRas = 0x0000000e;
SDRAM[0].McEmemArbTimingFaw = 0x00000011;
SDRAM[0].McEmemArbTimingRrd = 0x00000002;
SDRAM[0].McEmemArbTimingRap2Pre = 0x00000004;
SDRAM[0].McEmemArbTimingWap2Pre = 0x0000000e;
SDRAM[0].McEmemArbTimingR2R = 0x00000002;
SDRAM[0].McEmemArbTimingW2W = 0x00000002;
SDRAM[0].McEmemArbTimingR2W = 0x00000006;
SDRAM[0].McEmemArbTimingW2R = 0x00000009;
SDRAM[0].McEmemArbDaTurns = 0x09060202;
SDRAM[0].McEmemArbDaCovers = 0x001a1016;
SDRAM[0].McEmemArbMisc0 = 0x734e2a17;
SDRAM[0].McEmemArbMisc1 = 0x70000f02;
SDRAM[0].McEmemArbRing1Throttle = 0x001f0000;
SDRAM[0].McEmemArbOverride = 0x10000000;
SDRAM[0].McEmemArbOverride1 = 0x00000000;
SDRAM[0].McEmemArbRsv = 0xff00ff00;
SDRAM[0].McClkenOverride = 0x00000000;
SDRAM[0].McStatControl = 0x00000000;
SDRAM[0].McDisplaySnapRing = 0x00000003;
SDRAM[0].McVideoProtectBom = 0xfff00000;
SDRAM[0].McVideoProtectBomAdrHi = 0x00000000;
SDRAM[0].McVideoProtectSizeMb = 0x00000000;
SDRAM[0].McVideoProtectVprOverride = 0xe4bac743;
SDRAM[0].McVideoProtectVprOverride1 = 0x00000013;
SDRAM[0].McVideoProtectGpuOverride0 = 0x00000000;
SDRAM[0].McVideoProtectGpuOverride1 = 0x00000000;
SDRAM[0].McSecCarveoutBom = 0xfff00000;
SDRAM[0].McSecCarveoutAdrHi = 0x00000000;
SDRAM[0].McSecCarveoutSizeMb = 0x00000000;
SDRAM[0].McVideoProtectWriteAccess = 0x00000000;
SDRAM[0].McSecCarveoutProtectWriteAccess = 0x00000000;
SDRAM[0].EmcCaTrainingEnable = 0x00000000;
SDRAM[0].EmcCaTrainingTimingCntl1 = 0x1f7df7df;
SDRAM[0].EmcCaTrainingTimingCntl2 = 0x0000001f;
SDRAM[0].SwizzleRankByteEncode = 0x0000006f;
SDRAM[0].BootRomPatchControl = 0x00000000;
SDRAM[0].BootRomPatchData = 0x00000000;
SDRAM[0].McMtsCarveoutBom = 0xfff00000;
SDRAM[0].McMtsCarveoutAdrHi = 0x00000000;
SDRAM[0].McMtsCarveoutSizeMb = 0x00000000;
SDRAM[0].McMtsCarveoutRegCtrl = 0x00000000;
#@ MC_MLL_MPCORER_PTSA_RATE {0x7001944c} = 0x00000017;
#@ MC_PTSA_GRANT_DECREMENT {0x70019960} = 0x000001bb;
#@ MC_LATENCY_ALLOWANCE_XUSB_0 {0x7001937c} = 0x006e0038;
#@ MC_LATENCY_ALLOWANCE_XUSB_1 {0x70019380} = 0x006e0038;
#@ MC_LATENCY_ALLOWANCE_TSEC_0 {0x70019390} = 0x006e003c;
#@ MC_LATENCY_ALLOWANCE_SDMMCA_0 {0x700193b8} = 0x006e0090;
#@ MC_LATENCY_ALLOWANCE_SDMMCAA_0 {0x700193bc} = 0x006e0041;
#@ MC_LATENCY_ALLOWANCE_SDMMC_0 {0x700193c0} = 0x006e0090;
#@ MC_LATENCY_ALLOWANCE_SDMMCAB_0 {0x700193c4} = 0x006e0041;
#@ MC_LATENCY_ALLOWANCE_PPCS_0 {0x70019344} = 0x00270049;
#@ MC_LATENCY_ALLOWANCE_PPCS_1 {0x70019348} = 0x006e0080;
#@ MC_LATENCY_ALLOWANCE_MPCORE_0 {0x70019320} = 0x006e0004;
#@ MC_LATENCY_ALLOWANCE_MPCORELP_0 {0x70019324} = 0x006e0004;
#@ MC_LATENCY_ALLOWANCE_HC_0 {0x70019310} = 0x00080016;
#@ MC_LATENCY_ALLOWANCE_HC_1 {0x70019314} = 0x0000006e;
#@ MC_LATENCY_ALLOWANCE_AVPC_0 {0x700192e4} = 0x006e0004;
#@ MC_LATENCY_ALLOWANCE_GPU_0 {0x700193ac} = 0x006e0019;
#@ MC_LATENCY_ALLOWANCE_MSENC_0 {0x70019328} = 0x006e0018;
#@ MC_LATENCY_ALLOWANCE_HDA_0 {0x70019318} = 0x006e0024;
#@ MC_LATENCY_ALLOWANCE_VIC_0 {0x70019394} = 0x006e001b;
#@ MC_LATENCY_ALLOWANCE_VI2_0 {0x70019398} = 0x0000006e;
#@ MC_LATENCY_ALLOWANCE_ISP2_0 {0x70019370} = 0x00000036;
#@ MC_LATENCY_ALLOWANCE_ISP2_1 {0x70019374} = 0x006e006e;
#@ MC_LATENCY_ALLOWANCE_ISP2B_0 {0x70019384} = 0x00000036;
#@ MC_LATENCY_ALLOWANCE_ISP2B_1 {0x70019388} = 0x006e006e;
#@ MC_LATENCY_ALLOWANCE_VDE_0 {0x70019354} = 0x00d400ff;
#@ MC_LATENCY_ALLOWANCE_VDE_1 {0x70019358} = 0x00510029;
#@ MC_LATENCY_ALLOWANCE_VDE_2 {0x7001935c} = 0x006e006e;
#@ MC_LATENCY_ALLOWANCE_VDE_3 {0x70019360} = 0x006e006e;
#@ MC_LATENCY_ALLOWANCE_SATA_0 {0x70019350} = 0x006e0065;
#@ MC_LATENCY_ALLOWANCE_AFI_0 {0x700192e0} = 0x006e001c;

311
src/mainboard/google/nyan/bct/sdram-hynix-2GB-792.inc Normal file
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{ /* generated from sdram-0001-792-2GB.cfg; do not edit. */
.MemoryType = NvBootMemoryType_Ddr3,
.PllMInputDivider = 0x00000001,
.PllMFeedbackDivider = 0x00000042,
.PllMStableTime = 0x0000012c,
.PllMSetupControl = 0x00000000,
.PllMSelectDiv2 = 0x00000000,
.PllMPDLshiftPh45 = 0x00000001,
.PllMPDLshiftPh90 = 0x00000001,
.PllMPDLshiftPh135 = 0x00000001,
.PllMKCP = 0x00000000,
.PllMKVCO = 0x00000000,
.EmcBctSpare0 = 0x00000000,
.EmcBctSpare1 = 0x00000000,
.EmcBctSpare2 = 0x00000000,
.EmcBctSpare3 = 0x00000000,
.EmcBctSpare4 = 0x00000000,
.EmcBctSpare5 = 0x00000000,
.EmcBctSpare6 = 0x00000000,
.EmcBctSpare7 = 0x00000000,
.EmcBctSpare8 = 0x00000000,
.EmcBctSpare9 = 0x00000000,
.EmcBctSpare10 = 0x00000000,
.EmcBctSpare11 = 0x00000000,
.EmcClockSource = 0x80000000,
.EmcAutoCalInterval = 0x001fffff,
.EmcAutoCalConfig = 0xa1430000,
.EmcAutoCalConfig2 = 0x00000000,
.EmcAutoCalConfig3 = 0x00000000,
.EmcAutoCalWait = 0x00000190,
.EmcAdrCfg = 0x00000000,
.EmcPinProgramWait = 0x00000001,
.EmcPinExtraWait = 0x00000000,
.EmcTimingControlWait = 0x00000000,
.EmcRc = 0x00000025,
.EmcRfc = 0x000000cd,
.EmcRfcSlr = 0x00000000,
.EmcRas = 0x00000019,
.EmcRp = 0x0000000a,
.EmcR2r = 0x00000000,
.EmcW2w = 0x00000000,
.EmcR2w = 0x00000007,
.EmcW2r = 0x0000000d,
.EmcR2p = 0x00000004,
.EmcW2p = 0x00000013,
.EmcRdRcd = 0x0000000a,
.EmcWrRcd = 0x0000000a,
.EmcRrd = 0x00000003,
.EmcRext = 0x00000002,
.EmcWext = 0x00000000,
.EmcWdv = 0x00000006,
.EmcWdvMask = 0x00000006,
.EmcQUse = 0x0000000b,
.EmcQuseWidth = 0x00000002,
.EmcIbdly = 0x00000000,
.EmcEInput = 0x00000003,
.EmcEInputDuration = 0x0000000c,
.EmcPutermExtra = 0x00090000,
.EmcPutermWidth = 0x00000004,
.EmcPutermAdj = 0x00000000,
.EmcCdbCntl1 = 0x00000000,
.EmcCdbCntl2 = 0x00000000,
.EmcCdbCntl3 = 0x00000000,
.EmcQRst = 0x00000002,
.EmcQSafe = 0x00000011,
.EmcRdv = 0x00000017,
.EmcRdvMask = 0x00000019,
.EmcQpop = 0x0000000f,
.EmcCtt = 0x00000000,
.EmcCttDuration = 0x00000004,
.EmcRefresh = 0x000017eb,
.EmcBurstRefreshNum = 0x00000000,
.EmcPreRefreshReqCnt = 0x000005fa,
.EmcPdEx2Wr = 0x00000003,
.EmcPdEx2Rd = 0x00000003,
.EmcPChg2Pden = 0x00000001,
.EmcAct2Pden = 0x00000000,
.EmcAr2Pden = 0x000000c7,
.EmcRw2Pden = 0x00000018,
.EmcTxsr = 0x000000d7,
.EmcTxsrDll = 0x00000200,
.EmcTcke = 0x00000005,
.EmcTckesr = 0x00000006,
.EmcTpd = 0x00000005,
.EmcTfaw = 0x0000001d,
.EmcTrpab = 0x00000000,
.EmcTClkStable = 0x00000008,
.EmcTClkStop = 0x00000008,
.EmcTRefBw = 0x0000182c,
.EmcFbioCfg5 = 0x104ab898,
.EmcFbioCfg6 = 0x00000002,
.EmcFbioSpare = 0x00000000,
.EmcCfgRsv = 0xff00ff00,
.EmcMrs = 0x80001d71,
.EmcEmrs = 0x80100002,
.EmcEmrs2 = 0x80200018,
.EmcEmrs3 = 0x80300000,
.EmcMrw1 = 0x00000000,
.EmcMrw2 = 0x00000000,
.EmcMrw3 = 0x00000000,
.EmcMrw4 = 0x00000000,
.EmcMrwExtra = 0x00000000,
.EmcWarmBootMrwExtra = 0x00000000,
.EmcWarmBootExtraModeRegWriteEnable = 0x00000000,
.EmcExtraModeRegWriteEnable = 0x00000000,
.EmcMrwResetCommand = 0x00000000,
.EmcMrwResetNInitWait = 0x00000000,
.EmcMrsWaitCnt = 0x00f7000e,
.EmcMrsWaitCnt2 = 0x00f7000e,
.EmcCfg = 0x73300000,
.EmcCfg2 = 0x0000089d,
.EmcCfgPipe = 0x000040a0,
.EmcDbg = 0x01000c00,
.EmcCmdQ = 0x10004408,
.EmcMc2EmcQ = 0x06000404,
.EmcDynSelfRefControl = 0x80003025,
.AhbArbitrationXbarCtrlMemInitDone = 0x00000001,
.EmcCfgDigDll = 0xe00701b1,
.EmcCfgDigDllPeriod = 0x00008000,
.EmcDevSelect = 0x00000002,
.EmcSelDpdCtrl = 0x00040000,
.EmcDllXformDqs0 = 0x00000008,
.EmcDllXformDqs1 = 0x00000008,
.EmcDllXformDqs2 = 0x00000008,
.EmcDllXformDqs3 = 0x00000008,
.EmcDllXformDqs4 = 0x00000008,
.EmcDllXformDqs5 = 0x00000008,
.EmcDllXformDqs6 = 0x00000008,
.EmcDllXformDqs7 = 0x00000008,
.EmcDllXformDqs8 = 0x00000008,
.EmcDllXformDqs9 = 0x00000008,
.EmcDllXformDqs10 = 0x00000008,
.EmcDllXformDqs11 = 0x00000008,
.EmcDllXformDqs12 = 0x00000008,
.EmcDllXformDqs13 = 0x00000008,
.EmcDllXformDqs14 = 0x00000008,
.EmcDllXformDqs15 = 0x00000008,
.EmcDllXformQUse0 = 0x00000000,
.EmcDllXformQUse1 = 0x00000000,
.EmcDllXformQUse2 = 0x00000000,
.EmcDllXformQUse3 = 0x00000000,
.EmcDllXformQUse4 = 0x00000000,
.EmcDllXformQUse5 = 0x00000000,
.EmcDllXformQUse6 = 0x00000000,
.EmcDllXformQUse7 = 0x00000000,
.EmcDllXformAddr0 = 0x0000000e,
.EmcDllXformAddr1 = 0x0000000e,
.EmcDllXformAddr2 = 0x00000000,
.EmcDllXformAddr3 = 0x0000000e,
.EmcDllXformAddr4 = 0x00000000,
.EmcDllXformAddr5 = 0x00000000,
.EmcDllXformQUse8 = 0x00000000,
.EmcDllXformQUse9 = 0x00000000,
.EmcDllXformQUse10 = 0x00000000,
.EmcDllXformQUse11 = 0x00000000,
.EmcDllXformQUse12 = 0x00000000,
.EmcDllXformQUse13 = 0x00000000,
.EmcDllXformQUse14 = 0x00000000,
.EmcDllXformQUse15 = 0x00000000,
.EmcDliTrimTxDqs0 = 0x00000000,
.EmcDliTrimTxDqs1 = 0x00000000,
.EmcDliTrimTxDqs2 = 0x00000000,
.EmcDliTrimTxDqs3 = 0x00000000,
.EmcDliTrimTxDqs4 = 0x00000000,
.EmcDliTrimTxDqs5 = 0x00000000,
.EmcDliTrimTxDqs6 = 0x00000000,
.EmcDliTrimTxDqs7 = 0x00000000,
.EmcDliTrimTxDqs8 = 0x00000000,
.EmcDliTrimTxDqs9 = 0x00000000,
.EmcDliTrimTxDqs10 = 0x00000000,
.EmcDliTrimTxDqs11 = 0x00000000,
.EmcDliTrimTxDqs12 = 0x00000000,
.EmcDliTrimTxDqs13 = 0x00000000,
.EmcDliTrimTxDqs14 = 0x00000000,
.EmcDliTrimTxDqs15 = 0x00000000,
.EmcDllXformDq0 = 0x0000000b,
.EmcDllXformDq1 = 0x0000000b,
.EmcDllXformDq2 = 0x0000000b,
.EmcDllXformDq3 = 0x0000000b,
.EmcDllXformDq4 = 0x0000000b,
.EmcDllXformDq5 = 0x0000000b,
.EmcDllXformDq6 = 0x0000000b,
.EmcDllXformDq7 = 0x0000000b,
.WarmBootWait = 0x00000002,
.EmcCttTermCtrl = 0x00000802,
.EmcOdtWrite = 0x00000000,
.EmcOdtRead = 0x00000000,
.EmcZcalInterval = 0x00020000,
.EmcZcalWaitCnt = 0x00000042,
.EmcZcalMrwCmd = 0x80000000,
.EmcMrsResetDll = 0x00000000,
.EmcZcalInitDev0 = 0x80000011,
.EmcZcalInitDev1 = 0x00000000,
.EmcZcalInitWait = 0x00000001,
.EmcZcalWarmColdBootEnables = 0x00000003,
.EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab,
.EmcZqCalDdr3WarmBoot = 0x00000000,
.EmcZcalWarmBootWait = 0x00000001,
.EmcMrsWarmBootEnable = 0x00000001,
.EmcMrsResetDllWait = 0x00000000,
.EmcMrsExtra = 0x80001d71,
.EmcWarmBootMrsExtra = 0x80100002,
.EmcEmrsDdr2DllEnable = 0x00000000,
.EmcMrsDdr2DllReset = 0x00000000,
.EmcEmrsDdr2OcdCalib = 0x00000000,
.EmcDdr2Wait = 0x00000000,
.EmcClkenOverride = 0x00000000,
.McDisExtraSnapLevels = 0x00000000,
.EmcExtraRefreshNum = 0x00000002,
.EmcClkenOverrideAllWarmBoot = 0x00000000,
.McClkenOverrideAllWarmBoot = 0x00000000,
.EmcCfgDigDllPeriodWarmBoot = 0x00000003,
.PmcVddpSel = 0x00000002,
.PmcVddpSelWait = 0x00000002,
.PmcDdrPwr = 0x00000003,
.PmcDdrCfg = 0x00002002,
.PmcIoDpd3Req = 0x4fff2f97,
.PmcIoDpd3ReqWait = 0x00000000,
.PmcRegShort = 0x00000000,
.PmcNoIoPower = 0x00000000,
.PmcPorDpdCtrlWait = 0x00000000,
.EmcXm2CmdPadCtrl = 0x100002a0,
.EmcXm2CmdPadCtrl2 = 0x770c0000,
.EmcXm2CmdPadCtrl3 = 0x050c0000,
.EmcXm2CmdPadCtrl4 = 0x00000000,
.EmcXm2CmdPadCtrl5 = 0x00111111,
.EmcXm2DqsPadCtrl = 0x770c1414,
.EmcXm2DqsPadCtrl2 = 0x0020013d,
.EmcXm2DqsPadCtrl3 = 0x61861820,
.EmcXm2DqsPadCtrl4 = 0x00514514,
.EmcXm2DqsPadCtrl5 = 0x00514514,
.EmcXm2DqsPadCtrl6 = 0x61861800,
.EmcXm2DqPadCtrl = 0x770c2990,
.EmcXm2DqPadCtrl2 = 0x00000000,
.EmcXm2DqPadCtrl3 = 0x00000000,
.EmcXm2ClkPadCtrl = 0x77ffc085,
.EmcXm2ClkPadCtrl2 = 0x00000707,
.EmcXm2CompPadCtrl = 0x81f1f108,
.EmcXm2VttGenPadCtrl = 0x07070004,
.EmcXm2VttGenPadCtrl2 = 0x00000000,
.EmcXm2VttGenPadCtrl3 = 0x017fffff,
.EmcAcpdControl = 0x00000000,
.EmcSwizzleRank0ByteCfg = 0x00003120,
.EmcSwizzleRank0Byte0 = 0x25143067,
.EmcSwizzleRank0Byte1 = 0x45367102,
.EmcSwizzleRank0Byte2 = 0x47106253,
.EmcSwizzleRank0Byte3 = 0x04362175,
.EmcSwizzleRank1ByteCfg = 0x00003120,
.EmcSwizzleRank1Byte0 = 0x71546032,
.EmcSwizzleRank1Byte1 = 0x35104276,
.EmcSwizzleRank1Byte2 = 0x27043615,
.EmcSwizzleRank1Byte3 = 0x72306145,
.EmcDsrVttgenDrv = 0x0505003f,
.EmcTxdsrvttgen = 0x00000000,
.EmcBgbiasCtl0 = 0x00000000,
.McEmemAdrCfg = 0x00000000,
.McEmemAdrCfgDev0 = 0x00080303,
.McEmemAdrCfgDev1 = 0x00080303,
.McEmemAdrCfgBankMask0 = 0x00001248,
.McEmemAdrCfgBankMask1 = 0x00002490,
.McEmemAdrCfgBankMask2 = 0x00000920,
.McEmemAdrCfgBankSwizzle3 = 0x00000001,
.McEmemCfg = 0x00000800,
.McEmemArbCfg = 0x0e00000b,
.McEmemArbOutstandingReq = 0x80000040,
.McEmemArbTimingRcd = 0x00000004,
.McEmemArbTimingRp = 0x00000005,
.McEmemArbTimingRc = 0x00000013,
.McEmemArbTimingRas = 0x0000000c,
.McEmemArbTimingFaw = 0x0000000f,
.McEmemArbTimingRrd = 0x00000002,
.McEmemArbTimingRap2Pre = 0x00000003,
.McEmemArbTimingWap2Pre = 0x0000000c,
.McEmemArbTimingR2R = 0x00000002,
.McEmemArbTimingW2W = 0x00000002,
.McEmemArbTimingR2W = 0x00000005,
.McEmemArbTimingW2R = 0x00000008,
.McEmemArbDaTurns = 0x08050202,
.McEmemArbDaCovers = 0x00170e13,
.McEmemArbMisc0 = 0x736c2414,
.McEmemArbMisc1 = 0x70000f02,
.McEmemArbRing1Throttle = 0x001f0000,
.McEmemArbOverride = 0x10000000,
.McEmemArbOverride1 = 0x00000000,
.McEmemArbRsv = 0xff00ff00,
.McClkenOverride = 0x00000000,
.McStatControl = 0x00000000,
.McDisplaySnapRing = 0x00000003,
.McVideoProtectBom = 0xfff00000,
.McVideoProtectBomAdrHi = 0x00000000,
.McVideoProtectSizeMb = 0x00000000,
.McVideoProtectVprOverride = 0xe4bac743,
.McVideoProtectVprOverride1 = 0x00000013,
.McVideoProtectGpuOverride0 = 0x00000000,
.McVideoProtectGpuOverride1 = 0x00000000,
.McSecCarveoutBom = 0xfff00000,
.McSecCarveoutAdrHi = 0x00000000,
.McSecCarveoutSizeMb = 0x00000000,
.McVideoProtectWriteAccess = 0x00000000,
.McSecCarveoutProtectWriteAccess = 0x00000000,
.EmcCaTrainingEnable = 0x00000000,
.EmcCaTrainingTimingCntl1 = 0x1f7df7df,
.EmcCaTrainingTimingCntl2 = 0x0000001f,
.SwizzleRankByteEncode = 0x0000006f,
.BootRomPatchControl = 0x00000000,
.BootRomPatchData = 0x00000000,
.McMtsCarveoutBom = 0xfff00000,
.McMtsCarveoutAdrHi = 0x00000000,
.McMtsCarveoutSizeMb = 0x00000000,
.McMtsCarveoutRegCtrl = 0x00000000,
},

311
src/mainboard/google/nyan/bct/sdram-hynix-2GB-924.inc Normal file
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{ /* generated from sdram-0001-924-2GB.cfg; do not edit. */
.MemoryType = NvBootMemoryType_Ddr3,
.PllMInputDivider = 0x00000001,
.PllMFeedbackDivider = 0x0000004d,
.PllMStableTime = 0x0000012c,
.PllMSetupControl = 0x00000000,
.PllMSelectDiv2 = 0x00000000,
.PllMPDLshiftPh45 = 0x00000001,
.PllMPDLshiftPh90 = 0x00000001,
.PllMPDLshiftPh135 = 0x00000001,
.PllMKCP = 0x00000000,
.PllMKVCO = 0x00000000,
.EmcBctSpare0 = 0x00000000,
.EmcBctSpare1 = 0x00000000,
.EmcBctSpare2 = 0x00000000,
.EmcBctSpare3 = 0x00000000,
.EmcBctSpare4 = 0x00000000,
.EmcBctSpare5 = 0x00000000,
.EmcBctSpare6 = 0x00000000,
.EmcBctSpare7 = 0x00000000,
.EmcBctSpare8 = 0x00000000,
.EmcBctSpare9 = 0x00000000,
.EmcBctSpare10 = 0x00000000,
.EmcBctSpare11 = 0x00000000,
.EmcClockSource = 0x80000000,
.EmcAutoCalInterval = 0x001fffff,
.EmcAutoCalConfig = 0xa1430404,
.EmcAutoCalConfig2 = 0x00000000,
.EmcAutoCalConfig3 = 0x00000000,
.EmcAutoCalWait = 0x00000190,
.EmcAdrCfg = 0x00000000,
.EmcPinProgramWait = 0x00000001,
.EmcPinExtraWait = 0x00000000,
.EmcTimingControlWait = 0x00000000,
.EmcRc = 0x0000002b,
.EmcRfc = 0x000000ef,
.EmcRfcSlr = 0x00000000,
.EmcRas = 0x0000001e,
.EmcRp = 0x0000000b,
.EmcR2r = 0x00000000,
.EmcW2w = 0x00000000,
.EmcR2w = 0x00000008,
.EmcW2r = 0x0000000f,
.EmcR2p = 0x00000005,
.EmcW2p = 0x00000016,
.EmcRdRcd = 0x0000000b,
.EmcWrRcd = 0x0000000b,
.EmcRrd = 0x00000004,
.EmcRext = 0x00000002,
.EmcWext = 0x00000000,
.EmcWdv = 0x00000006,
.EmcWdvMask = 0x00000006,
.EmcQUse = 0x0000000c,
.EmcQuseWidth = 0x00000002,
.EmcIbdly = 0x00000000,
.EmcEInput = 0x00000002,
.EmcEInputDuration = 0x0000000e,
.EmcPutermExtra = 0x000a0000,
.EmcPutermWidth = 0x00000004,
.EmcPutermAdj = 0x00000000,
.EmcCdbCntl1 = 0x00000000,
.EmcCdbCntl2 = 0x00000000,
.EmcCdbCntl3 = 0x00000000,
.EmcQRst = 0x00000001,
.EmcQSafe = 0x00000015,
.EmcRdv = 0x0000001b,
.EmcRdvMask = 0x0000001d,
.EmcQpop = 0x00000010,
.EmcCtt = 0x00000000,
.EmcCttDuration = 0x00000004,
.EmcRefresh = 0x00001be9,
.EmcBurstRefreshNum = 0x00000000,
.EmcPreRefreshReqCnt = 0x000006fa,
.EmcPdEx2Wr = 0x00000004,
.EmcPdEx2Rd = 0x00000015,
.EmcPChg2Pden = 0x00000001,
.EmcAct2Pden = 0x00000000,
.EmcAr2Pden = 0x000000e6,
.EmcRw2Pden = 0x0000001b,
.EmcTxsr = 0x000000fa,
.EmcTxsrDll = 0x00000200,
.EmcTcke = 0x00000006,
.EmcTckesr = 0x00000007,
.EmcTpd = 0x00000006,
.EmcTfaw = 0x00000022,
.EmcTrpab = 0x00000000,
.EmcTClkStable = 0x0000000a,
.EmcTClkStop = 0x0000000a,
.EmcTRefBw = 0x00001c29,
.EmcFbioCfg5 = 0x104ab898,
.EmcFbioCfg6 = 0x00000002,
.EmcFbioSpare = 0x00000000,
.EmcCfgRsv = 0xff00ff00,
.EmcMrs = 0x80000f15,
.EmcEmrs = 0x80100002,
.EmcEmrs2 = 0x80200020,
.EmcEmrs3 = 0x80300000,
.EmcMrw1 = 0x00000000,
.EmcMrw2 = 0x00000000,
.EmcMrw3 = 0x00000000,
.EmcMrw4 = 0x00000000,
.EmcMrwExtra = 0x00000000,
.EmcWarmBootMrwExtra = 0x00000000,
.EmcWarmBootExtraModeRegWriteEnable = 0x00000000,
.EmcExtraModeRegWriteEnable = 0x00000000,
.EmcMrwResetCommand = 0x00000000,
.EmcMrwResetNInitWait = 0x00000000,
.EmcMrsWaitCnt = 0x00ce000e,
.EmcMrsWaitCnt2 = 0x00ce000e,
.EmcCfg = 0x73300000,
.EmcCfg2 = 0x000008a5,
.EmcCfgPipe = 0x00000000,
.EmcDbg = 0x01000c00,
.EmcCmdQ = 0x10004408,
.EmcMc2EmcQ = 0x06000404,
.EmcDynSelfRefControl = 0x800037ed,
.AhbArbitrationXbarCtrlMemInitDone = 0x00000001,
.EmcCfgDigDll = 0xe00401b1,
.EmcCfgDigDllPeriod = 0x00008000,
.EmcDevSelect = 0x00000002,
.EmcSelDpdCtrl = 0x00040000,
.EmcDllXformDqs0 = 0x00000005,
.EmcDllXformDqs1 = 0x00000005,
.EmcDllXformDqs2 = 0x00000005,
.EmcDllXformDqs3 = 0x00000005,
.EmcDllXformDqs4 = 0x00000005,
.EmcDllXformDqs5 = 0x00000005,
.EmcDllXformDqs6 = 0x00000005,
.EmcDllXformDqs7 = 0x00000005,
.EmcDllXformDqs8 = 0x00000005,
.EmcDllXformDqs9 = 0x00000005,
.EmcDllXformDqs10 = 0x00000005,
.EmcDllXformDqs11 = 0x00000005,
.EmcDllXformDqs12 = 0x00000005,
.EmcDllXformDqs13 = 0x00000005,
.EmcDllXformDqs14 = 0x00000005,
.EmcDllXformDqs15 = 0x00000005,
.EmcDllXformQUse0 = 0x00000000,
.EmcDllXformQUse1 = 0x00000000,
.EmcDllXformQUse2 = 0x00000000,
.EmcDllXformQUse3 = 0x00000000,
.EmcDllXformQUse4 = 0x00000000,
.EmcDllXformQUse5 = 0x00000000,
.EmcDllXformQUse6 = 0x00000000,
.EmcDllXformQUse7 = 0x00000000,
.EmcDllXformAddr0 = 0x0000400e,
.EmcDllXformAddr1 = 0x0000400e,
.EmcDllXformAddr2 = 0x00000000,
.EmcDllXformAddr3 = 0x0000400e,
.EmcDllXformAddr4 = 0x0000400e,
.EmcDllXformAddr5 = 0x00000000,
.EmcDllXformQUse8 = 0x00000000,
.EmcDllXformQUse9 = 0x00000000,
.EmcDllXformQUse10 = 0x00000000,
.EmcDllXformQUse11 = 0x00000000,
.EmcDllXformQUse12 = 0x00000000,
.EmcDllXformQUse13 = 0x00000000,
.EmcDllXformQUse14 = 0x00000000,
.EmcDllXformQUse15 = 0x00000000,
.EmcDliTrimTxDqs0 = 0x00000000,
.EmcDliTrimTxDqs1 = 0x00000000,
.EmcDliTrimTxDqs2 = 0x00000000,
.EmcDliTrimTxDqs3 = 0x00000000,
.EmcDliTrimTxDqs4 = 0x00000000,
.EmcDliTrimTxDqs5 = 0x00000000,
.EmcDliTrimTxDqs6 = 0x00000000,
.EmcDliTrimTxDqs7 = 0x00000000,
.EmcDliTrimTxDqs8 = 0x00000000,
.EmcDliTrimTxDqs9 = 0x00000000,
.EmcDliTrimTxDqs10 = 0x00000000,
.EmcDliTrimTxDqs11 = 0x00000000,
.EmcDliTrimTxDqs12 = 0x00000000,
.EmcDliTrimTxDqs13 = 0x00000000,
.EmcDliTrimTxDqs14 = 0x00000000,
.EmcDliTrimTxDqs15 = 0x00000000,
.EmcDllXformDq0 = 0x00000006,
.EmcDllXformDq1 = 0x00000006,
.EmcDllXformDq2 = 0x00000006,
.EmcDllXformDq3 = 0x00000006,
.EmcDllXformDq4 = 0x00000006,
.EmcDllXformDq5 = 0x00000006,
.EmcDllXformDq6 = 0x00000006,
.EmcDllXformDq7 = 0x00000006,
.WarmBootWait = 0x00000002,
.EmcCttTermCtrl = 0x00000802,
.EmcOdtWrite = 0x00000000,
.EmcOdtRead = 0x00000000,
.EmcZcalInterval = 0x00020000,
.EmcZcalWaitCnt = 0x0000004c,
.EmcZcalMrwCmd = 0x80000000,
.EmcMrsResetDll = 0x00000000,
.EmcZcalInitDev0 = 0x80000011,
.EmcZcalInitDev1 = 0x00000000,
.EmcZcalInitWait = 0x00000001,
.EmcZcalWarmColdBootEnables = 0x00000003,
.EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab,
.EmcZqCalDdr3WarmBoot = 0x00000000,
.EmcZcalWarmBootWait = 0x00000001,
.EmcMrsWarmBootEnable = 0x00000001,
.EmcMrsResetDllWait = 0x00000000,
.EmcMrsExtra = 0x80000f15,
.EmcWarmBootMrsExtra = 0x80100002,
.EmcEmrsDdr2DllEnable = 0x00000000,
.EmcMrsDdr2DllReset = 0x00000000,
.EmcEmrsDdr2OcdCalib = 0x00000000,
.EmcDdr2Wait = 0x00000000,
.EmcClkenOverride = 0x00000000,
.McDisExtraSnapLevels = 0x00000000,
.EmcExtraRefreshNum = 0x00000002,
.EmcClkenOverrideAllWarmBoot = 0x00000000,
.McClkenOverrideAllWarmBoot = 0x00000000,
.EmcCfgDigDllPeriodWarmBoot = 0x00000003,
.PmcVddpSel = 0x00000002,
.PmcVddpSelWait = 0x00000002,
.PmcDdrPwr = 0x00000003,
.PmcDdrCfg = 0x00002002,
.PmcIoDpd3Req = 0x4fff2f97,
.PmcIoDpd3ReqWait = 0x00000000,
.PmcRegShort = 0x00000000,
.PmcNoIoPower = 0x00000000,
.PmcPorDpdCtrlWait = 0x00000000,
.EmcXm2CmdPadCtrl = 0x100002a0,
.EmcXm2CmdPadCtrl2 = 0x770c0000,
.EmcXm2CmdPadCtrl3 = 0x050c0000,
.EmcXm2CmdPadCtrl4 = 0x00000000,
.EmcXm2CmdPadCtrl5 = 0x00111111,
.EmcXm2DqsPadCtrl = 0x770c1414,
.EmcXm2DqsPadCtrl2 = 0x0020013d,
.EmcXm2DqsPadCtrl3 = 0x55555520,
.EmcXm2DqsPadCtrl4 = 0x003cf3cf,
.EmcXm2DqsPadCtrl5 = 0x003cf3cf,
.EmcXm2DqsPadCtrl6 = 0x55555500,
.EmcXm2DqPadCtrl = 0x770c2990,
.EmcXm2DqPadCtrl2 = 0x00000000,
.EmcXm2DqPadCtrl3 = 0x00000000,
.EmcXm2ClkPadCtrl = 0x77ffc085,
.EmcXm2ClkPadCtrl2 = 0x00000303,
.EmcXm2CompPadCtrl = 0x81f1f108,
.EmcXm2VttGenPadCtrl = 0x07070004,
.EmcXm2VttGenPadCtrl2 = 0x00000000,
.EmcXm2VttGenPadCtrl3 = 0x016eeeee,
.EmcAcpdControl = 0x00000000,
.EmcSwizzleRank0ByteCfg = 0x00003120,
.EmcSwizzleRank0Byte0 = 0x25143067,
.EmcSwizzleRank0Byte1 = 0x45367102,
.EmcSwizzleRank0Byte2 = 0x47106253,
.EmcSwizzleRank0Byte3 = 0x04362175,
.EmcSwizzleRank1ByteCfg = 0x00003120,
.EmcSwizzleRank1Byte0 = 0x71546032,
.EmcSwizzleRank1Byte1 = 0x35104276,
.EmcSwizzleRank1Byte2 = 0x27043615,
.EmcSwizzleRank1Byte3 = 0x72306145,
.EmcDsrVttgenDrv = 0x0606003f,
.EmcTxdsrvttgen = 0x00000000,
.EmcBgbiasCtl0 = 0x00000000,
.McEmemAdrCfg = 0x00000000,
.McEmemAdrCfgDev0 = 0x00080303,
.McEmemAdrCfgDev1 = 0x00080303,
.McEmemAdrCfgBankMask0 = 0x00001248,
.McEmemAdrCfgBankMask1 = 0x00002490,
.McEmemAdrCfgBankMask2 = 0x00000920,
.McEmemAdrCfgBankSwizzle3 = 0x00000001,
.McEmemCfg = 0x00000800,
.McEmemArbCfg = 0x0e00000d,
.McEmemArbOutstandingReq = 0x80000040,
.McEmemArbTimingRcd = 0x00000005,
.McEmemArbTimingRp = 0x00000006,
.McEmemArbTimingRc = 0x00000016,
.McEmemArbTimingRas = 0x0000000e,
.McEmemArbTimingFaw = 0x00000011,
.McEmemArbTimingRrd = 0x00000002,
.McEmemArbTimingRap2Pre = 0x00000004,
.McEmemArbTimingWap2Pre = 0x0000000e,
.McEmemArbTimingR2R = 0x00000002,
.McEmemArbTimingW2W = 0x00000002,
.McEmemArbTimingR2W = 0x00000006,
.McEmemArbTimingW2R = 0x00000009,
.McEmemArbDaTurns = 0x09060202,
.McEmemArbDaCovers = 0x001a1016,
.McEmemArbMisc0 = 0x734e2a17,
.McEmemArbMisc1 = 0x70000f02,
.McEmemArbRing1Throttle = 0x001f0000,
.McEmemArbOverride = 0x10000000,
.McEmemArbOverride1 = 0x00000000,
.McEmemArbRsv = 0xff00ff00,
.McClkenOverride = 0x00000000,
.McStatControl = 0x00000000,
.McDisplaySnapRing = 0x00000003,
.McVideoProtectBom = 0xfff00000,
.McVideoProtectBomAdrHi = 0x00000000,
.McVideoProtectSizeMb = 0x00000000,
.McVideoProtectVprOverride = 0xe4bac743,
.McVideoProtectVprOverride1 = 0x00000013,
.McVideoProtectGpuOverride0 = 0x00000000,
.McVideoProtectGpuOverride1 = 0x00000000,
.McSecCarveoutBom = 0xfff00000,
.McSecCarveoutAdrHi = 0x00000000,
.McSecCarveoutSizeMb = 0x00000000,
.McVideoProtectWriteAccess = 0x00000000,
.McSecCarveoutProtectWriteAccess = 0x00000000,
.EmcCaTrainingEnable = 0x00000000,
.EmcCaTrainingTimingCntl1 = 0x1f7df7df,
.EmcCaTrainingTimingCntl2 = 0x0000001f,
.SwizzleRankByteEncode = 0x0000006f,
.BootRomPatchControl = 0x00000000,
.BootRomPatchData = 0x00000000,
.McMtsCarveoutBom = 0xfff00000,
.McMtsCarveoutAdrHi = 0x00000000,
.McMtsCarveoutSizeMb = 0x00000000,
.McMtsCarveoutRegCtrl = 0x00000000,
},

4
src/mainboard/google/nyan/bct/sdram-unused.inc Normal file
View File

@ -0,0 +1,4 @@
{ /* dummy. */
.MemoryType = NvBootMemoryType_Unused,
0,
},

18
src/mainboard/google/nyan/bootblock.c
View File

@ -72,17 +72,19 @@ void bootblock_mainboard_init(void)
pmic_init(4); pmic_init(4);
/* SPI4 data out (MOSI) */ /* SPI4 data out (MOSI) */
pinmux_set_config(PINMUX_SDMMC1_CMD_INDEX, pinmux_set_config(PINMUX_GPIO_PG6_INDEX,
PINMUX_SDMMC1_CMD_FUNC_SPI4 | PINMUX_INPUT_ENABLE); PINMUX_GPIO_PG6_FUNC_SPI4 | PINMUX_INPUT_ENABLE |
PINMUX_PULL_UP);
/* SPI4 data in (MISO) */ /* SPI4 data in (MISO) */
pinmux_set_config(PINMUX_SDMMC1_DAT1_INDEX, pinmux_set_config(PINMUX_GPIO_PG7_INDEX,
PINMUX_SDMMC1_DAT1_FUNC_SPI4 | PINMUX_INPUT_ENABLE); PINMUX_GPIO_PG7_FUNC_SPI4 | PINMUX_INPUT_ENABLE |
PINMUX_PULL_UP);
/* SPI4 clock */ /* SPI4 clock */
pinmux_set_config(PINMUX_SDMMC1_DAT2_INDEX, pinmux_set_config(PINMUX_GPIO_PG5_INDEX,
PINMUX_SDMMC1_DAT2_FUNC_SPI4 | PINMUX_INPUT_ENABLE); PINMUX_GPIO_PG5_FUNC_SPI4 | PINMUX_INPUT_ENABLE);
/* SPI4 chip select 0 */ /* SPI4 chip select 0 */
pinmux_set_config(PINMUX_SDMMC1_DAT3_INDEX, pinmux_set_config(PINMUX_GPIO_PI3_INDEX,
PINMUX_SDMMC1_DAT3_FUNC_SPI4 | PINMUX_INPUT_ENABLE); PINMUX_GPIO_PI3_FUNC_SPI4 | PINMUX_INPUT_ENABLE);
tegra_spi_init(4); tegra_spi_init(4);
} }

22
src/mainboard/google/nyan/romstage.c
View File

@ -25,15 +25,12 @@
#include <cbfs.h> #include <cbfs.h>
#include <cbmem.h> #include <cbmem.h>
#include <console/console.h> #include <console/console.h>
#include "sdram_configs.h"
#include "soc/nvidia/tegra124/chip.h" #include "soc/nvidia/tegra124/chip.h"
#include "soc/nvidia/tegra124/sdram.h"
#include <soc/display.h> #include <soc/display.h>
#include <timestamp.h> #include <timestamp.h>
// Convenient shorthand (in MB)
#define DRAM_START (CONFIG_SYS_SDRAM_BASE >> 20)
#define DRAM_SIZE CONFIG_DRAM_SIZE_MB
#define DRAM_END (DRAM_START + DRAM_SIZE) /* plus one... */
enum { enum {
L2CTLR_ECC_PARITY = 0x1 << 21, L2CTLR_ECC_PARITY = 0x1 << 21,
L2CTLR_TAG_RAM_LATENCY_MASK = 0x7 << 6, L2CTLR_TAG_RAM_LATENCY_MASK = 0x7 << 6,
@ -74,6 +71,7 @@ static void configure_l2actlr(void)
void main(void) void main(void)
{ {
int dram_size_mb;
#if CONFIG_COLLECT_TIMESTAMPS #if CONFIG_COLLECT_TIMESTAMPS
uint64_t romstage_start_time = timestamp_get(); uint64_t romstage_start_time = timestamp_get();
#endif #endif
@ -97,12 +95,20 @@ void main(void)
console_init(); console_init();
exception_init(); exception_init();
sdram_init(get_sdram_config());
/* used for MMU and CBMEM setup */
dram_size_mb = sdram_size_mb();
u32 dram_start = (CONFIG_SYS_SDRAM_BASE >> 20);
u32 dram_end = dram_start + dram_size_mb; /* plus one... */
mmu_init(); mmu_init();
mmu_config_range(0, DRAM_START, DCACHE_OFF); mmu_config_range(0, dram_start, DCACHE_OFF);
mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK); mmu_config_range(dram_start, dram_size_mb, DCACHE_WRITEBACK);
mmu_config_range(CONFIG_DRAM_DMA_START >> 20, mmu_config_range(CONFIG_DRAM_DMA_START >> 20,
CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF); CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF);
mmu_config_range(DRAM_END, 4096 - DRAM_END, DCACHE_OFF); mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF);
mmu_disable_range(0, 1); mmu_disable_range(0, 1);
dcache_invalidate_all(); dcache_invalidate_all();
dcache_mmu_enable(); dcache_mmu_enable();

58
src/mainboard/google/nyan/sdram_configs.c Normal file
View File

@ -0,0 +1,58 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <console/console.h>
#include <soc/nvidia/tegra124/sdram.h>
#include "sdram_configs.h"
static struct sdram_params sdram_configs[] = {
#include "bct/sdram-hynix-2GB-792.inc" /* ram_code = 0000 */
#include "bct/sdram-unused.inc" /* ram_code = 0001 */
#include "bct/sdram-unused.inc" /* ram_code = 0010 */
#include "bct/sdram-unused.inc" /* ram_code = 0011 */
#include "bct/sdram-unused.inc" /* ram_code = 0100 */
#include "bct/sdram-unused.inc" /* ram_code = 0101 */
#include "bct/sdram-unused.inc" /* ram_code = 0110 */
#include "bct/sdram-unused.inc" /* ram_code = 0111 */
#include "bct/sdram-unused.inc" /* ram_code = 1000 */
#include "bct/sdram-unused.inc" /* ram_code = 1001 */
#include "bct/sdram-unused.inc" /* ram_code = 1010 */
#include "bct/sdram-unused.inc" /* ram_code = 1011 */
#include "bct/sdram-unused.inc" /* ram_code = 1100 */
#include "bct/sdram-unused.inc" /* ram_code = 1101 */
#include "bct/sdram-unused.inc" /* ram_code = 1110 */
#include "bct/sdram-unused.inc" /* ram_code = 1111 */
};
const struct sdram_params *get_sdram_config()
{
uint32_t ramcode = sdram_get_ram_code();
/*
* If we need to apply some special hacks to RAMCODE mapping (ex, by
* board_id), do that now.
*/
printk(BIOS_SPEW, "%s: RAMCODE=%d\n", __func__, ramcode);
if (ramcode >= sizeof(sdram_configs) / sizeof(sdram_configs[0]) ||
sdram_configs[ramcode].MemoryType == NvBootMemoryType_Unused) {
die("Invalid RAMCODE.");
}
return &sdram_configs[ramcode];
}

28
src/mainboard/google/nyan/sdram_configs.h Normal file
View File

@ -0,0 +1,28 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __MAINBOARD_GOOGLE_NYAN_SDRAM_CONFIG_H__
#define __MAINBOARD_GOOGLE_NYAN_SDRAM_CONFIG_H__
#include <soc/nvidia/tegra124/sdram_param.h>
/* Loads SDRAM configurations for current system. */
const struct sdram_params *get_sdram_config(void);
#endif /* __MAINBOARD_GOOGLE_NYAN_SDRAM_CONFIG_H__ */

18
src/mainboard/google/nyan_big/Kconfig
View File

@ -40,10 +40,6 @@ config MAINBOARD_PART_NUMBER
string string
default "Nyan Big" default "Nyan Big"
config DRAM_SIZE_MB
int
default 2048
config DRAM_DMA_START config DRAM_DMA_START
hex hex
default 0x90000000 default 0x90000000
@ -90,18 +86,4 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS
hex hex
default 1 default 1
choice
prompt "BCT sdram configuration"
default NYAN_BIG_BCT_SDRAM_792
help
The SDRAM configuration to put in the BCT.
config NYAN_BIG_BCT_SDRAM_792
bool "792 MHz"
config NYAN_BIG_BCT_SDRAM_924
bool "924 MHz"
endchoice
endif # BOARD_GOOGLE_NYAN_BIG endif # BOARD_GOOGLE_NYAN_BIG

1
src/mainboard/google/nyan_big/Makefile.inc
View File

@ -32,6 +32,7 @@ bootblock-y += bootblock.c
bootblock-y += pmic.c bootblock-y += pmic.c
romstage-y += romstage.c romstage-y += romstage.c
romstage-y += sdram_configs.c
romstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-$(CONFIG_CHROMEOS) += chromeos.c
ramstage-y += mainboard.c ramstage-y += mainboard.c

6
src/mainboard/google/nyan_big/bct/Makefile.inc
View File

@ -20,5 +20,7 @@
bct-cfg-$(CONFIG_NYAN_BIG_BCT_CFG_EMMC) += emmc.cfg bct-cfg-$(CONFIG_NYAN_BIG_BCT_CFG_EMMC) += emmc.cfg
bct-cfg-$(CONFIG_NYAN_BIG_BCT_CFG_SPI) += spi.cfg bct-cfg-$(CONFIG_NYAN_BIG_BCT_CFG_SPI) += spi.cfg
bct-cfg-y += odmdata.cfg bct-cfg-y += odmdata.cfg
bct-cfg-$(CONFIG_NYAN_BIG_BCT_SDRAM_924) += sdram-924.cfg
bct-cfg-$(CONFIG_NYAN_BIG_BCT_SDRAM_792) += sdram-792.cfg # Note when SDRAM config (sdram-*.cfg) files are changed, we have to regenerate
# the include files (sdram-*.inc). See ../../nyan/bct/Makefile.inc for more
# information.

346
src/mainboard/google/nyan_big/bct/sdram-792.cfg
View File

@ -1,346 +0,0 @@
# CFG Version 07
# Do not edit. Generated by gen_sdram_cfg V4.0.7. Command:
# gen_sdram_cfg -i ddr3_256Mx16x4_H5TC4G63AFR_RDA.par 1.262 -dram_board_cfg 10 -fly_by_time_ps 1650
# -b PM358/PM358_792MHz_emc_reg.txt -o PM358_Hynix_2GB_H5TC4G63AFR_RDA_792Mhz.cfg
# Parameter file: ddr3_256Mx16x4_H5TC4G63AFR_RDA.par, tck = 1.26 ns (792.39 MHz)
# bkv file: PM358/PM358_792MHz_emc_reg.txt
SDRAM[0].MemoryType = NvBootMemoryType_Ddr3;
SDRAM[0].PllMInputDivider = 0x00000001;
SDRAM[0].PllMFeedbackDivider = 0x00000042;
SDRAM[0].PllMStableTime = 0x0000012c;
SDRAM[0].PllMSetupControl = 0x00000000;
SDRAM[0].PllMSelectDiv2 = 0x00000000;
SDRAM[0].PllMPDLshiftPh45 = 0x00000001;
SDRAM[0].PllMPDLshiftPh90 = 0x00000001;
SDRAM[0].PllMPDLshiftPh135 = 0x00000001;
SDRAM[0].PllMKCP = 0x00000000;
SDRAM[0].PllMKVCO = 0x00000000;
SDRAM[0].EmcBctSpare0 = 0x00000000;
SDRAM[0].EmcBctSpare1 = 0x00000000;
SDRAM[0].EmcBctSpare2 = 0x00000000;
SDRAM[0].EmcBctSpare3 = 0x00000000;
SDRAM[0].EmcBctSpare4 = 0x00000000;
SDRAM[0].EmcBctSpare5 = 0x00000000;
SDRAM[0].EmcBctSpare6 = 0x00000000;
SDRAM[0].EmcBctSpare7 = 0x00000000;
SDRAM[0].EmcBctSpare8 = 0x00000000;
SDRAM[0].EmcBctSpare9 = 0x00000000;
SDRAM[0].EmcBctSpare10 = 0x00000000;
SDRAM[0].EmcBctSpare11 = 0x00000000;
SDRAM[0].EmcClockSource = 0x80000000;
SDRAM[0].EmcAutoCalInterval = 0x001fffff;
SDRAM[0].EmcAutoCalConfig = 0xa1430000;
SDRAM[0].EmcAutoCalConfig2 = 0x00000000;
SDRAM[0].EmcAutoCalConfig3 = 0x00000000;
SDRAM[0].EmcAutoCalWait = 0x00000190;
SDRAM[0].EmcAdrCfg = 0x00000000;
SDRAM[0].EmcPinProgramWait = 0x00000001;
SDRAM[0].EmcPinExtraWait = 0x00000000;
SDRAM[0].EmcTimingControlWait = 0x00000000;
SDRAM[0].EmcRc = 0x00000025;
SDRAM[0].EmcRfc = 0x000000cd;
SDRAM[0].EmcRfcSlr = 0x00000000;
SDRAM[0].EmcRas = 0x00000019;
SDRAM[0].EmcRp = 0x0000000a;
SDRAM[0].EmcR2r = 0x00000000;
SDRAM[0].EmcW2w = 0x00000000;
SDRAM[0].EmcR2w = 0x00000007;
SDRAM[0].EmcW2r = 0x0000000d;
SDRAM[0].EmcR2p = 0x00000004;
SDRAM[0].EmcW2p = 0x00000013;
SDRAM[0].EmcRdRcd = 0x0000000a;
SDRAM[0].EmcWrRcd = 0x0000000a;
SDRAM[0].EmcRrd = 0x00000003;
SDRAM[0].EmcRext = 0x00000002;
SDRAM[0].EmcWext = 0x00000000;
SDRAM[0].EmcWdv = 0x00000006;
SDRAM[0].EmcWdvMask = 0x00000006;
SDRAM[0].EmcQUse = 0x0000000b;
SDRAM[0].EmcQuseWidth = 0x00000002;
SDRAM[0].EmcIbdly = 0x00000000;
SDRAM[0].EmcEInput = 0x00000003;
SDRAM[0].EmcEInputDuration = 0x0000000c;
SDRAM[0].EmcPutermExtra = 0x00090000;
SDRAM[0].EmcPutermWidth = 0x00000004;
SDRAM[0].EmcPutermAdj = 0x00000000;
SDRAM[0].EmcCdbCntl1 = 0x00000000;
SDRAM[0].EmcCdbCntl2 = 0x00000000;
SDRAM[0].EmcCdbCntl3 = 0x00000000;
SDRAM[0].EmcQRst = 0x00000002;
SDRAM[0].EmcQSafe = 0x00000011;
SDRAM[0].EmcRdv = 0x00000017;
SDRAM[0].EmcRdvMask = 0x00000019;
SDRAM[0].EmcQpop = 0x0000000f;
SDRAM[0].EmcCtt = 0x00000000;
SDRAM[0].EmcCttDuration = 0x00000004;
SDRAM[0].EmcRefresh = 0x000017eb;
SDRAM[0].EmcBurstRefreshNum = 0x00000000;
SDRAM[0].EmcPreRefreshReqCnt = 0x000005fa;
SDRAM[0].EmcPdEx2Wr = 0x00000003;
SDRAM[0].EmcPdEx2Rd = 0x00000003;
SDRAM[0].EmcPChg2Pden = 0x00000001;
SDRAM[0].EmcAct2Pden = 0x00000000;
SDRAM[0].EmcAr2Pden = 0x000000c7;
SDRAM[0].EmcRw2Pden = 0x00000018;
SDRAM[0].EmcTxsr = 0x000000d7;
SDRAM[0].EmcTxsrDll = 0x00000200;
SDRAM[0].EmcTcke = 0x00000005;
SDRAM[0].EmcTckesr = 0x00000006;
SDRAM[0].EmcTpd = 0x00000005;
SDRAM[0].EmcTfaw = 0x0000001d;
SDRAM[0].EmcTrpab = 0x00000000;
SDRAM[0].EmcTClkStable = 0x00000008;
SDRAM[0].EmcTClkStop = 0x00000008;
SDRAM[0].EmcTRefBw = 0x0000182c;
SDRAM[0].EmcFbioCfg5 = 0x104ab898;
SDRAM[0].EmcFbioCfg6 = 0x00000002;
SDRAM[0].EmcFbioSpare = 0x00000000;
SDRAM[0].EmcCfgRsv = 0xff00ff00;
SDRAM[0].EmcMrs = 0x80001d71;
SDRAM[0].EmcEmrs = 0x80100002;
SDRAM[0].EmcEmrs2 = 0x80200018;
SDRAM[0].EmcEmrs3 = 0x80300000;
SDRAM[0].EmcMrw1 = 0x00000000;
SDRAM[0].EmcMrw2 = 0x00000000;
SDRAM[0].EmcMrw3 = 0x00000000;
SDRAM[0].EmcMrw4 = 0x00000000;
SDRAM[0].EmcMrwExtra = 0x00000000;
SDRAM[0].EmcWarmBootMrwExtra = 0x00000000;
SDRAM[0].EmcWarmBootExtraModeRegWriteEnable = 0x00000000;
SDRAM[0].EmcExtraModeRegWriteEnable = 0x00000000;
SDRAM[0].EmcMrwResetCommand = 0x00000000;
SDRAM[0].EmcMrwResetNInitWait = 0x00000000;
SDRAM[0].EmcMrsWaitCnt = 0x00f7000e;
SDRAM[0].EmcMrsWaitCnt2 = 0x00f7000e;
SDRAM[0].EmcCfg = 0x73300000;
SDRAM[0].EmcCfg2 = 0x0000089d;
SDRAM[0].EmcCfgPipe = 0x000040a0;
SDRAM[0].EmcDbg = 0x01000c00;
SDRAM[0].EmcCmdQ = 0x10004408;
SDRAM[0].EmcMc2EmcQ = 0x06000404;
SDRAM[0].EmcDynSelfRefControl = 0x80003025;
SDRAM[0].AhbArbitrationXbarCtrlMemInitDone = 0x00000001;
SDRAM[0].EmcCfgDigDll = 0xe00701b1;
SDRAM[0].EmcCfgDigDllPeriod = 0x00008000;
SDRAM[0].EmcDevSelect = 0x00000002;
SDRAM[0].EmcSelDpdCtrl = 0x00040000;
SDRAM[0].EmcDllXformDqs0 = 0x00000008;
SDRAM[0].EmcDllXformDqs1 = 0x00000008;
SDRAM[0].EmcDllXformDqs2 = 0x00000008;
SDRAM[0].EmcDllXformDqs3 = 0x00000008;
SDRAM[0].EmcDllXformDqs4 = 0x00000008;
SDRAM[0].EmcDllXformDqs5 = 0x00000008;
SDRAM[0].EmcDllXformDqs6 = 0x00000008;
SDRAM[0].EmcDllXformDqs7 = 0x00000008;
SDRAM[0].EmcDllXformDqs8 = 0x00000008;
SDRAM[0].EmcDllXformDqs9 = 0x00000008;
SDRAM[0].EmcDllXformDqs10 = 0x00000008;
SDRAM[0].EmcDllXformDqs11 = 0x00000008;
SDRAM[0].EmcDllXformDqs12 = 0x00000008;
SDRAM[0].EmcDllXformDqs13 = 0x00000008;
SDRAM[0].EmcDllXformDqs14 = 0x00000008;
SDRAM[0].EmcDllXformDqs15 = 0x00000008;
SDRAM[0].EmcDllXformQUse0 = 0x00000000;
SDRAM[0].EmcDllXformQUse1 = 0x00000000;
SDRAM[0].EmcDllXformQUse2 = 0x00000000;
SDRAM[0].EmcDllXformQUse3 = 0x00000000;
SDRAM[0].EmcDllXformQUse4 = 0x00000000;
SDRAM[0].EmcDllXformQUse5 = 0x00000000;
SDRAM[0].EmcDllXformQUse6 = 0x00000000;
SDRAM[0].EmcDllXformQUse7 = 0x00000000;
SDRAM[0].EmcDllXformAddr0 = 0x0000000e;
SDRAM[0].EmcDllXformAddr1 = 0x0000000e;
SDRAM[0].EmcDllXformAddr2 = 0x00000000;
SDRAM[0].EmcDllXformAddr3 = 0x0000000e;
SDRAM[0].EmcDllXformAddr4 = 0x00000000;
SDRAM[0].EmcDllXformAddr5 = 0x00000000;
SDRAM[0].EmcDllXformQUse8 = 0x00000000;
SDRAM[0].EmcDllXformQUse9 = 0x00000000;
SDRAM[0].EmcDllXformQUse10 = 0x00000000;
SDRAM[0].EmcDllXformQUse11 = 0x00000000;
SDRAM[0].EmcDllXformQUse12 = 0x00000000;
SDRAM[0].EmcDllXformQUse13 = 0x00000000;
SDRAM[0].EmcDllXformQUse14 = 0x00000000;
SDRAM[0].EmcDllXformQUse15 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs0 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs1 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs2 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs3 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs4 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs5 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs6 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs7 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs8 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs9 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs10 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs11 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs12 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs13 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs14 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs15 = 0x00000000;
SDRAM[0].EmcDllXformDq0 = 0x0000000b;
SDRAM[0].EmcDllXformDq1 = 0x0000000b;
SDRAM[0].EmcDllXformDq2 = 0x0000000b;
SDRAM[0].EmcDllXformDq3 = 0x0000000b;
SDRAM[0].EmcDllXformDq4 = 0x0000000b;
SDRAM[0].EmcDllXformDq5 = 0x0000000b;
SDRAM[0].EmcDllXformDq6 = 0x0000000b;
SDRAM[0].EmcDllXformDq7 = 0x0000000b;
SDRAM[0].WarmBootWait = 0x00000002;
SDRAM[0].EmcCttTermCtrl = 0x00000802;
SDRAM[0].EmcOdtWrite = 0x00000000;
SDRAM[0].EmcOdtRead = 0x00000000;
SDRAM[0].EmcZcalInterval = 0x00020000;
SDRAM[0].EmcZcalWaitCnt = 0x00000042;
SDRAM[0].EmcZcalMrwCmd = 0x80000000;
SDRAM[0].EmcMrsResetDll = 0x00000000;
SDRAM[0].EmcZcalInitDev0 = 0x80000011;
SDRAM[0].EmcZcalInitDev1 = 0x00000000;
SDRAM[0].EmcZcalInitWait = 0x00000001;
SDRAM[0].EmcZcalWarmColdBootEnables = 0x00000003;
SDRAM[0].EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab;
SDRAM[0].EmcZqCalDdr3WarmBoot = 0x00000000;
SDRAM[0].EmcZcalWarmBootWait = 0x00000001;
SDRAM[0].EmcMrsWarmBootEnable = 0x00000001;
SDRAM[0].EmcMrsResetDllWait = 0x00000000;
SDRAM[0].EmcMrsExtra = 0x80001d71;
SDRAM[0].EmcWarmBootMrsExtra = 0x80100002;
SDRAM[0].EmcEmrsDdr2DllEnable = 0x00000000;
SDRAM[0].EmcMrsDdr2DllReset = 0x00000000;
SDRAM[0].EmcEmrsDdr2OcdCalib = 0x00000000;
SDRAM[0].EmcDdr2Wait = 0x00000000;
SDRAM[0].EmcClkenOverride = 0x00000000;
SDRAM[0].McDisExtraSnapLevels = 0x00000000;
SDRAM[0].EmcExtraRefreshNum = 0x00000002;
SDRAM[0].EmcClkenOverrideAllWarmBoot = 0x00000000;
SDRAM[0].McClkenOverrideAllWarmBoot = 0x00000000;
SDRAM[0].EmcCfgDigDllPeriodWarmBoot = 0x00000003;
SDRAM[0].PmcVddpSel = 0x00000002;
SDRAM[0].PmcVddpSelWait = 0x00000002;
SDRAM[0].PmcDdrPwr = 0x00000003;
SDRAM[0].PmcDdrCfg = 0x00002002;
SDRAM[0].PmcIoDpd3Req = 0x4fff2f97;
SDRAM[0].PmcIoDpd3ReqWait = 0x00000000;
SDRAM[0].PmcRegShort = 0x00000000;
SDRAM[0].PmcNoIoPower = 0x00000000;
SDRAM[0].PmcPorDpdCtrlWait = 0x00000000;
SDRAM[0].EmcXm2CmdPadCtrl = 0x100002a0;
SDRAM[0].EmcXm2CmdPadCtrl2 = 0x770c0000;
SDRAM[0].EmcXm2CmdPadCtrl3 = 0x050c0000;
SDRAM[0].EmcXm2CmdPadCtrl4 = 0x00000000;
SDRAM[0].EmcXm2CmdPadCtrl5 = 0x00111111;
SDRAM[0].EmcXm2DqsPadCtrl = 0x770c1414;
SDRAM[0].EmcXm2DqsPadCtrl2 = 0x0020013d;
SDRAM[0].EmcXm2DqsPadCtrl3 = 0x61861820;
SDRAM[0].EmcXm2DqsPadCtrl4 = 0x00514514;
SDRAM[0].EmcXm2DqsPadCtrl5 = 0x00514514;
SDRAM[0].EmcXm2DqsPadCtrl6 = 0x61861800;
SDRAM[0].EmcXm2DqPadCtrl = 0x770c2990;
SDRAM[0].EmcXm2DqPadCtrl2 = 0x00000000;
SDRAM[0].EmcXm2DqPadCtrl3 = 0x00000000;
SDRAM[0].EmcXm2ClkPadCtrl = 0x77ffc085;
SDRAM[0].EmcXm2ClkPadCtrl2 = 0x00000707;
SDRAM[0].EmcXm2CompPadCtrl = 0x81f1f108;
SDRAM[0].EmcXm2VttGenPadCtrl = 0x07070004;
SDRAM[0].EmcXm2VttGenPadCtrl2 = 0x00000000;
SDRAM[0].EmcXm2VttGenPadCtrl3 = 0x017fffff;
SDRAM[0].EmcAcpdControl = 0x00000000;
SDRAM[0].EmcSwizzleRank0ByteCfg = 0x00003120;
SDRAM[0].EmcSwizzleRank0Byte0 = 0x25143067;
SDRAM[0].EmcSwizzleRank0Byte1 = 0x45367102;
SDRAM[0].EmcSwizzleRank0Byte2 = 0x47106253;
SDRAM[0].EmcSwizzleRank0Byte3 = 0x04362175;
SDRAM[0].EmcSwizzleRank1ByteCfg = 0x00003120;
SDRAM[0].EmcSwizzleRank1Byte0 = 0x71546032;
SDRAM[0].EmcSwizzleRank1Byte1 = 0x35104276;
SDRAM[0].EmcSwizzleRank1Byte2 = 0x27043615;
SDRAM[0].EmcSwizzleRank1Byte3 = 0x72306145;
SDRAM[0].EmcDsrVttgenDrv = 0x0505003f;
SDRAM[0].EmcTxdsrvttgen = 0x00000000;
SDRAM[0].EmcBgbiasCtl0 = 0x00000000;
SDRAM[0].McEmemAdrCfg = 0x00000000;
SDRAM[0].McEmemAdrCfgDev0 = 0x00080303;
SDRAM[0].McEmemAdrCfgDev1 = 0x00080303;
SDRAM[0].McEmemAdrCfgBankMask0 = 0x00001248;
SDRAM[0].McEmemAdrCfgBankMask1 = 0x00002490;
SDRAM[0].McEmemAdrCfgBankMask2 = 0x00000920;
SDRAM[0].McEmemAdrCfgBankSwizzle3 = 0x00000001;
SDRAM[0].McEmemCfg = 0x00000800;
SDRAM[0].McEmemArbCfg = 0x0e00000b;
SDRAM[0].McEmemArbOutstandingReq = 0x80000040;
SDRAM[0].McEmemArbTimingRcd = 0x00000004;
SDRAM[0].McEmemArbTimingRp = 0x00000005;
SDRAM[0].McEmemArbTimingRc = 0x00000013;
SDRAM[0].McEmemArbTimingRas = 0x0000000c;
SDRAM[0].McEmemArbTimingFaw = 0x0000000f;
SDRAM[0].McEmemArbTimingRrd = 0x00000002;
SDRAM[0].McEmemArbTimingRap2Pre = 0x00000003;
SDRAM[0].McEmemArbTimingWap2Pre = 0x0000000c;
SDRAM[0].McEmemArbTimingR2R = 0x00000002;
SDRAM[0].McEmemArbTimingW2W = 0x00000002;
SDRAM[0].McEmemArbTimingR2W = 0x00000005;
SDRAM[0].McEmemArbTimingW2R = 0x00000008;
SDRAM[0].McEmemArbDaTurns = 0x08050202;
SDRAM[0].McEmemArbDaCovers = 0x00170e13;
SDRAM[0].McEmemArbMisc0 = 0x736c2414;
SDRAM[0].McEmemArbMisc1 = 0x70000f02;
SDRAM[0].McEmemArbRing1Throttle = 0x001f0000;
SDRAM[0].McEmemArbOverride = 0x10000000;
SDRAM[0].McEmemArbOverride1 = 0x00000000;
SDRAM[0].McEmemArbRsv = 0xff00ff00;
SDRAM[0].McClkenOverride = 0x00000000;
SDRAM[0].McStatControl = 0x00000000;
SDRAM[0].McDisplaySnapRing = 0x00000003;
SDRAM[0].McVideoProtectBom = 0xfff00000;
SDRAM[0].McVideoProtectBomAdrHi = 0x00000000;
SDRAM[0].McVideoProtectSizeMb = 0x00000000;
SDRAM[0].McVideoProtectVprOverride = 0xe4bac743;
SDRAM[0].McVideoProtectVprOverride1 = 0x00000013;
SDRAM[0].McVideoProtectGpuOverride0 = 0x00000000;
SDRAM[0].McVideoProtectGpuOverride1 = 0x00000000;
SDRAM[0].McSecCarveoutBom = 0xfff00000;
SDRAM[0].McSecCarveoutAdrHi = 0x00000000;
SDRAM[0].McSecCarveoutSizeMb = 0x00000000;
SDRAM[0].McVideoProtectWriteAccess = 0x00000000;
SDRAM[0].McSecCarveoutProtectWriteAccess = 0x00000000;
SDRAM[0].EmcCaTrainingEnable = 0x00000000;
SDRAM[0].EmcCaTrainingTimingCntl1 = 0x1f7df7df;
SDRAM[0].EmcCaTrainingTimingCntl2 = 0x0000001f;
SDRAM[0].SwizzleRankByteEncode = 0x0000006f;
SDRAM[0].BootRomPatchControl = 0x00000000;
SDRAM[0].BootRomPatchData = 0x00000000;
SDRAM[0].McMtsCarveoutBom = 0xfff00000;
SDRAM[0].McMtsCarveoutAdrHi = 0x00000000;
SDRAM[0].McMtsCarveoutSizeMb = 0x00000000;
SDRAM[0].McMtsCarveoutRegCtrl = 0x00000000;
#@ MC_MLL_MPCORER_PTSA_RATE {0x7001944c} = 0x00000013;
#@ MC_PTSA_GRANT_DECREMENT {0x70019960} = 0x0000017c;
#@ MC_LATENCY_ALLOWANCE_XUSB_0 {0x7001937c} = 0x00810038;
#@ MC_LATENCY_ALLOWANCE_XUSB_1 {0x70019380} = 0x00810038;
#@ MC_LATENCY_ALLOWANCE_TSEC_0 {0x70019390} = 0x0081003c;
#@ MC_LATENCY_ALLOWANCE_SDMMCA_0 {0x700193b8} = 0x00810090;
#@ MC_LATENCY_ALLOWANCE_SDMMCAA_0 {0x700193bc} = 0x00810041;
#@ MC_LATENCY_ALLOWANCE_SDMMC_0 {0x700193c0} = 0x00810090;
#@ MC_LATENCY_ALLOWANCE_SDMMCAB_0 {0x700193c4} = 0x00810041;
#@ MC_LATENCY_ALLOWANCE_PPCS_0 {0x70019344} = 0x00270049;
#@ MC_LATENCY_ALLOWANCE_PPCS_1 {0x70019348} = 0x00810080;
#@ MC_LATENCY_ALLOWANCE_MPCORE_0 {0x70019320} = 0x00810004;
#@ MC_LATENCY_ALLOWANCE_MPCORELP_0 {0x70019324} = 0x00810004;
#@ MC_LATENCY_ALLOWANCE_HC_0 {0x70019310} = 0x00080016;
#@ MC_LATENCY_ALLOWANCE_HC_1 {0x70019314} = 0x00000081;
#@ MC_LATENCY_ALLOWANCE_AVPC_0 {0x700192e4} = 0x00810004;
#@ MC_LATENCY_ALLOWANCE_GPU_0 {0x700193ac} = 0x00810019;
#@ MC_LATENCY_ALLOWANCE_MSENC_0 {0x70019328} = 0x00810018;
#@ MC_LATENCY_ALLOWANCE_HDA_0 {0x70019318} = 0x00810024;
#@ MC_LATENCY_ALLOWANCE_VIC_0 {0x70019394} = 0x0081001c;
#@ MC_LATENCY_ALLOWANCE_VI2_0 {0x70019398} = 0x00000081;
#@ MC_LATENCY_ALLOWANCE_ISP2_0 {0x70019370} = 0x00000036;
#@ MC_LATENCY_ALLOWANCE_ISP2_1 {0x70019374} = 0x00810081;
#@ MC_LATENCY_ALLOWANCE_ISP2B_0 {0x70019384} = 0x00000036;
#@ MC_LATENCY_ALLOWANCE_ISP2B_1 {0x70019388} = 0x00810081;
#@ MC_LATENCY_ALLOWANCE_VDE_0 {0x70019354} = 0x00d400ff;
#@ MC_LATENCY_ALLOWANCE_VDE_1 {0x70019358} = 0x00510029;
#@ MC_LATENCY_ALLOWANCE_VDE_2 {0x7001935c} = 0x00810081;
#@ MC_LATENCY_ALLOWANCE_VDE_3 {0x70019360} = 0x00810081;
#@ MC_LATENCY_ALLOWANCE_SATA_0 {0x70019350} = 0x00810065;
#@ MC_LATENCY_ALLOWANCE_AFI_0 {0x700192e0} = 0x0081001c;

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src/mainboard/google/nyan_big/bct/sdram-924.cfg
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@ -1,346 +0,0 @@
# CFG Version 11
# Do not edit. Generated by gen_sdram_cfg V5.0.1. Command:
# gen_sdram_cfg -i ddr3_256Mx16x4_H5TC4G63AFR_RDA.par 1.082 -dram_board_cfg 10 -fly_by_time_ps 1650
# -b PM358/PM358_924MHz_emc_reg.txt -o PM358_Hynix_2GB_H5TC4G63AFR_RDA_924Mhz.cfg
# Parameter file: ddr3_256Mx16x4_H5TC4G63AFR_RDA.par, tck = 1.08 ns (924.21 MHz)
# bkv file: PM358/PM358_924MHz_emc_reg.txt
SDRAM[0].MemoryType = NvBootMemoryType_Ddr3;
SDRAM[0].PllMInputDivider = 0x00000001;
SDRAM[0].PllMFeedbackDivider = 0x0000004d;
SDRAM[0].PllMStableTime = 0x0000012c;
SDRAM[0].PllMSetupControl = 0x00000000;
SDRAM[0].PllMSelectDiv2 = 0x00000000;
SDRAM[0].PllMPDLshiftPh45 = 0x00000001;
SDRAM[0].PllMPDLshiftPh90 = 0x00000001;
SDRAM[0].PllMPDLshiftPh135 = 0x00000001;
SDRAM[0].PllMKCP = 0x00000000;
SDRAM[0].PllMKVCO = 0x00000000;
SDRAM[0].EmcBctSpare0 = 0x00000000;
SDRAM[0].EmcBctSpare1 = 0x00000000;
SDRAM[0].EmcBctSpare2 = 0x00000000;
SDRAM[0].EmcBctSpare3 = 0x00000000;
SDRAM[0].EmcBctSpare4 = 0x00000000;
SDRAM[0].EmcBctSpare5 = 0x00000000;
SDRAM[0].EmcBctSpare6 = 0x00000000;
SDRAM[0].EmcBctSpare7 = 0x00000000;
SDRAM[0].EmcBctSpare8 = 0x00000000;
SDRAM[0].EmcBctSpare9 = 0x00000000;
SDRAM[0].EmcBctSpare10 = 0x00000000;
SDRAM[0].EmcBctSpare11 = 0x00000000;
SDRAM[0].EmcClockSource = 0x80000000;
SDRAM[0].EmcAutoCalInterval = 0x001fffff;
SDRAM[0].EmcAutoCalConfig = 0xa1430404;
SDRAM[0].EmcAutoCalConfig2 = 0x00000000;
SDRAM[0].EmcAutoCalConfig3 = 0x00000000;
SDRAM[0].EmcAutoCalWait = 0x00000190;
SDRAM[0].EmcAdrCfg = 0x00000000;
SDRAM[0].EmcPinProgramWait = 0x00000001;
SDRAM[0].EmcPinExtraWait = 0x00000000;
SDRAM[0].EmcTimingControlWait = 0x00000000;
SDRAM[0].EmcRc = 0x0000002b;
SDRAM[0].EmcRfc = 0x000000ef;
SDRAM[0].EmcRfcSlr = 0x00000000;
SDRAM[0].EmcRas = 0x0000001e;
SDRAM[0].EmcRp = 0x0000000b;
SDRAM[0].EmcR2r = 0x00000000;
SDRAM[0].EmcW2w = 0x00000000;
SDRAM[0].EmcR2w = 0x00000008;
SDRAM[0].EmcW2r = 0x0000000f;
SDRAM[0].EmcR2p = 0x00000005;
SDRAM[0].EmcW2p = 0x00000016;
SDRAM[0].EmcRdRcd = 0x0000000b;
SDRAM[0].EmcWrRcd = 0x0000000b;
SDRAM[0].EmcRrd = 0x00000004;
SDRAM[0].EmcRext = 0x00000002;
SDRAM[0].EmcWext = 0x00000000;
SDRAM[0].EmcWdv = 0x00000006;
SDRAM[0].EmcWdvMask = 0x00000006;
SDRAM[0].EmcQUse = 0x0000000c;
SDRAM[0].EmcQuseWidth = 0x00000002;
SDRAM[0].EmcIbdly = 0x00000000;
SDRAM[0].EmcEInput = 0x00000002;
SDRAM[0].EmcEInputDuration = 0x0000000e;
SDRAM[0].EmcPutermExtra = 0x000a0000;
SDRAM[0].EmcPutermWidth = 0x00000004;
SDRAM[0].EmcPutermAdj = 0x00000000;
SDRAM[0].EmcCdbCntl1 = 0x00000000;
SDRAM[0].EmcCdbCntl2 = 0x00000000;
SDRAM[0].EmcCdbCntl3 = 0x00000000;
SDRAM[0].EmcQRst = 0x00000001;
SDRAM[0].EmcQSafe = 0x00000015;
SDRAM[0].EmcRdv = 0x0000001b;
SDRAM[0].EmcRdvMask = 0x0000001d;
SDRAM[0].EmcQpop = 0x00000010;
SDRAM[0].EmcCtt = 0x00000000;
SDRAM[0].EmcCttDuration = 0x00000004;
SDRAM[0].EmcRefresh = 0x00001be9;
SDRAM[0].EmcBurstRefreshNum = 0x00000000;
SDRAM[0].EmcPreRefreshReqCnt = 0x000006fa;
SDRAM[0].EmcPdEx2Wr = 0x00000004;
SDRAM[0].EmcPdEx2Rd = 0x00000015;
SDRAM[0].EmcPChg2Pden = 0x00000001;
SDRAM[0].EmcAct2Pden = 0x00000000;
SDRAM[0].EmcAr2Pden = 0x000000e6;
SDRAM[0].EmcRw2Pden = 0x0000001b;
SDRAM[0].EmcTxsr = 0x000000fa;
SDRAM[0].EmcTxsrDll = 0x00000200;
SDRAM[0].EmcTcke = 0x00000006;
SDRAM[0].EmcTckesr = 0x00000007;
SDRAM[0].EmcTpd = 0x00000006;
SDRAM[0].EmcTfaw = 0x00000022;
SDRAM[0].EmcTrpab = 0x00000000;
SDRAM[0].EmcTClkStable = 0x0000000a;
SDRAM[0].EmcTClkStop = 0x0000000a;
SDRAM[0].EmcTRefBw = 0x00001c29;
SDRAM[0].EmcFbioCfg5 = 0x104ab898;
SDRAM[0].EmcFbioCfg6 = 0x00000002;
SDRAM[0].EmcFbioSpare = 0x00000000;
SDRAM[0].EmcCfgRsv = 0xff00ff00;
SDRAM[0].EmcMrs = 0x80000f15;
SDRAM[0].EmcEmrs = 0x80100002;
SDRAM[0].EmcEmrs2 = 0x80200020;
SDRAM[0].EmcEmrs3 = 0x80300000;
SDRAM[0].EmcMrw1 = 0x00000000;
SDRAM[0].EmcMrw2 = 0x00000000;
SDRAM[0].EmcMrw3 = 0x00000000;
SDRAM[0].EmcMrw4 = 0x00000000;
SDRAM[0].EmcMrwExtra = 0x00000000;
SDRAM[0].EmcWarmBootMrwExtra = 0x00000000;
SDRAM[0].EmcWarmBootExtraModeRegWriteEnable = 0x00000000;
SDRAM[0].EmcExtraModeRegWriteEnable = 0x00000000;
SDRAM[0].EmcMrwResetCommand = 0x00000000;
SDRAM[0].EmcMrwResetNInitWait = 0x00000000;
SDRAM[0].EmcMrsWaitCnt = 0x00ce000e;
SDRAM[0].EmcMrsWaitCnt2 = 0x00ce000e;
SDRAM[0].EmcCfg = 0x73300000;
SDRAM[0].EmcCfg2 = 0x000008a5;
SDRAM[0].EmcCfgPipe = 0x00000000;
SDRAM[0].EmcDbg = 0x01000c00;
SDRAM[0].EmcCmdQ = 0x10004408;
SDRAM[0].EmcMc2EmcQ = 0x06000404;
SDRAM[0].EmcDynSelfRefControl = 0x800037ed;
SDRAM[0].AhbArbitrationXbarCtrlMemInitDone = 0x00000001;
SDRAM[0].EmcCfgDigDll = 0xe00401b1;
SDRAM[0].EmcCfgDigDllPeriod = 0x00008000;
SDRAM[0].EmcDevSelect = 0x00000002;
SDRAM[0].EmcSelDpdCtrl = 0x00040000;
SDRAM[0].EmcDllXformDqs0 = 0x00000005;
SDRAM[0].EmcDllXformDqs1 = 0x00000005;
SDRAM[0].EmcDllXformDqs2 = 0x00000005;
SDRAM[0].EmcDllXformDqs3 = 0x00000005;
SDRAM[0].EmcDllXformDqs4 = 0x00000005;
SDRAM[0].EmcDllXformDqs5 = 0x00000005;
SDRAM[0].EmcDllXformDqs6 = 0x00000005;
SDRAM[0].EmcDllXformDqs7 = 0x00000005;
SDRAM[0].EmcDllXformDqs8 = 0x00000005;
SDRAM[0].EmcDllXformDqs9 = 0x00000005;
SDRAM[0].EmcDllXformDqs10 = 0x00000005;
SDRAM[0].EmcDllXformDqs11 = 0x00000005;
SDRAM[0].EmcDllXformDqs12 = 0x00000005;
SDRAM[0].EmcDllXformDqs13 = 0x00000005;
SDRAM[0].EmcDllXformDqs14 = 0x00000005;
SDRAM[0].EmcDllXformDqs15 = 0x00000005;
SDRAM[0].EmcDllXformQUse0 = 0x00000000;
SDRAM[0].EmcDllXformQUse1 = 0x00000000;
SDRAM[0].EmcDllXformQUse2 = 0x00000000;
SDRAM[0].EmcDllXformQUse3 = 0x00000000;
SDRAM[0].EmcDllXformQUse4 = 0x00000000;
SDRAM[0].EmcDllXformQUse5 = 0x00000000;
SDRAM[0].EmcDllXformQUse6 = 0x00000000;
SDRAM[0].EmcDllXformQUse7 = 0x00000000;
SDRAM[0].EmcDllXformAddr0 = 0x0000400e;
SDRAM[0].EmcDllXformAddr1 = 0x0000400e;
SDRAM[0].EmcDllXformAddr2 = 0x00000000;
SDRAM[0].EmcDllXformAddr3 = 0x0000400e;
SDRAM[0].EmcDllXformAddr4 = 0x0000400e;
SDRAM[0].EmcDllXformAddr5 = 0x00000000;
SDRAM[0].EmcDllXformQUse8 = 0x00000000;
SDRAM[0].EmcDllXformQUse9 = 0x00000000;
SDRAM[0].EmcDllXformQUse10 = 0x00000000;
SDRAM[0].EmcDllXformQUse11 = 0x00000000;
SDRAM[0].EmcDllXformQUse12 = 0x00000000;
SDRAM[0].EmcDllXformQUse13 = 0x00000000;
SDRAM[0].EmcDllXformQUse14 = 0x00000000;
SDRAM[0].EmcDllXformQUse15 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs0 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs1 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs2 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs3 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs4 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs5 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs6 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs7 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs8 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs9 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs10 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs11 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs12 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs13 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs14 = 0x00000000;
SDRAM[0].EmcDliTrimTxDqs15 = 0x00000000;
SDRAM[0].EmcDllXformDq0 = 0x00000006;
SDRAM[0].EmcDllXformDq1 = 0x00000006;
SDRAM[0].EmcDllXformDq2 = 0x00000006;
SDRAM[0].EmcDllXformDq3 = 0x00000006;
SDRAM[0].EmcDllXformDq4 = 0x00000006;
SDRAM[0].EmcDllXformDq5 = 0x00000006;
SDRAM[0].EmcDllXformDq6 = 0x00000006;
SDRAM[0].EmcDllXformDq7 = 0x00000006;
SDRAM[0].WarmBootWait = 0x00000002;
SDRAM[0].EmcCttTermCtrl = 0x00000802;
SDRAM[0].EmcOdtWrite = 0x00000000;
SDRAM[0].EmcOdtRead = 0x00000000;
SDRAM[0].EmcZcalInterval = 0x00020000;
SDRAM[0].EmcZcalWaitCnt = 0x0000004c;
SDRAM[0].EmcZcalMrwCmd = 0x80000000;
SDRAM[0].EmcMrsResetDll = 0x00000000;
SDRAM[0].EmcZcalInitDev0 = 0x80000011;
SDRAM[0].EmcZcalInitDev1 = 0x00000000;
SDRAM[0].EmcZcalInitWait = 0x00000001;
SDRAM[0].EmcZcalWarmColdBootEnables = 0x00000003;
SDRAM[0].EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab;
SDRAM[0].EmcZqCalDdr3WarmBoot = 0x00000000;
SDRAM[0].EmcZcalWarmBootWait = 0x00000001;
SDRAM[0].EmcMrsWarmBootEnable = 0x00000001;
SDRAM[0].EmcMrsResetDllWait = 0x00000000;
SDRAM[0].EmcMrsExtra = 0x80000f15;
SDRAM[0].EmcWarmBootMrsExtra = 0x80100002;
SDRAM[0].EmcEmrsDdr2DllEnable = 0x00000000;
SDRAM[0].EmcMrsDdr2DllReset = 0x00000000;
SDRAM[0].EmcEmrsDdr2OcdCalib = 0x00000000;
SDRAM[0].EmcDdr2Wait = 0x00000000;
SDRAM[0].EmcClkenOverride = 0x00000000;
SDRAM[0].McDisExtraSnapLevels = 0x00000000;
SDRAM[0].EmcExtraRefreshNum = 0x00000002;
SDRAM[0].EmcClkenOverrideAllWarmBoot = 0x00000000;
SDRAM[0].McClkenOverrideAllWarmBoot = 0x00000000;
SDRAM[0].EmcCfgDigDllPeriodWarmBoot = 0x00000003;
SDRAM[0].PmcVddpSel = 0x00000002;
SDRAM[0].PmcVddpSelWait = 0x00000002;
SDRAM[0].PmcDdrPwr = 0x00000003;
SDRAM[0].PmcDdrCfg = 0x00002002;
SDRAM[0].PmcIoDpd3Req = 0x4fff2f97;
SDRAM[0].PmcIoDpd3ReqWait = 0x00000000;
SDRAM[0].PmcRegShort = 0x00000000;
SDRAM[0].PmcNoIoPower = 0x00000000;
SDRAM[0].PmcPorDpdCtrlWait = 0x00000000;
SDRAM[0].EmcXm2CmdPadCtrl = 0x100002a0;
SDRAM[0].EmcXm2CmdPadCtrl2 = 0x770c0000;
SDRAM[0].EmcXm2CmdPadCtrl3 = 0x050c0000;
SDRAM[0].EmcXm2CmdPadCtrl4 = 0x00000000;
SDRAM[0].EmcXm2CmdPadCtrl5 = 0x00111111;
SDRAM[0].EmcXm2DqsPadCtrl = 0x770c1414;
SDRAM[0].EmcXm2DqsPadCtrl2 = 0x0020013d;
SDRAM[0].EmcXm2DqsPadCtrl3 = 0x55555520;
SDRAM[0].EmcXm2DqsPadCtrl4 = 0x003cf3cf;
SDRAM[0].EmcXm2DqsPadCtrl5 = 0x003cf3cf;
SDRAM[0].EmcXm2DqsPadCtrl6 = 0x55555500;
SDRAM[0].EmcXm2DqPadCtrl = 0x770c2990;
SDRAM[0].EmcXm2DqPadCtrl2 = 0x00000000;
SDRAM[0].EmcXm2DqPadCtrl3 = 0x00000000;
SDRAM[0].EmcXm2ClkPadCtrl = 0x77ffc085;
SDRAM[0].EmcXm2ClkPadCtrl2 = 0x00000303;
SDRAM[0].EmcXm2CompPadCtrl = 0x81f1f108;
SDRAM[0].EmcXm2VttGenPadCtrl = 0x07070004;
SDRAM[0].EmcXm2VttGenPadCtrl2 = 0x00000000;
SDRAM[0].EmcXm2VttGenPadCtrl3 = 0x016eeeee;
SDRAM[0].EmcAcpdControl = 0x00000000;
SDRAM[0].EmcSwizzleRank0ByteCfg = 0x00003120;
SDRAM[0].EmcSwizzleRank0Byte0 = 0x25143067;
SDRAM[0].EmcSwizzleRank0Byte1 = 0x45367102;
SDRAM[0].EmcSwizzleRank0Byte2 = 0x47106253;
SDRAM[0].EmcSwizzleRank0Byte3 = 0x04362175;
SDRAM[0].EmcSwizzleRank1ByteCfg = 0x00003120;
SDRAM[0].EmcSwizzleRank1Byte0 = 0x71546032;
SDRAM[0].EmcSwizzleRank1Byte1 = 0x35104276;
SDRAM[0].EmcSwizzleRank1Byte2 = 0x27043615;
SDRAM[0].EmcSwizzleRank1Byte3 = 0x72306145;
SDRAM[0].EmcDsrVttgenDrv = 0x0606003f;
SDRAM[0].EmcTxdsrvttgen = 0x00000000;
SDRAM[0].EmcBgbiasCtl0 = 0x00000000;
SDRAM[0].McEmemAdrCfg = 0x00000000;
SDRAM[0].McEmemAdrCfgDev0 = 0x00080303;
SDRAM[0].McEmemAdrCfgDev1 = 0x00080303;
SDRAM[0].McEmemAdrCfgBankMask0 = 0x00001248;
SDRAM[0].McEmemAdrCfgBankMask1 = 0x00002490;
SDRAM[0].McEmemAdrCfgBankMask2 = 0x00000920;
SDRAM[0].McEmemAdrCfgBankSwizzle3 = 0x00000001;
SDRAM[0].McEmemCfg = 0x00000800;
SDRAM[0].McEmemArbCfg = 0x0e00000d;
SDRAM[0].McEmemArbOutstandingReq = 0x80000040;
SDRAM[0].McEmemArbTimingRcd = 0x00000005;
SDRAM[0].McEmemArbTimingRp = 0x00000006;
SDRAM[0].McEmemArbTimingRc = 0x00000016;
SDRAM[0].McEmemArbTimingRas = 0x0000000e;
SDRAM[0].McEmemArbTimingFaw = 0x00000011;
SDRAM[0].McEmemArbTimingRrd = 0x00000002;
SDRAM[0].McEmemArbTimingRap2Pre = 0x00000004;
SDRAM[0].McEmemArbTimingWap2Pre = 0x0000000e;
SDRAM[0].McEmemArbTimingR2R = 0x00000002;
SDRAM[0].McEmemArbTimingW2W = 0x00000002;
SDRAM[0].McEmemArbTimingR2W = 0x00000006;
SDRAM[0].McEmemArbTimingW2R = 0x00000009;
SDRAM[0].McEmemArbDaTurns = 0x09060202;
SDRAM[0].McEmemArbDaCovers = 0x001a1016;
SDRAM[0].McEmemArbMisc0 = 0x734e2a17;
SDRAM[0].McEmemArbMisc1 = 0x70000f02;
SDRAM[0].McEmemArbRing1Throttle = 0x001f0000;
SDRAM[0].McEmemArbOverride = 0x10000000;
SDRAM[0].McEmemArbOverride1 = 0x00000000;
SDRAM[0].McEmemArbRsv = 0xff00ff00;
SDRAM[0].McClkenOverride = 0x00000000;
SDRAM[0].McStatControl = 0x00000000;
SDRAM[0].McDisplaySnapRing = 0x00000003;
SDRAM[0].McVideoProtectBom = 0xfff00000;
SDRAM[0].McVideoProtectBomAdrHi = 0x00000000;
SDRAM[0].McVideoProtectSizeMb = 0x00000000;
SDRAM[0].McVideoProtectVprOverride = 0xe4bac743;
SDRAM[0].McVideoProtectVprOverride1 = 0x00000013;
SDRAM[0].McVideoProtectGpuOverride0 = 0x00000000;
SDRAM[0].McVideoProtectGpuOverride1 = 0x00000000;
SDRAM[0].McSecCarveoutBom = 0xfff00000;
SDRAM[0].McSecCarveoutAdrHi = 0x00000000;
SDRAM[0].McSecCarveoutSizeMb = 0x00000000;
SDRAM[0].McVideoProtectWriteAccess = 0x00000000;
SDRAM[0].McSecCarveoutProtectWriteAccess = 0x00000000;
SDRAM[0].EmcCaTrainingEnable = 0x00000000;
SDRAM[0].EmcCaTrainingTimingCntl1 = 0x1f7df7df;
SDRAM[0].EmcCaTrainingTimingCntl2 = 0x0000001f;
SDRAM[0].SwizzleRankByteEncode = 0x0000006f;
SDRAM[0].BootRomPatchControl = 0x00000000;
SDRAM[0].BootRomPatchData = 0x00000000;
SDRAM[0].McMtsCarveoutBom = 0xfff00000;
SDRAM[0].McMtsCarveoutAdrHi = 0x00000000;
SDRAM[0].McMtsCarveoutSizeMb = 0x00000000;
SDRAM[0].McMtsCarveoutRegCtrl = 0x00000000;
#@ MC_MLL_MPCORER_PTSA_RATE {0x7001944c} = 0x00000017;
#@ MC_PTSA_GRANT_DECREMENT {0x70019960} = 0x000001bb;
#@ MC_LATENCY_ALLOWANCE_XUSB_0 {0x7001937c} = 0x006e0038;
#@ MC_LATENCY_ALLOWANCE_XUSB_1 {0x70019380} = 0x006e0038;
#@ MC_LATENCY_ALLOWANCE_TSEC_0 {0x70019390} = 0x006e003c;
#@ MC_LATENCY_ALLOWANCE_SDMMCA_0 {0x700193b8} = 0x006e0090;
#@ MC_LATENCY_ALLOWANCE_SDMMCAA_0 {0x700193bc} = 0x006e0041;
#@ MC_LATENCY_ALLOWANCE_SDMMC_0 {0x700193c0} = 0x006e0090;
#@ MC_LATENCY_ALLOWANCE_SDMMCAB_0 {0x700193c4} = 0x006e0041;
#@ MC_LATENCY_ALLOWANCE_PPCS_0 {0x70019344} = 0x00270049;
#@ MC_LATENCY_ALLOWANCE_PPCS_1 {0x70019348} = 0x006e0080;
#@ MC_LATENCY_ALLOWANCE_MPCORE_0 {0x70019320} = 0x006e0004;
#@ MC_LATENCY_ALLOWANCE_MPCORELP_0 {0x70019324} = 0x006e0004;
#@ MC_LATENCY_ALLOWANCE_HC_0 {0x70019310} = 0x00080016;
#@ MC_LATENCY_ALLOWANCE_HC_1 {0x70019314} = 0x0000006e;
#@ MC_LATENCY_ALLOWANCE_AVPC_0 {0x700192e4} = 0x006e0004;
#@ MC_LATENCY_ALLOWANCE_GPU_0 {0x700193ac} = 0x006e0019;
#@ MC_LATENCY_ALLOWANCE_MSENC_0 {0x70019328} = 0x006e0018;
#@ MC_LATENCY_ALLOWANCE_HDA_0 {0x70019318} = 0x006e0024;
#@ MC_LATENCY_ALLOWANCE_VIC_0 {0x70019394} = 0x006e001b;
#@ MC_LATENCY_ALLOWANCE_VI2_0 {0x70019398} = 0x0000006e;
#@ MC_LATENCY_ALLOWANCE_ISP2_0 {0x70019370} = 0x00000036;
#@ MC_LATENCY_ALLOWANCE_ISP2_1 {0x70019374} = 0x006e006e;
#@ MC_LATENCY_ALLOWANCE_ISP2B_0 {0x70019384} = 0x00000036;
#@ MC_LATENCY_ALLOWANCE_ISP2B_1 {0x70019388} = 0x006e006e;
#@ MC_LATENCY_ALLOWANCE_VDE_0 {0x70019354} = 0x00d400ff;
#@ MC_LATENCY_ALLOWANCE_VDE_1 {0x70019358} = 0x00510029;
#@ MC_LATENCY_ALLOWANCE_VDE_2 {0x7001935c} = 0x006e006e;
#@ MC_LATENCY_ALLOWANCE_VDE_3 {0x70019360} = 0x006e006e;
#@ MC_LATENCY_ALLOWANCE_SATA_0 {0x70019350} = 0x006e0065;
#@ MC_LATENCY_ALLOWANCE_AFI_0 {0x700192e0} = 0x006e001c;

311
src/mainboard/google/nyan_big/bct/sdram-hynix-2GB-204.inc Normal file
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{ /* generated from sdram-0001-204-2GB.cfg; do not edit. */
.MemoryType = NvBootMemoryType_Ddr3,
.PllMInputDivider = 0x00000001,
.PllMFeedbackDivider = 0x00000022,
.PllMStableTime = 0x0000012c,
.PllMSetupControl = 0x00000000,
.PllMSelectDiv2 = 0x00000000,
.PllMPDLshiftPh45 = 0x00000001,
.PllMPDLshiftPh90 = 0x00000001,
.PllMPDLshiftPh135 = 0x00000001,
.PllMKCP = 0x00000000,
.PllMKVCO = 0x00000000,
.EmcBctSpare0 = 0x00000000,
.EmcBctSpare1 = 0x00000000,
.EmcBctSpare2 = 0x00000000,
.EmcBctSpare3 = 0x00000000,
.EmcBctSpare4 = 0x00000000,
.EmcBctSpare5 = 0x00000000,
.EmcBctSpare6 = 0x00000000,
.EmcBctSpare7 = 0x00000000,
.EmcBctSpare8 = 0x00000000,
.EmcBctSpare9 = 0x00000000,
.EmcBctSpare10 = 0x00000000,
.EmcBctSpare11 = 0x00000000,
.EmcClockSource = 0x40000002,
.EmcAutoCalInterval = 0x001fffff,
.EmcAutoCalConfig = 0xa1430000,
.EmcAutoCalConfig2 = 0x00000000,
.EmcAutoCalConfig3 = 0x00000000,
.EmcAutoCalWait = 0x00000190,
.EmcAdrCfg = 0x00000000,
.EmcPinProgramWait = 0x00000001,
.EmcPinExtraWait = 0x00000000,
.EmcTimingControlWait = 0x00000000,
.EmcRc = 0x00000009,
.EmcRfc = 0x00000035,
.EmcRfcSlr = 0x00000000,
.EmcRas = 0x00000007,
.EmcRp = 0x00000002,
.EmcR2r = 0x00000000,
.EmcW2w = 0x00000000,
.EmcR2w = 0x00000005,
.EmcW2r = 0x0000000a,
.EmcR2p = 0x00000003,
.EmcW2p = 0x0000000b,
.EmcRdRcd = 0x00000002,
.EmcWrRcd = 0x00000002,
.EmcRrd = 0x00000003,
.EmcRext = 0x00000003,
.EmcWext = 0x00000000,
.EmcWdv = 0x00000005,
.EmcWdvMask = 0x00000005,
.EmcQUse = 0x00000006,
.EmcQuseWidth = 0x00000002,
.EmcIbdly = 0x00000000,
.EmcEInput = 0x00000004,
.EmcEInputDuration = 0x00000006,
.EmcPutermExtra = 0x00010000,
.EmcPutermWidth = 0x00000003,
.EmcPutermAdj = 0x00000000,
.EmcCdbCntl1 = 0x00000000,
.EmcCdbCntl2 = 0x00000000,
.EmcCdbCntl3 = 0x00000000,
.EmcQRst = 0x00000003,
.EmcQSafe = 0x0000000d,
.EmcRdv = 0x0000000f,
.EmcRdvMask = 0x00000011,
.EmcQpop = 0x0000000a,
.EmcCtt = 0x00000000,
.EmcCttDuration = 0x00000003,
.EmcRefresh = 0x00000607,
.EmcBurstRefreshNum = 0x00000000,
.EmcPreRefreshReqCnt = 0x00000181,
.EmcPdEx2Wr = 0x00000002,
.EmcPdEx2Rd = 0x00000002,
.EmcPChg2Pden = 0x00000001,
.EmcAct2Pden = 0x00000000,
.EmcAr2Pden = 0x00000032,
.EmcRw2Pden = 0x0000000f,
.EmcTxsr = 0x00000038,
.EmcTxsrDll = 0x00000038,
.EmcTcke = 0x00000004,
.EmcTckesr = 0x00000005,
.EmcTpd = 0x00000004,
.EmcTfaw = 0x00000007,
.EmcTrpab = 0x00000000,
.EmcTClkStable = 0x00000005,
.EmcTClkStop = 0x00000005,
.EmcTRefBw = 0x00000638,
.EmcFbioCfg5 = 0x106aa298,
.EmcFbioCfg6 = 0x00000000,
.EmcFbioSpare = 0x00000000,
.EmcCfgRsv = 0xff00ff00,
.EmcMrs = 0x80001221,
.EmcEmrs = 0x80100003,
.EmcEmrs2 = 0x80200008,
.EmcEmrs3 = 0x80300000,
.EmcMrw1 = 0x00000000,
.EmcMrw2 = 0x00000000,
.EmcMrw3 = 0x00000000,
.EmcMrw4 = 0x00000000,
.EmcMrwExtra = 0x00000000,
.EmcWarmBootMrwExtra = 0x00000000,
.EmcWarmBootExtraModeRegWriteEnable = 0x00000000,
.EmcExtraModeRegWriteEnable = 0x00000000,
.EmcMrwResetCommand = 0x00000000,
.EmcMrwResetNInitWait = 0x00000000,
.EmcMrsWaitCnt = 0x000c000c,
.EmcMrsWaitCnt2 = 0x000c000c,
.EmcCfg = 0x73240000,
.EmcCfg2 = 0x0000088d,
.EmcCfgPipe = 0x0000d2b3,
.EmcDbg = 0x01000c00,
.EmcCmdQ = 0x10004408,
.EmcMc2EmcQ = 0x06000404,
.EmcDynSelfRefControl = 0x80000d22,
.AhbArbitrationXbarCtrlMemInitDone = 0x00000001,
.EmcCfgDigDll = 0x002c00a0,
.EmcCfgDigDllPeriod = 0x00008000,
.EmcDevSelect = 0x00000002,
.EmcSelDpdCtrl = 0x00040008,
.EmcDllXformDqs0 = 0x00064000,
.EmcDllXformDqs1 = 0x00064000,
.EmcDllXformDqs2 = 0x00064000,
.EmcDllXformDqs3 = 0x00064000,
.EmcDllXformDqs4 = 0x00064000,
.EmcDllXformDqs5 = 0x00064000,
.EmcDllXformDqs6 = 0x00064000,
.EmcDllXformDqs7 = 0x00064000,
.EmcDllXformDqs8 = 0x00064000,
.EmcDllXformDqs9 = 0x00064000,
.EmcDllXformDqs10 = 0x00064000,
.EmcDllXformDqs11 = 0x00064000,
.EmcDllXformDqs12 = 0x00064000,
.EmcDllXformDqs13 = 0x00064000,
.EmcDllXformDqs14 = 0x00064000,
.EmcDllXformDqs15 = 0x00064000,
.EmcDllXformQUse0 = 0x00000000,
.EmcDllXformQUse1 = 0x00000000,
.EmcDllXformQUse2 = 0x00000000,
.EmcDllXformQUse3 = 0x00000000,
.EmcDllXformQUse4 = 0x00000000,
.EmcDllXformQUse5 = 0x00000000,
.EmcDllXformQUse6 = 0x00000000,
.EmcDllXformQUse7 = 0x00000000,
.EmcDllXformAddr0 = 0x00000000,
.EmcDllXformAddr1 = 0x00000000,
.EmcDllXformAddr2 = 0x00004000,
.EmcDllXformAddr3 = 0x00000000,
.EmcDllXformAddr4 = 0x00000000,
.EmcDllXformAddr5 = 0x00004000,
.EmcDllXformQUse8 = 0x00000000,
.EmcDllXformQUse9 = 0x00000000,
.EmcDllXformQUse10 = 0x00000000,
.EmcDllXformQUse11 = 0x00000000,
.EmcDllXformQUse12 = 0x00000000,
.EmcDllXformQUse13 = 0x00000000,
.EmcDllXformQUse14 = 0x00000000,
.EmcDllXformQUse15 = 0x00000000,
.EmcDliTrimTxDqs0 = 0x00000000,
.EmcDliTrimTxDqs1 = 0x00000000,
.EmcDliTrimTxDqs2 = 0x00000000,
.EmcDliTrimTxDqs3 = 0x00000000,
.EmcDliTrimTxDqs4 = 0x00000000,
.EmcDliTrimTxDqs5 = 0x00000000,
.EmcDliTrimTxDqs6 = 0x00000000,
.EmcDliTrimTxDqs7 = 0x00000000,
.EmcDliTrimTxDqs8 = 0x00000000,
.EmcDliTrimTxDqs9 = 0x00000000,
.EmcDliTrimTxDqs10 = 0x00000000,
.EmcDliTrimTxDqs11 = 0x00000000,
.EmcDliTrimTxDqs12 = 0x00000000,
.EmcDliTrimTxDqs13 = 0x00000000,
.EmcDliTrimTxDqs14 = 0x00000000,
.EmcDliTrimTxDqs15 = 0x00000000,
.EmcDllXformDq0 = 0x00090000,
.EmcDllXformDq1 = 0x00090000,
.EmcDllXformDq2 = 0x00094000,
.EmcDllXformDq3 = 0x00094000,
.EmcDllXformDq4 = 0x00009400,
.EmcDllXformDq5 = 0x00009000,
.EmcDllXformDq6 = 0x00009000,
.EmcDllXformDq7 = 0x00009000,
.WarmBootWait = 0x00000002,
.EmcCttTermCtrl = 0x00000802,
.EmcOdtWrite = 0x00000000,
.EmcOdtRead = 0x00000000,
.EmcZcalInterval = 0x00020000,
.EmcZcalWaitCnt = 0x00000042,
.EmcZcalMrwCmd = 0x80000000,
.EmcMrsResetDll = 0x00000000,
.EmcZcalInitDev0 = 0x80000011,
.EmcZcalInitDev1 = 0x00000000,
.EmcZcalInitWait = 0x00000003,
.EmcZcalWarmColdBootEnables = 0x00000003,
.EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab,
.EmcZqCalDdr3WarmBoot = 0x00000000,
.EmcZcalWarmBootWait = 0x00000002,
.EmcMrsWarmBootEnable = 0x00000001,
.EmcMrsResetDllWait = 0x00000000,
.EmcMrsExtra = 0x80001221,
.EmcWarmBootMrsExtra = 0x80100003,
.EmcEmrsDdr2DllEnable = 0x00000000,
.EmcMrsDdr2DllReset = 0x00000000,
.EmcEmrsDdr2OcdCalib = 0x00000000,
.EmcDdr2Wait = 0x00000000,
.EmcClkenOverride = 0x00000000,
.McDisExtraSnapLevels = 0x00000000,
.EmcExtraRefreshNum = 0x00000002,
.EmcClkenOverrideAllWarmBoot = 0x00000000,
.McClkenOverrideAllWarmBoot = 0x00000000,
.EmcCfgDigDllPeriodWarmBoot = 0x00000003,
.PmcVddpSel = 0x00000002,
.PmcVddpSelWait = 0x00000002,
.PmcDdrPwr = 0x00000003,
.PmcDdrCfg = 0x00002002,
.PmcIoDpd3Req = 0x4fff2f97,
.PmcIoDpd3ReqWait = 0x00000000,
.PmcRegShort = 0x00000000,
.PmcNoIoPower = 0x00000000,
.PmcPorDpdCtrlWait = 0x00000000,
.EmcXm2CmdPadCtrl = 0x10000280,
.EmcXm2CmdPadCtrl2 = 0x770c0000,
.EmcXm2CmdPadCtrl3 = 0x050c0000,
.EmcXm2CmdPadCtrl4 = 0x00000000,
.EmcXm2CmdPadCtrl5 = 0x00111111,
.EmcXm2DqsPadCtrl = 0x770c1414,
.EmcXm2DqsPadCtrl2 = 0x0130b118,
.EmcXm2DqsPadCtrl3 = 0x51451400,
.EmcXm2DqsPadCtrl4 = 0x00514514,
.EmcXm2DqsPadCtrl5 = 0x00514514,
.EmcXm2DqsPadCtrl6 = 0x51451400,
.EmcXm2DqPadCtrl = 0x770c2990,
.EmcXm2DqPadCtrl2 = 0x00000000,
.EmcXm2DqPadCtrl3 = 0x00000000,
.EmcXm2ClkPadCtrl = 0x77ffc081,
.EmcXm2ClkPadCtrl2 = 0x00000303,
.EmcXm2CompPadCtrl = 0x81f1f108,
.EmcXm2VttGenPadCtrl = 0x07070004,
.EmcXm2VttGenPadCtrl2 = 0x0000003f,
.EmcXm2VttGenPadCtrl3 = 0x016eeeee,
.EmcAcpdControl = 0x00000000,
.EmcSwizzleRank0ByteCfg = 0x00003120,
.EmcSwizzleRank0Byte0 = 0x25143067,
.EmcSwizzleRank0Byte1 = 0x45367102,
.EmcSwizzleRank0Byte2 = 0x47106253,
.EmcSwizzleRank0Byte3 = 0x04362175,
.EmcSwizzleRank1ByteCfg = 0x00003120,
.EmcSwizzleRank1Byte0 = 0x71546032,
.EmcSwizzleRank1Byte1 = 0x35104276,
.EmcSwizzleRank1Byte2 = 0x27043615,
.EmcSwizzleRank1Byte3 = 0x72306145,
.EmcDsrVttgenDrv = 0x0000003f,
.EmcTxdsrvttgen = 0x00000066,
.EmcBgbiasCtl0 = 0x00000008,
.McEmemAdrCfg = 0x00000000,
.McEmemAdrCfgDev0 = 0x00080303,
.McEmemAdrCfgDev1 = 0x00080303,
.McEmemAdrCfgBankMask0 = 0x00001248,
.McEmemAdrCfgBankMask1 = 0x00002490,
.McEmemAdrCfgBankMask2 = 0x00000920,
.McEmemAdrCfgBankSwizzle3 = 0x00000001,
.McEmemCfg = 0x00000800,
.McEmemArbCfg = 0x01000003,
.McEmemArbOutstandingReq = 0x80000040,
.McEmemArbTimingRcd = 0x00000001,
.McEmemArbTimingRp = 0x00000001,
.McEmemArbTimingRc = 0x00000005,
.McEmemArbTimingRas = 0x00000002,
.McEmemArbTimingFaw = 0x00000004,
.McEmemArbTimingRrd = 0x00000001,
.McEmemArbTimingRap2Pre = 0x00000002,
.McEmemArbTimingWap2Pre = 0x00000008,
.McEmemArbTimingR2R = 0x00000003,
.McEmemArbTimingW2W = 0x00000002,
.McEmemArbTimingR2W = 0x00000004,
.McEmemArbTimingW2R = 0x00000006,
.McEmemArbDaTurns = 0x06040203,
.McEmemArbDaCovers = 0x000a0405,
.McEmemArbMisc0 = 0x73840a06,
.McEmemArbMisc1 = 0x70000f03,
.McEmemArbRing1Throttle = 0x001f0000,
.McEmemArbOverride = 0x10000000,
.McEmemArbOverride1 = 0x00000000,
.McEmemArbRsv = 0xff00ff00,
.McClkenOverride = 0x00000000,
.McStatControl = 0x00000000,
.McDisplaySnapRing = 0x00000003,
.McVideoProtectBom = 0xfff00000,
.McVideoProtectBomAdrHi = 0x00000000,
.McVideoProtectSizeMb = 0x00000000,
.McVideoProtectVprOverride = 0xe4bac743,
.McVideoProtectVprOverride1 = 0x00000013,
.McVideoProtectGpuOverride0 = 0x00000000,
.McVideoProtectGpuOverride1 = 0x00000000,
.McSecCarveoutBom = 0xfff00000,
.McSecCarveoutAdrHi = 0x00000000,
.McSecCarveoutSizeMb = 0x00000000,
.McVideoProtectWriteAccess = 0x00000000,
.McSecCarveoutProtectWriteAccess = 0x00000000,
.EmcCaTrainingEnable = 0x00000000,
.EmcCaTrainingTimingCntl1 = 0x1f7df7df,
.EmcCaTrainingTimingCntl2 = 0x0000001f,
.SwizzleRankByteEncode = 0x0000006f,
.BootRomPatchControl = 0x00000000,
.BootRomPatchData = 0x00000000,
.McMtsCarveoutBom = 0xfff00000,
.McMtsCarveoutAdrHi = 0x00000000,
.McMtsCarveoutSizeMb = 0x00000000,
.McMtsCarveoutRegCtrl = 0x00000000,
},

311
src/mainboard/google/nyan_big/bct/sdram-hynix-2GB-792.inc Normal file
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{ /* generated from sdram-0001-792-2GB.cfg; do not edit. */
.MemoryType = NvBootMemoryType_Ddr3,
.PllMInputDivider = 0x00000001,
.PllMFeedbackDivider = 0x00000042,
.PllMStableTime = 0x0000012c,
.PllMSetupControl = 0x00000000,
.PllMSelectDiv2 = 0x00000000,
.PllMPDLshiftPh45 = 0x00000001,
.PllMPDLshiftPh90 = 0x00000001,
.PllMPDLshiftPh135 = 0x00000001,
.PllMKCP = 0x00000000,
.PllMKVCO = 0x00000000,
.EmcBctSpare0 = 0x00000000,
.EmcBctSpare1 = 0x00000000,
.EmcBctSpare2 = 0x00000000,
.EmcBctSpare3 = 0x00000000,
.EmcBctSpare4 = 0x00000000,
.EmcBctSpare5 = 0x00000000,
.EmcBctSpare6 = 0x00000000,
.EmcBctSpare7 = 0x00000000,
.EmcBctSpare8 = 0x00000000,
.EmcBctSpare9 = 0x00000000,
.EmcBctSpare10 = 0x00000000,
.EmcBctSpare11 = 0x00000000,
.EmcClockSource = 0x80000000,
.EmcAutoCalInterval = 0x001fffff,
.EmcAutoCalConfig = 0xa1430000,
.EmcAutoCalConfig2 = 0x00000000,
.EmcAutoCalConfig3 = 0x00000000,
.EmcAutoCalWait = 0x00000190,
.EmcAdrCfg = 0x00000000,
.EmcPinProgramWait = 0x00000001,
.EmcPinExtraWait = 0x00000000,
.EmcTimingControlWait = 0x00000000,
.EmcRc = 0x00000025,
.EmcRfc = 0x000000cc,
.EmcRfcSlr = 0x00000000,
.EmcRas = 0x0000001a,
.EmcRp = 0x00000009,
.EmcR2r = 0x00000000,
.EmcW2w = 0x00000000,
.EmcR2w = 0x00000008,
.EmcW2r = 0x0000000d,
.EmcR2p = 0x00000004,
.EmcW2p = 0x00000013,
.EmcRdRcd = 0x00000009,
.EmcWrRcd = 0x00000009,
.EmcRrd = 0x00000003,
.EmcRext = 0x00000002,
.EmcWext = 0x00000000,
.EmcWdv = 0x00000006,
.EmcWdvMask = 0x00000006,
.EmcQUse = 0x0000000b,
.EmcQuseWidth = 0x00000002,
.EmcIbdly = 0x00000000,
.EmcEInput = 0x00000002,
.EmcEInputDuration = 0x0000000d,
.EmcPutermExtra = 0x00080000,
.EmcPutermWidth = 0x00000004,
.EmcPutermAdj = 0x00000000,
.EmcCdbCntl1 = 0x00000000,
.EmcCdbCntl2 = 0x00000000,
.EmcCdbCntl3 = 0x00000000,
.EmcQRst = 0x00000001,
.EmcQSafe = 0x00000014,
.EmcRdv = 0x00000018,
.EmcRdvMask = 0x0000001a,
.EmcQpop = 0x0000000f,
.EmcCtt = 0x00000000,
.EmcCttDuration = 0x00000004,
.EmcRefresh = 0x000017e2,
.EmcBurstRefreshNum = 0x00000000,
.EmcPreRefreshReqCnt = 0x000005f8,
.EmcPdEx2Wr = 0x00000003,
.EmcPdEx2Rd = 0x00000011,
.EmcPChg2Pden = 0x00000001,
.EmcAct2Pden = 0x00000000,
.EmcAr2Pden = 0x000000c6,
.EmcRw2Pden = 0x00000018,
.EmcTxsr = 0x000000d6,
.EmcTxsrDll = 0x00000200,
.EmcTcke = 0x00000005,
.EmcTckesr = 0x00000006,
.EmcTpd = 0x00000005,
.EmcTfaw = 0x0000001d,
.EmcTrpab = 0x00000000,
.EmcTClkStable = 0x00000008,
.EmcTClkStop = 0x00000008,
.EmcTRefBw = 0x00001822,
.EmcFbioCfg5 = 0x104ab098,
.EmcFbioCfg6 = 0x00000000,
.EmcFbioSpare = 0x00000000,
.EmcCfgRsv = 0xff00ff00,
.EmcMrs = 0x80000d71,
.EmcEmrs = 0x80100002,
.EmcEmrs2 = 0x80200018,
.EmcEmrs3 = 0x80300000,
.EmcMrw1 = 0x00000000,
.EmcMrw2 = 0x00000000,
.EmcMrw3 = 0x00000000,
.EmcMrw4 = 0x00000000,
.EmcMrwExtra = 0x00000000,
.EmcWarmBootMrwExtra = 0x00000000,
.EmcWarmBootExtraModeRegWriteEnable = 0x00000000,
.EmcExtraModeRegWriteEnable = 0x00000000,
.EmcMrwResetCommand = 0x00000000,
.EmcMrwResetNInitWait = 0x00000000,
.EmcMrsWaitCnt = 0x00f8000c,
.EmcMrsWaitCnt2 = 0x00f8000c,
.EmcCfg = 0x73300000,
.EmcCfg2 = 0x0000089d,
.EmcCfgPipe = 0x00004080,
.EmcDbg = 0x01000c00,
.EmcCmdQ = 0x10004408,
.EmcMc2EmcQ = 0x06000404,
.EmcDynSelfRefControl = 0x80003012,
.AhbArbitrationXbarCtrlMemInitDone = 0x00000001,
.EmcCfgDigDll = 0xe00700b1,
.EmcCfgDigDllPeriod = 0x00008000,
.EmcDevSelect = 0x00000002,
.EmcSelDpdCtrl = 0x00040000,
.EmcDllXformDqs0 = 0x00000008,
.EmcDllXformDqs1 = 0x00000008,
.EmcDllXformDqs2 = 0x00000008,
.EmcDllXformDqs3 = 0x00000008,
.EmcDllXformDqs4 = 0x00000008,
.EmcDllXformDqs5 = 0x00000008,
.EmcDllXformDqs6 = 0x00000008,
.EmcDllXformDqs7 = 0x00000008,
.EmcDllXformDqs8 = 0x00000008,
.EmcDllXformDqs9 = 0x00000008,
.EmcDllXformDqs10 = 0x00000008,
.EmcDllXformDqs11 = 0x00000008,
.EmcDllXformDqs12 = 0x00000008,
.EmcDllXformDqs13 = 0x00000008,
.EmcDllXformDqs14 = 0x00000008,
.EmcDllXformDqs15 = 0x00000008,
.EmcDllXformQUse0 = 0x00000000,
.EmcDllXformQUse1 = 0x00000000,
.EmcDllXformQUse2 = 0x00000000,
.EmcDllXformQUse3 = 0x00000000,
.EmcDllXformQUse4 = 0x00000000,
.EmcDllXformQUse5 = 0x00000000,
.EmcDllXformQUse6 = 0x00000000,
.EmcDllXformQUse7 = 0x00000000,
.EmcDllXformAddr0 = 0x00034000,
.EmcDllXformAddr1 = 0x00034000,
.EmcDllXformAddr2 = 0x00000000,
.EmcDllXformAddr3 = 0x00034000,
.EmcDllXformAddr4 = 0x00034000,
.EmcDllXformAddr5 = 0x00000000,
.EmcDllXformQUse8 = 0x00000000,
.EmcDllXformQUse9 = 0x00000000,
.EmcDllXformQUse10 = 0x00000000,
.EmcDllXformQUse11 = 0x00000000,
.EmcDllXformQUse12 = 0x00000000,
.EmcDllXformQUse13 = 0x00000000,
.EmcDllXformQUse14 = 0x00000000,
.EmcDllXformQUse15 = 0x00000000,
.EmcDliTrimTxDqs0 = 0x00000008,
.EmcDliTrimTxDqs1 = 0x00000008,
.EmcDliTrimTxDqs2 = 0x00000005,
.EmcDliTrimTxDqs3 = 0x00000009,
.EmcDliTrimTxDqs4 = 0x00000009,
.EmcDliTrimTxDqs5 = 0x00000007,
.EmcDliTrimTxDqs6 = 0x00000009,
.EmcDliTrimTxDqs7 = 0x00000008,
.EmcDliTrimTxDqs8 = 0x00000008,
.EmcDliTrimTxDqs9 = 0x00000008,
.EmcDliTrimTxDqs10 = 0x00000005,
.EmcDliTrimTxDqs11 = 0x00000009,
.EmcDliTrimTxDqs12 = 0x00000009,
.EmcDliTrimTxDqs13 = 0x00000007,
.EmcDliTrimTxDqs14 = 0x00000009,
.EmcDliTrimTxDqs15 = 0x00000008,
.EmcDllXformDq0 = 0x0000000e,
.EmcDllXformDq1 = 0x0000000e,
.EmcDllXformDq2 = 0x0000000e,
.EmcDllXformDq3 = 0x0000000e,
.EmcDllXformDq4 = 0x0000000e,
.EmcDllXformDq5 = 0x0000000e,
.EmcDllXformDq6 = 0x0000000e,
.EmcDllXformDq7 = 0x0000000e,
.WarmBootWait = 0x00000002,
.EmcCttTermCtrl = 0x00000802,
.EmcOdtWrite = 0x00000000,
.EmcOdtRead = 0x00000000,
.EmcZcalInterval = 0x00020000,
.EmcZcalWaitCnt = 0x00000042,
.EmcZcalMrwCmd = 0x80000000,
.EmcMrsResetDll = 0x00000000,
.EmcZcalInitDev0 = 0x80000011,
.EmcZcalInitDev1 = 0x00000000,
.EmcZcalInitWait = 0x00000001,
.EmcZcalWarmColdBootEnables = 0x00000003,
.EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab,
.EmcZqCalDdr3WarmBoot = 0x00000000,
.EmcZcalWarmBootWait = 0x00000001,
.EmcMrsWarmBootEnable = 0x00000001,
.EmcMrsResetDllWait = 0x00000000,
.EmcMrsExtra = 0x80000d71,
.EmcWarmBootMrsExtra = 0x80100002,
.EmcEmrsDdr2DllEnable = 0x00000000,
.EmcMrsDdr2DllReset = 0x00000000,
.EmcEmrsDdr2OcdCalib = 0x00000000,
.EmcDdr2Wait = 0x00000000,
.EmcClkenOverride = 0x00000000,
.McDisExtraSnapLevels = 0x00000000,
.EmcExtraRefreshNum = 0x00000002,
.EmcClkenOverrideAllWarmBoot = 0x00000000,
.McClkenOverrideAllWarmBoot = 0x00000000,
.EmcCfgDigDllPeriodWarmBoot = 0x00000003,
.PmcVddpSel = 0x00000002,
.PmcVddpSelWait = 0x00000002,
.PmcDdrPwr = 0x00000003,
.PmcDdrCfg = 0x00002002,
.PmcIoDpd3Req = 0x4fff2f97,
.PmcIoDpd3ReqWait = 0x00000000,
.PmcRegShort = 0x00000000,
.PmcNoIoPower = 0x00000000,
.PmcPorDpdCtrlWait = 0x00000000,
.EmcXm2CmdPadCtrl = 0x100002a0,
.EmcXm2CmdPadCtrl2 = 0x770c0000,
.EmcXm2CmdPadCtrl3 = 0x050c0000,
.EmcXm2CmdPadCtrl4 = 0x00000000,
.EmcXm2CmdPadCtrl5 = 0x00111111,
.EmcXm2DqsPadCtrl = 0x770c1414,
.EmcXm2DqsPadCtrl2 = 0x0120113d,
.EmcXm2DqsPadCtrl3 = 0x61861820,
.EmcXm2DqsPadCtrl4 = 0x00514514,
.EmcXm2DqsPadCtrl5 = 0x00514514,
.EmcXm2DqsPadCtrl6 = 0x61861800,
.EmcXm2DqPadCtrl = 0x770c2990,
.EmcXm2DqPadCtrl2 = 0x00000000,
.EmcXm2DqPadCtrl3 = 0x00000000,
.EmcXm2ClkPadCtrl = 0x77ffc085,
.EmcXm2ClkPadCtrl2 = 0x00000101,
.EmcXm2CompPadCtrl = 0x81f1f108,
.EmcXm2VttGenPadCtrl = 0x07070004,
.EmcXm2VttGenPadCtrl2 = 0x00000000,
.EmcXm2VttGenPadCtrl3 = 0x016eeeee,
.EmcAcpdControl = 0x00000000,
.EmcSwizzleRank0ByteCfg = 0x00003120,
.EmcSwizzleRank0Byte0 = 0x25143067,
.EmcSwizzleRank0Byte1 = 0x45367102,
.EmcSwizzleRank0Byte2 = 0x47106253,
.EmcSwizzleRank0Byte3 = 0x04362175,
.EmcSwizzleRank1ByteCfg = 0x00003120,
.EmcSwizzleRank1Byte0 = 0x71546032,
.EmcSwizzleRank1Byte1 = 0x35104276,
.EmcSwizzleRank1Byte2 = 0x27043615,
.EmcSwizzleRank1Byte3 = 0x72306145,
.EmcDsrVttgenDrv = 0x0606003f,
.EmcTxdsrvttgen = 0x00000000,
.EmcBgbiasCtl0 = 0x00000000,
.McEmemAdrCfg = 0x00000000,
.McEmemAdrCfgDev0 = 0x00080303,
.McEmemAdrCfgDev1 = 0x00080303,
.McEmemAdrCfgBankMask0 = 0x00001248,
.McEmemAdrCfgBankMask1 = 0x00002490,
.McEmemAdrCfgBankMask2 = 0x00000920,
.McEmemAdrCfgBankSwizzle3 = 0x00000001,
.McEmemCfg = 0x00000800,
.McEmemArbCfg = 0x0e00000b,
.McEmemArbOutstandingReq = 0x80000040,
.McEmemArbTimingRcd = 0x00000004,
.McEmemArbTimingRp = 0x00000005,
.McEmemArbTimingRc = 0x00000013,
.McEmemArbTimingRas = 0x0000000c,
.McEmemArbTimingFaw = 0x0000000f,
.McEmemArbTimingRrd = 0x00000002,
.McEmemArbTimingRap2Pre = 0x00000003,
.McEmemArbTimingWap2Pre = 0x0000000c,
.McEmemArbTimingR2R = 0x00000002,
.McEmemArbTimingW2W = 0x00000002,
.McEmemArbTimingR2W = 0x00000006,
.McEmemArbTimingW2R = 0x00000008,
.McEmemArbDaTurns = 0x08060202,
.McEmemArbDaCovers = 0x00160d13,
.McEmemArbMisc0 = 0x734c2414,
.McEmemArbMisc1 = 0x70000f02,
.McEmemArbRing1Throttle = 0x001f0000,
.McEmemArbOverride = 0x10000000,
.McEmemArbOverride1 = 0x00000000,
.McEmemArbRsv = 0xff00ff00,
.McClkenOverride = 0x00000000,
.McStatControl = 0x00000000,
.McDisplaySnapRing = 0x00000003,
.McVideoProtectBom = 0xfff00000,
.McVideoProtectBomAdrHi = 0x00000000,
.McVideoProtectSizeMb = 0x00000000,
.McVideoProtectVprOverride = 0xe4bac743,
.McVideoProtectVprOverride1 = 0x00000013,
.McVideoProtectGpuOverride0 = 0x00000000,
.McVideoProtectGpuOverride1 = 0x00000000,
.McSecCarveoutBom = 0xfff00000,
.McSecCarveoutAdrHi = 0x00000000,
.McSecCarveoutSizeMb = 0x00000000,
.McVideoProtectWriteAccess = 0x00000000,
.McSecCarveoutProtectWriteAccess = 0x00000000,
.EmcCaTrainingEnable = 0x00000000,
.EmcCaTrainingTimingCntl1 = 0x1f7df7df,
.EmcCaTrainingTimingCntl2 = 0x0000001f,
.SwizzleRankByteEncode = 0x0000006f,
.BootRomPatchControl = 0x00000000,
.BootRomPatchData = 0x00000000,
.McMtsCarveoutBom = 0xfff00000,
.McMtsCarveoutAdrHi = 0x00000000,
.McMtsCarveoutSizeMb = 0x00000000,
.McMtsCarveoutRegCtrl = 0x00000000,
},

311
src/mainboard/google/nyan_big/bct/sdram-hynix-2GB-924.inc Normal file
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{ /* generated from sdram-0001-924-2GB.cfg; do not edit. */
.MemoryType = NvBootMemoryType_Ddr3,
.PllMInputDivider = 0x00000001,
.PllMFeedbackDivider = 0x0000004d,
.PllMStableTime = 0x0000012c,
.PllMSetupControl = 0x00000000,
.PllMSelectDiv2 = 0x00000000,
.PllMPDLshiftPh45 = 0x00000001,
.PllMPDLshiftPh90 = 0x00000001,
.PllMPDLshiftPh135 = 0x00000001,
.PllMKCP = 0x00000000,
.PllMKVCO = 0x00000000,
.EmcBctSpare0 = 0x00000000,
.EmcBctSpare1 = 0x00000000,
.EmcBctSpare2 = 0x00000000,
.EmcBctSpare3 = 0x00000000,
.EmcBctSpare4 = 0x00000000,
.EmcBctSpare5 = 0x00000000,
.EmcBctSpare6 = 0x00000000,
.EmcBctSpare7 = 0x00000000,
.EmcBctSpare8 = 0x00000000,
.EmcBctSpare9 = 0x00000000,
.EmcBctSpare10 = 0x00000000,
.EmcBctSpare11 = 0x00000000,
.EmcClockSource = 0x80000000,
.EmcAutoCalInterval = 0x001fffff,
.EmcAutoCalConfig = 0xa1430404,
.EmcAutoCalConfig2 = 0x00000000,
.EmcAutoCalConfig3 = 0x00000000,
.EmcAutoCalWait = 0x00000190,
.EmcAdrCfg = 0x00000000,
.EmcPinProgramWait = 0x00000001,
.EmcPinExtraWait = 0x00000000,
.EmcTimingControlWait = 0x00000000,
.EmcRc = 0x0000002b,
.EmcRfc = 0x000000ef,
.EmcRfcSlr = 0x00000000,
.EmcRas = 0x0000001e,
.EmcRp = 0x0000000b,
.EmcR2r = 0x00000000,
.EmcW2w = 0x00000000,
.EmcR2w = 0x00000008,
.EmcW2r = 0x0000000f,
.EmcR2p = 0x00000005,
.EmcW2p = 0x00000016,
.EmcRdRcd = 0x0000000b,
.EmcWrRcd = 0x0000000b,
.EmcRrd = 0x00000004,
.EmcRext = 0x00000002,
.EmcWext = 0x00000000,
.EmcWdv = 0x00000006,
.EmcWdvMask = 0x00000006,
.EmcQUse = 0x0000000c,
.EmcQuseWidth = 0x00000002,
.EmcIbdly = 0x00000000,
.EmcEInput = 0x00000002,
.EmcEInputDuration = 0x0000000e,
.EmcPutermExtra = 0x000a0000,
.EmcPutermWidth = 0x00000004,
.EmcPutermAdj = 0x00000000,
.EmcCdbCntl1 = 0x00000000,
.EmcCdbCntl2 = 0x00000000,
.EmcCdbCntl3 = 0x00000000,
.EmcQRst = 0x00000001,
.EmcQSafe = 0x00000015,
.EmcRdv = 0x0000001b,
.EmcRdvMask = 0x0000001d,
.EmcQpop = 0x00000010,
.EmcCtt = 0x00000000,
.EmcCttDuration = 0x00000004,
.EmcRefresh = 0x00001be9,
.EmcBurstRefreshNum = 0x00000000,
.EmcPreRefreshReqCnt = 0x000006fa,
.EmcPdEx2Wr = 0x00000004,
.EmcPdEx2Rd = 0x00000015,
.EmcPChg2Pden = 0x00000001,
.EmcAct2Pden = 0x00000000,
.EmcAr2Pden = 0x000000e6,
.EmcRw2Pden = 0x0000001b,
.EmcTxsr = 0x000000fa,
.EmcTxsrDll = 0x00000200,
.EmcTcke = 0x00000006,
.EmcTckesr = 0x00000007,
.EmcTpd = 0x00000006,
.EmcTfaw = 0x00000022,
.EmcTrpab = 0x00000000,
.EmcTClkStable = 0x0000000a,
.EmcTClkStop = 0x0000000a,
.EmcTRefBw = 0x00001c29,
.EmcFbioCfg5 = 0x104ab898,
.EmcFbioCfg6 = 0x00000002,
.EmcFbioSpare = 0x00000000,
.EmcCfgRsv = 0xff00ff00,
.EmcMrs = 0x80000f15,
.EmcEmrs = 0x80100002,
.EmcEmrs2 = 0x80200020,
.EmcEmrs3 = 0x80300000,
.EmcMrw1 = 0x00000000,
.EmcMrw2 = 0x00000000,
.EmcMrw3 = 0x00000000,
.EmcMrw4 = 0x00000000,
.EmcMrwExtra = 0x00000000,
.EmcWarmBootMrwExtra = 0x00000000,
.EmcWarmBootExtraModeRegWriteEnable = 0x00000000,
.EmcExtraModeRegWriteEnable = 0x00000000,
.EmcMrwResetCommand = 0x00000000,
.EmcMrwResetNInitWait = 0x00000000,
.EmcMrsWaitCnt = 0x00ce000e,
.EmcMrsWaitCnt2 = 0x00ce000e,
.EmcCfg = 0x73300000,
.EmcCfg2 = 0x000008a5,
.EmcCfgPipe = 0x00000000,
.EmcDbg = 0x01000c00,
.EmcCmdQ = 0x10004408,
.EmcMc2EmcQ = 0x06000404,
.EmcDynSelfRefControl = 0x800037ed,
.AhbArbitrationXbarCtrlMemInitDone = 0x00000001,
.EmcCfgDigDll = 0xe00401b1,
.EmcCfgDigDllPeriod = 0x00008000,
.EmcDevSelect = 0x00000002,
.EmcSelDpdCtrl = 0x00040000,
.EmcDllXformDqs0 = 0x00000005,
.EmcDllXformDqs1 = 0x00000005,
.EmcDllXformDqs2 = 0x00000005,
.EmcDllXformDqs3 = 0x00000005,
.EmcDllXformDqs4 = 0x00000005,
.EmcDllXformDqs5 = 0x00000005,
.EmcDllXformDqs6 = 0x00000005,
.EmcDllXformDqs7 = 0x00000005,
.EmcDllXformDqs8 = 0x00000005,
.EmcDllXformDqs9 = 0x00000005,
.EmcDllXformDqs10 = 0x00000005,
.EmcDllXformDqs11 = 0x00000005,
.EmcDllXformDqs12 = 0x00000005,
.EmcDllXformDqs13 = 0x00000005,
.EmcDllXformDqs14 = 0x00000005,
.EmcDllXformDqs15 = 0x00000005,
.EmcDllXformQUse0 = 0x00000000,
.EmcDllXformQUse1 = 0x00000000,
.EmcDllXformQUse2 = 0x00000000,
.EmcDllXformQUse3 = 0x00000000,
.EmcDllXformQUse4 = 0x00000000,
.EmcDllXformQUse5 = 0x00000000,
.EmcDllXformQUse6 = 0x00000000,
.EmcDllXformQUse7 = 0x00000000,
.EmcDllXformAddr0 = 0x0000400e,
.EmcDllXformAddr1 = 0x0000400e,
.EmcDllXformAddr2 = 0x00000000,
.EmcDllXformAddr3 = 0x0000400e,
.EmcDllXformAddr4 = 0x0000400e,
.EmcDllXformAddr5 = 0x00000000,
.EmcDllXformQUse8 = 0x00000000,
.EmcDllXformQUse9 = 0x00000000,
.EmcDllXformQUse10 = 0x00000000,
.EmcDllXformQUse11 = 0x00000000,
.EmcDllXformQUse12 = 0x00000000,
.EmcDllXformQUse13 = 0x00000000,
.EmcDllXformQUse14 = 0x00000000,
.EmcDllXformQUse15 = 0x00000000,
.EmcDliTrimTxDqs0 = 0x00000000,
.EmcDliTrimTxDqs1 = 0x00000000,
.EmcDliTrimTxDqs2 = 0x00000000,
.EmcDliTrimTxDqs3 = 0x00000000,
.EmcDliTrimTxDqs4 = 0x00000000,
.EmcDliTrimTxDqs5 = 0x00000000,
.EmcDliTrimTxDqs6 = 0x00000000,
.EmcDliTrimTxDqs7 = 0x00000000,
.EmcDliTrimTxDqs8 = 0x00000000,
.EmcDliTrimTxDqs9 = 0x00000000,
.EmcDliTrimTxDqs10 = 0x00000000,
.EmcDliTrimTxDqs11 = 0x00000000,
.EmcDliTrimTxDqs12 = 0x00000000,
.EmcDliTrimTxDqs13 = 0x00000000,
.EmcDliTrimTxDqs14 = 0x00000000,
.EmcDliTrimTxDqs15 = 0x00000000,
.EmcDllXformDq0 = 0x00000006,
.EmcDllXformDq1 = 0x00000006,
.EmcDllXformDq2 = 0x00000006,
.EmcDllXformDq3 = 0x00000006,
.EmcDllXformDq4 = 0x00000006,
.EmcDllXformDq5 = 0x00000006,
.EmcDllXformDq6 = 0x00000006,
.EmcDllXformDq7 = 0x00000006,
.WarmBootWait = 0x00000002,
.EmcCttTermCtrl = 0x00000802,
.EmcOdtWrite = 0x00000000,
.EmcOdtRead = 0x00000000,
.EmcZcalInterval = 0x00020000,
.EmcZcalWaitCnt = 0x0000004c,
.EmcZcalMrwCmd = 0x80000000,
.EmcMrsResetDll = 0x00000000,
.EmcZcalInitDev0 = 0x80000011,
.EmcZcalInitDev1 = 0x00000000,
.EmcZcalInitWait = 0x00000001,
.EmcZcalWarmColdBootEnables = 0x00000003,
.EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab,
.EmcZqCalDdr3WarmBoot = 0x00000000,
.EmcZcalWarmBootWait = 0x00000001,
.EmcMrsWarmBootEnable = 0x00000001,
.EmcMrsResetDllWait = 0x00000000,
.EmcMrsExtra = 0x80000f15,
.EmcWarmBootMrsExtra = 0x80100002,
.EmcEmrsDdr2DllEnable = 0x00000000,
.EmcMrsDdr2DllReset = 0x00000000,
.EmcEmrsDdr2OcdCalib = 0x00000000,
.EmcDdr2Wait = 0x00000000,
.EmcClkenOverride = 0x00000000,
.McDisExtraSnapLevels = 0x00000000,
.EmcExtraRefreshNum = 0x00000002,
.EmcClkenOverrideAllWarmBoot = 0x00000000,
.McClkenOverrideAllWarmBoot = 0x00000000,
.EmcCfgDigDllPeriodWarmBoot = 0x00000003,
.PmcVddpSel = 0x00000002,
.PmcVddpSelWait = 0x00000002,
.PmcDdrPwr = 0x00000003,
.PmcDdrCfg = 0x00002002,
.PmcIoDpd3Req = 0x4fff2f97,
.PmcIoDpd3ReqWait = 0x00000000,
.PmcRegShort = 0x00000000,
.PmcNoIoPower = 0x00000000,
.PmcPorDpdCtrlWait = 0x00000000,
.EmcXm2CmdPadCtrl = 0x100002a0,
.EmcXm2CmdPadCtrl2 = 0x770c0000,
.EmcXm2CmdPadCtrl3 = 0x050c0000,
.EmcXm2CmdPadCtrl4 = 0x00000000,
.EmcXm2CmdPadCtrl5 = 0x00111111,
.EmcXm2DqsPadCtrl = 0x770c1414,
.EmcXm2DqsPadCtrl2 = 0x0020013d,
.EmcXm2DqsPadCtrl3 = 0x55555520,
.EmcXm2DqsPadCtrl4 = 0x003cf3cf,
.EmcXm2DqsPadCtrl5 = 0x003cf3cf,
.EmcXm2DqsPadCtrl6 = 0x55555500,
.EmcXm2DqPadCtrl = 0x770c2990,
.EmcXm2DqPadCtrl2 = 0x00000000,
.EmcXm2DqPadCtrl3 = 0x00000000,
.EmcXm2ClkPadCtrl = 0x77ffc085,
.EmcXm2ClkPadCtrl2 = 0x00000303,
.EmcXm2CompPadCtrl = 0x81f1f108,
.EmcXm2VttGenPadCtrl = 0x07070004,
.EmcXm2VttGenPadCtrl2 = 0x00000000,
.EmcXm2VttGenPadCtrl3 = 0x016eeeee,
.EmcAcpdControl = 0x00000000,
.EmcSwizzleRank0ByteCfg = 0x00003120,
.EmcSwizzleRank0Byte0 = 0x25143067,
.EmcSwizzleRank0Byte1 = 0x45367102,
.EmcSwizzleRank0Byte2 = 0x47106253,
.EmcSwizzleRank0Byte3 = 0x04362175,
.EmcSwizzleRank1ByteCfg = 0x00003120,
.EmcSwizzleRank1Byte0 = 0x71546032,
.EmcSwizzleRank1Byte1 = 0x35104276,
.EmcSwizzleRank1Byte2 = 0x27043615,
.EmcSwizzleRank1Byte3 = 0x72306145,
.EmcDsrVttgenDrv = 0x0606003f,
.EmcTxdsrvttgen = 0x00000000,
.EmcBgbiasCtl0 = 0x00000000,
.McEmemAdrCfg = 0x00000000,
.McEmemAdrCfgDev0 = 0x00080303,
.McEmemAdrCfgDev1 = 0x00080303,
.McEmemAdrCfgBankMask0 = 0x00001248,
.McEmemAdrCfgBankMask1 = 0x00002490,
.McEmemAdrCfgBankMask2 = 0x00000920,
.McEmemAdrCfgBankSwizzle3 = 0x00000001,
.McEmemCfg = 0x00000800,
.McEmemArbCfg = 0x0e00000d,
.McEmemArbOutstandingReq = 0x80000040,
.McEmemArbTimingRcd = 0x00000005,
.McEmemArbTimingRp = 0x00000006,
.McEmemArbTimingRc = 0x00000016,
.McEmemArbTimingRas = 0x0000000e,
.McEmemArbTimingFaw = 0x00000011,
.McEmemArbTimingRrd = 0x00000002,
.McEmemArbTimingRap2Pre = 0x00000004,
.McEmemArbTimingWap2Pre = 0x0000000e,
.McEmemArbTimingR2R = 0x00000002,
.McEmemArbTimingW2W = 0x00000002,
.McEmemArbTimingR2W = 0x00000006,
.McEmemArbTimingW2R = 0x00000009,
.McEmemArbDaTurns = 0x09060202,
.McEmemArbDaCovers = 0x001a1016,
.McEmemArbMisc0 = 0x734e2a17,
.McEmemArbMisc1 = 0x70000f02,
.McEmemArbRing1Throttle = 0x001f0000,
.McEmemArbOverride = 0x10000000,
.McEmemArbOverride1 = 0x00000000,
.McEmemArbRsv = 0xff00ff00,
.McClkenOverride = 0x00000000,
.McStatControl = 0x00000000,
.McDisplaySnapRing = 0x00000003,
.McVideoProtectBom = 0xfff00000,
.McVideoProtectBomAdrHi = 0x00000000,
.McVideoProtectSizeMb = 0x00000000,
.McVideoProtectVprOverride = 0xe4bac743,
.McVideoProtectVprOverride1 = 0x00000013,
.McVideoProtectGpuOverride0 = 0x00000000,
.McVideoProtectGpuOverride1 = 0x00000000,
.McSecCarveoutBom = 0xfff00000,
.McSecCarveoutAdrHi = 0x00000000,
.McSecCarveoutSizeMb = 0x00000000,
.McVideoProtectWriteAccess = 0x00000000,
.McSecCarveoutProtectWriteAccess = 0x00000000,
.EmcCaTrainingEnable = 0x00000000,
.EmcCaTrainingTimingCntl1 = 0x1f7df7df,
.EmcCaTrainingTimingCntl2 = 0x0000001f,
.SwizzleRankByteEncode = 0x0000006f,
.BootRomPatchControl = 0x00000000,
.BootRomPatchData = 0x00000000,
.McMtsCarveoutBom = 0xfff00000,
.McMtsCarveoutAdrHi = 0x00000000,
.McMtsCarveoutSizeMb = 0x00000000,
.McMtsCarveoutRegCtrl = 0x00000000,
},

311
src/mainboard/google/nyan_big/bct/sdram-hynix-4GB-204.inc Normal file
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@ -0,0 +1,311 @@
{ /* generated from sdram-0100-204-4GB.cfg; do not edit. */
.MemoryType = NvBootMemoryType_Ddr3,
.PllMInputDivider = 0x00000001,
.PllMFeedbackDivider = 0x00000022,
.PllMStableTime = 0x0000012c,
.PllMSetupControl = 0x00000000,
.PllMSelectDiv2 = 0x00000000,
.PllMPDLshiftPh45 = 0x00000001,
.PllMPDLshiftPh90 = 0x00000001,
.PllMPDLshiftPh135 = 0x00000001,
.PllMKCP = 0x00000000,
.PllMKVCO = 0x00000000,
.EmcBctSpare0 = 0x00000000,
.EmcBctSpare1 = 0x00000000,
.EmcBctSpare2 = 0x00000000,
.EmcBctSpare3 = 0x00000000,
.EmcBctSpare4 = 0x00000000,
.EmcBctSpare5 = 0x00000000,
.EmcBctSpare6 = 0x00000000,
.EmcBctSpare7 = 0x00000000,
.EmcBctSpare8 = 0x00000000,
.EmcBctSpare9 = 0x00000000,
.EmcBctSpare10 = 0x00000000,
.EmcBctSpare11 = 0x00000000,
.EmcClockSource = 0x40000002,
.EmcAutoCalInterval = 0x001fffff,
.EmcAutoCalConfig = 0xa1430000,
.EmcAutoCalConfig2 = 0x00000000,
.EmcAutoCalConfig3 = 0x00000000,
.EmcAutoCalWait = 0x00000190,
.EmcAdrCfg = 0x00000001,
.EmcPinProgramWait = 0x00000001,
.EmcPinExtraWait = 0x00000000,
.EmcTimingControlWait = 0x00000000,
.EmcRc = 0x00000009,
.EmcRfc = 0x00000047,
.EmcRfcSlr = 0x00000000,
.EmcRas = 0x00000007,
.EmcRp = 0x00000002,
.EmcR2r = 0x00000000,
.EmcW2w = 0x00000000,
.EmcR2w = 0x00000005,
.EmcW2r = 0x0000000a,
.EmcR2p = 0x00000003,
.EmcW2p = 0x0000000b,
.EmcRdRcd = 0x00000002,
.EmcWrRcd = 0x00000002,
.EmcRrd = 0x00000003,
.EmcRext = 0x00000003,
.EmcWext = 0x00000000,
.EmcWdv = 0x00000005,
.EmcWdvMask = 0x00000005,
.EmcQUse = 0x00000006,
.EmcQuseWidth = 0x00000002,
.EmcIbdly = 0x00000000,
.EmcEInput = 0x00000004,
.EmcEInputDuration = 0x00000006,
.EmcPutermExtra = 0x00010000,
.EmcPutermWidth = 0x00000003,
.EmcPutermAdj = 0x00000000,
.EmcCdbCntl1 = 0x00000000,
.EmcCdbCntl2 = 0x00000000,
.EmcCdbCntl3 = 0x00000000,
.EmcQRst = 0x00000003,
.EmcQSafe = 0x0000000d,
.EmcRdv = 0x0000000f,
.EmcRdvMask = 0x00000011,
.EmcQpop = 0x0000000a,
.EmcCtt = 0x00000000,
.EmcCttDuration = 0x00000003,
.EmcRefresh = 0x00000607,
.EmcBurstRefreshNum = 0x00000000,
.EmcPreRefreshReqCnt = 0x00000181,
.EmcPdEx2Wr = 0x00000002,
.EmcPdEx2Rd = 0x00000002,
.EmcPChg2Pden = 0x00000001,
.EmcAct2Pden = 0x00000000,
.EmcAr2Pden = 0x00000044,
.EmcRw2Pden = 0x0000000f,
.EmcTxsr = 0x0000004a,
.EmcTxsrDll = 0x0000004a,
.EmcTcke = 0x00000004,
.EmcTckesr = 0x00000005,
.EmcTpd = 0x00000004,
.EmcTfaw = 0x00000007,
.EmcTrpab = 0x00000000,
.EmcTClkStable = 0x00000005,
.EmcTClkStop = 0x00000005,
.EmcTRefBw = 0x00000638,
.EmcFbioCfg5 = 0x106aa298,
.EmcFbioCfg6 = 0x00000000,
.EmcFbioSpare = 0x00000000,
.EmcCfgRsv = 0xff00ff00,
.EmcMrs = 0x00001221,
.EmcEmrs = 0x00100003,
.EmcEmrs2 = 0x00200008,
.EmcEmrs3 = 0x00300000,
.EmcMrw1 = 0x00000000,
.EmcMrw2 = 0x00000000,
.EmcMrw3 = 0x00000000,
.EmcMrw4 = 0x00000000,
.EmcMrwExtra = 0x00000000,
.EmcWarmBootMrwExtra = 0x00000000,
.EmcWarmBootExtraModeRegWriteEnable = 0x00000000,
.EmcExtraModeRegWriteEnable = 0x00000000,
.EmcMrwResetCommand = 0x00000000,
.EmcMrwResetNInitWait = 0x00000000,
.EmcMrsWaitCnt = 0x000c000c,
.EmcMrsWaitCnt2 = 0x000c000c,
.EmcCfg = 0x73240000,
.EmcCfg2 = 0x0000088d,
.EmcCfgPipe = 0x0000d2b3,
.EmcDbg = 0x01000c00,
.EmcCmdQ = 0x10004408,
.EmcMc2EmcQ = 0x06000404,
.EmcDynSelfRefControl = 0x80000d22,
.AhbArbitrationXbarCtrlMemInitDone = 0x00000001,
.EmcCfgDigDll = 0x002c00a0,
.EmcCfgDigDllPeriod = 0x00008000,
.EmcDevSelect = 0x00000000,
.EmcSelDpdCtrl = 0x00040008,
.EmcDllXformDqs0 = 0x00064000,
.EmcDllXformDqs1 = 0x00064000,
.EmcDllXformDqs2 = 0x00064000,
.EmcDllXformDqs3 = 0x00064000,
.EmcDllXformDqs4 = 0x00064000,
.EmcDllXformDqs5 = 0x00064000,
.EmcDllXformDqs6 = 0x00064000,
.EmcDllXformDqs7 = 0x00064000,
.EmcDllXformDqs8 = 0x00064000,
.EmcDllXformDqs9 = 0x00064000,
.EmcDllXformDqs10 = 0x00064000,
.EmcDllXformDqs11 = 0x00064000,
.EmcDllXformDqs12 = 0x00064000,
.EmcDllXformDqs13 = 0x00064000,
.EmcDllXformDqs14 = 0x00064000,
.EmcDllXformDqs15 = 0x00064000,
.EmcDllXformQUse0 = 0x00000000,
.EmcDllXformQUse1 = 0x00000000,
.EmcDllXformQUse2 = 0x00000000,
.EmcDllXformQUse3 = 0x00000000,
.EmcDllXformQUse4 = 0x00000000,
.EmcDllXformQUse5 = 0x00000000,
.EmcDllXformQUse6 = 0x00000000,
.EmcDllXformQUse7 = 0x00000000,
.EmcDllXformAddr0 = 0x00000000,
.EmcDllXformAddr1 = 0x00000000,
.EmcDllXformAddr2 = 0x00004000,
.EmcDllXformAddr3 = 0x00000000,
.EmcDllXformAddr4 = 0x00000000,
.EmcDllXformAddr5 = 0x00004000,
.EmcDllXformQUse8 = 0x00000000,
.EmcDllXformQUse9 = 0x00000000,
.EmcDllXformQUse10 = 0x00000000,
.EmcDllXformQUse11 = 0x00000000,
.EmcDllXformQUse12 = 0x00000000,
.EmcDllXformQUse13 = 0x00000000,
.EmcDllXformQUse14 = 0x00000000,
.EmcDllXformQUse15 = 0x00000000,
.EmcDliTrimTxDqs0 = 0x00000000,
.EmcDliTrimTxDqs1 = 0x00000000,
.EmcDliTrimTxDqs2 = 0x00000000,
.EmcDliTrimTxDqs3 = 0x00000000,
.EmcDliTrimTxDqs4 = 0x00000000,
.EmcDliTrimTxDqs5 = 0x00000000,
.EmcDliTrimTxDqs6 = 0x00000000,
.EmcDliTrimTxDqs7 = 0x00000000,
.EmcDliTrimTxDqs8 = 0x00000000,
.EmcDliTrimTxDqs9 = 0x00000000,
.EmcDliTrimTxDqs10 = 0x00000000,
.EmcDliTrimTxDqs11 = 0x00000000,
.EmcDliTrimTxDqs12 = 0x00000000,
.EmcDliTrimTxDqs13 = 0x00000000,
.EmcDliTrimTxDqs14 = 0x00000000,
.EmcDliTrimTxDqs15 = 0x00000000,
.EmcDllXformDq0 = 0x00090000,
.EmcDllXformDq1 = 0x00090000,
.EmcDllXformDq2 = 0x00094000,
.EmcDllXformDq3 = 0x00094000,
.EmcDllXformDq4 = 0x00009400,
.EmcDllXformDq5 = 0x00009000,
.EmcDllXformDq6 = 0x00009000,
.EmcDllXformDq7 = 0x00009000,
.WarmBootWait = 0x00000002,
.EmcCttTermCtrl = 0x00000802,
.EmcOdtWrite = 0x00000000,
.EmcOdtRead = 0x00000000,
.EmcZcalInterval = 0x00020000,
.EmcZcalWaitCnt = 0x00000042,
.EmcZcalMrwCmd = 0x00000000,
.EmcMrsResetDll = 0x00000000,
.EmcZcalInitDev0 = 0x80000011,
.EmcZcalInitDev1 = 0x40000011,
.EmcZcalInitWait = 0x00000003,
.EmcZcalWarmColdBootEnables = 0x00000003,
.EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab,
.EmcZqCalDdr3WarmBoot = 0x00000000,
.EmcZcalWarmBootWait = 0x00000002,
.EmcMrsWarmBootEnable = 0x00000001,
.EmcMrsResetDllWait = 0x00000000,
.EmcMrsExtra = 0x00001221,
.EmcWarmBootMrsExtra = 0x00100003,
.EmcEmrsDdr2DllEnable = 0x00000000,
.EmcMrsDdr2DllReset = 0x00000000,
.EmcEmrsDdr2OcdCalib = 0x00000000,
.EmcDdr2Wait = 0x00000000,
.EmcClkenOverride = 0x00000000,
.McDisExtraSnapLevels = 0x00000000,
.EmcExtraRefreshNum = 0x00000002,
.EmcClkenOverrideAllWarmBoot = 0x00000000,
.McClkenOverrideAllWarmBoot = 0x00000000,
.EmcCfgDigDllPeriodWarmBoot = 0x00000003,
.PmcVddpSel = 0x00000002,
.PmcVddpSelWait = 0x00000002,
.PmcDdrPwr = 0x00000003,
.PmcDdrCfg = 0x00002002,
.PmcIoDpd3Req = 0x4fffffff,
.PmcIoDpd3ReqWait = 0x00000000,
.PmcRegShort = 0x00000000,
.PmcNoIoPower = 0x00000000,
.PmcPorDpdCtrlWait = 0x00000000,
.EmcXm2CmdPadCtrl = 0x10000280,
.EmcXm2CmdPadCtrl2 = 0x770c0000,
.EmcXm2CmdPadCtrl3 = 0x050c0000,
.EmcXm2CmdPadCtrl4 = 0x00000000,
.EmcXm2CmdPadCtrl5 = 0x00111111,
.EmcXm2DqsPadCtrl = 0x770c1414,
.EmcXm2DqsPadCtrl2 = 0x0130b118,
.EmcXm2DqsPadCtrl3 = 0x51451400,
.EmcXm2DqsPadCtrl4 = 0x00514514,
.EmcXm2DqsPadCtrl5 = 0x00514514,
.EmcXm2DqsPadCtrl6 = 0x51451400,
.EmcXm2DqPadCtrl = 0x770c2990,
.EmcXm2DqPadCtrl2 = 0x00000000,
.EmcXm2DqPadCtrl3 = 0x00000000,
.EmcXm2ClkPadCtrl = 0x77ffc081,
.EmcXm2ClkPadCtrl2 = 0x00000303,
.EmcXm2CompPadCtrl = 0x81f1f108,
.EmcXm2VttGenPadCtrl = 0x07070004,
.EmcXm2VttGenPadCtrl2 = 0x0000003f,
.EmcXm2VttGenPadCtrl3 = 0x016eeeee,
.EmcAcpdControl = 0x00000000,
.EmcSwizzleRank0ByteCfg = 0x00003120,
.EmcSwizzleRank0Byte0 = 0x25143067,
.EmcSwizzleRank0Byte1 = 0x45367102,
.EmcSwizzleRank0Byte2 = 0x47106253,
.EmcSwizzleRank0Byte3 = 0x04362175,
.EmcSwizzleRank1ByteCfg = 0x00003120,
.EmcSwizzleRank1Byte0 = 0x71546032,
.EmcSwizzleRank1Byte1 = 0x35104276,
.EmcSwizzleRank1Byte2 = 0x27043615,
.EmcSwizzleRank1Byte3 = 0x72306145,
.EmcDsrVttgenDrv = 0x0000003f,
.EmcTxdsrvttgen = 0x00000066,
.EmcBgbiasCtl0 = 0x00000008,
.McEmemAdrCfg = 0x00000001,
.McEmemAdrCfgDev0 = 0x00080303,
.McEmemAdrCfgDev1 = 0x00080303,
.McEmemAdrCfgBankMask0 = 0x00001248,
.McEmemAdrCfgBankMask1 = 0x00002490,
.McEmemAdrCfgBankMask2 = 0x00000920,
.McEmemAdrCfgBankSwizzle3 = 0x00000001,
.McEmemCfg = 0x00001000,
.McEmemArbCfg = 0x01000003,
.McEmemArbOutstandingReq = 0x80000040,
.McEmemArbTimingRcd = 0x00000001,
.McEmemArbTimingRp = 0x00000001,
.McEmemArbTimingRc = 0x00000005,
.McEmemArbTimingRas = 0x00000002,
.McEmemArbTimingFaw = 0x00000004,
.McEmemArbTimingRrd = 0x00000001,
.McEmemArbTimingRap2Pre = 0x00000002,
.McEmemArbTimingWap2Pre = 0x00000008,
.McEmemArbTimingR2R = 0x00000003,
.McEmemArbTimingW2W = 0x00000002,
.McEmemArbTimingR2W = 0x00000004,
.McEmemArbTimingW2R = 0x00000006,
.McEmemArbDaTurns = 0x06040203,
.McEmemArbDaCovers = 0x000a0405,
.McEmemArbMisc0 = 0x74a40a06,
.McEmemArbMisc1 = 0x70000f03,
.McEmemArbRing1Throttle = 0x001f0000,
.McEmemArbOverride = 0x10000000,
.McEmemArbOverride1 = 0x00000000,
.McEmemArbRsv = 0xff00ff00,
.McClkenOverride = 0x00000000,
.McStatControl = 0x00000000,
.McDisplaySnapRing = 0x00000003,
.McVideoProtectBom = 0xfff00000,
.McVideoProtectBomAdrHi = 0x00000000,
.McVideoProtectSizeMb = 0x00000000,
.McVideoProtectVprOverride = 0xe4bac743,
.McVideoProtectVprOverride1 = 0x00000013,
.McVideoProtectGpuOverride0 = 0x00000000,
.McVideoProtectGpuOverride1 = 0x00000000,
.McSecCarveoutBom = 0xfff00000,
.McSecCarveoutAdrHi = 0x00000000,
.McSecCarveoutSizeMb = 0x00000000,
.McVideoProtectWriteAccess = 0x00000000,
.McSecCarveoutProtectWriteAccess = 0x00000000,
.EmcCaTrainingEnable = 0x00000000,
.EmcCaTrainingTimingCntl1 = 0x1f7df7df,
.EmcCaTrainingTimingCntl2 = 0x0000001f,
.SwizzleRankByteEncode = 0x0000006f,
.BootRomPatchControl = 0x00000000,
.BootRomPatchData = 0x00000000,
.McMtsCarveoutBom = 0xfff00000,
.McMtsCarveoutAdrHi = 0x00000000,
.McMtsCarveoutSizeMb = 0x00000000,
.McMtsCarveoutRegCtrl = 0x00000000,
},

311
src/mainboard/google/nyan_big/bct/sdram-hynix-4GB-792.inc Normal file
View File

@ -0,0 +1,311 @@
{ /* generated from sdram-0100-792-4GB.cfg; do not edit. */
.MemoryType = NvBootMemoryType_Ddr3,
.PllMInputDivider = 0x00000001,
.PllMFeedbackDivider = 0x00000042,
.PllMStableTime = 0x0000012c,
.PllMSetupControl = 0x00000000,
.PllMSelectDiv2 = 0x00000000,
.PllMPDLshiftPh45 = 0x00000001,
.PllMPDLshiftPh90 = 0x00000001,
.PllMPDLshiftPh135 = 0x00000001,
.PllMKCP = 0x00000000,
.PllMKVCO = 0x00000000,
.EmcBctSpare0 = 0x00000000,
.EmcBctSpare1 = 0x00000000,
.EmcBctSpare2 = 0x00000000,
.EmcBctSpare3 = 0x00000000,
.EmcBctSpare4 = 0x00000000,
.EmcBctSpare5 = 0x00000000,
.EmcBctSpare6 = 0x00000000,
.EmcBctSpare7 = 0x00000000,
.EmcBctSpare8 = 0x00000000,
.EmcBctSpare9 = 0x00000000,
.EmcBctSpare10 = 0x00000000,
.EmcBctSpare11 = 0x00000000,
.EmcClockSource = 0x80000000,
.EmcAutoCalInterval = 0x001fffff,
.EmcAutoCalConfig = 0xa1430000,
.EmcAutoCalConfig2 = 0x00000000,
.EmcAutoCalConfig3 = 0x00000000,
.EmcAutoCalWait = 0x00000190,
.EmcAdrCfg = 0x00000001,
.EmcPinProgramWait = 0x00000001,
.EmcPinExtraWait = 0x00000000,
.EmcTimingControlWait = 0x00000000,
.EmcRc = 0x00000025,
.EmcRfc = 0x00000114,
.EmcRfcSlr = 0x00000000,
.EmcRas = 0x0000001a,
.EmcRp = 0x00000007,
.EmcR2r = 0x00000000,
.EmcW2w = 0x00000000,
.EmcR2w = 0x00000008,
.EmcW2r = 0x0000000d,
.EmcR2p = 0x00000004,
.EmcW2p = 0x00000013,
.EmcRdRcd = 0x00000009,
.EmcWrRcd = 0x00000009,
.EmcRrd = 0x00000003,
.EmcRext = 0x00000002,
.EmcWext = 0x00000000,
.EmcWdv = 0x00000006,
.EmcWdvMask = 0x00000006,
.EmcQUse = 0x0000000b,
.EmcQuseWidth = 0x00000002,
.EmcIbdly = 0x00000000,
.EmcEInput = 0x00000002,
.EmcEInputDuration = 0x0000000d,
.EmcPutermExtra = 0x00080000,
.EmcPutermWidth = 0x00000004,
.EmcPutermAdj = 0x00000000,
.EmcCdbCntl1 = 0x00000000,
.EmcCdbCntl2 = 0x00000000,
.EmcCdbCntl3 = 0x00000000,
.EmcQRst = 0x00000001,
.EmcQSafe = 0x00000014,
.EmcRdv = 0x00000018,
.EmcRdvMask = 0x0000001a,
.EmcQpop = 0x0000000f,
.EmcCtt = 0x00000000,
.EmcCttDuration = 0x00000004,
.EmcRefresh = 0x000017e2,
.EmcBurstRefreshNum = 0x00000000,
.EmcPreRefreshReqCnt = 0x000005f8,
.EmcPdEx2Wr = 0x00000003,
.EmcPdEx2Rd = 0x00000011,
.EmcPChg2Pden = 0x00000001,
.EmcAct2Pden = 0x00000000,
.EmcAr2Pden = 0x0000010d,
.EmcRw2Pden = 0x00000018,
.EmcTxsr = 0x0000011e,
.EmcTxsrDll = 0x00000200,
.EmcTcke = 0x00000005,
.EmcTckesr = 0x00000006,
.EmcTpd = 0x00000005,
.EmcTfaw = 0x0000001d,
.EmcTrpab = 0x00000000,
.EmcTClkStable = 0x00000008,
.EmcTClkStop = 0x00000008,
.EmcTRefBw = 0x00001822,
.EmcFbioCfg5 = 0x104ab098,
.EmcFbioCfg6 = 0x00000000,
.EmcFbioSpare = 0x00000000,
.EmcCfgRsv = 0xff00ff00,
.EmcMrs = 0x00000d71,
.EmcEmrs = 0x00100002,
.EmcEmrs2 = 0x00200018,
.EmcEmrs3 = 0x00300000,
.EmcMrw1 = 0x00000000,
.EmcMrw2 = 0x00000000,
.EmcMrw3 = 0x00000000,
.EmcMrw4 = 0x00000000,
.EmcMrwExtra = 0x00000000,
.EmcWarmBootMrwExtra = 0x00000000,
.EmcWarmBootExtraModeRegWriteEnable = 0x00000000,
.EmcExtraModeRegWriteEnable = 0x00000000,
.EmcMrwResetCommand = 0x00000000,
.EmcMrwResetNInitWait = 0x00000000,
.EmcMrsWaitCnt = 0x006f000c,
.EmcMrsWaitCnt2 = 0x006f000c,
.EmcCfg = 0x73300000,
.EmcCfg2 = 0x0000089d,
.EmcCfgPipe = 0x00004080,
.EmcDbg = 0x01000c00,
.EmcCmdQ = 0x10004408,
.EmcMc2EmcQ = 0x06000404,
.EmcDynSelfRefControl = 0x80003012,
.AhbArbitrationXbarCtrlMemInitDone = 0x00000001,
.EmcCfgDigDll = 0xe00700b1,
.EmcCfgDigDllPeriod = 0x00008000,
.EmcDevSelect = 0x00000000,
.EmcSelDpdCtrl = 0x00040000,
.EmcDllXformDqs0 = 0x00000008,
.EmcDllXformDqs1 = 0x00000008,
.EmcDllXformDqs2 = 0x00000008,
.EmcDllXformDqs3 = 0x00000008,
.EmcDllXformDqs4 = 0x00000008,
.EmcDllXformDqs5 = 0x00000008,
.EmcDllXformDqs6 = 0x00000008,
.EmcDllXformDqs7 = 0x00000008,
.EmcDllXformDqs8 = 0x00000008,
.EmcDllXformDqs9 = 0x00000008,
.EmcDllXformDqs10 = 0x00000008,
.EmcDllXformDqs11 = 0x00000008,
.EmcDllXformDqs12 = 0x00000008,
.EmcDllXformDqs13 = 0x00000008,
.EmcDllXformDqs14 = 0x00000008,
.EmcDllXformDqs15 = 0x00000008,
.EmcDllXformQUse0 = 0x00000000,
.EmcDllXformQUse1 = 0x00000000,
.EmcDllXformQUse2 = 0x00000000,
.EmcDllXformQUse3 = 0x00000000,
.EmcDllXformQUse4 = 0x00000000,
.EmcDllXformQUse5 = 0x00000000,
.EmcDllXformQUse6 = 0x00000000,
.EmcDllXformQUse7 = 0x00000000,
.EmcDllXformAddr0 = 0x00034000,
.EmcDllXformAddr1 = 0x00034000,
.EmcDllXformAddr2 = 0x00000000,
.EmcDllXformAddr3 = 0x00034000,
.EmcDllXformAddr4 = 0x00034000,
.EmcDllXformAddr5 = 0x00000000,
.EmcDllXformQUse8 = 0x00000000,
.EmcDllXformQUse9 = 0x00000000,
.EmcDllXformQUse10 = 0x00000000,
.EmcDllXformQUse11 = 0x00000000,
.EmcDllXformQUse12 = 0x00000000,
.EmcDllXformQUse13 = 0x00000000,
.EmcDllXformQUse14 = 0x00000000,
.EmcDllXformQUse15 = 0x00000000,
.EmcDliTrimTxDqs0 = 0x00000008,
.EmcDliTrimTxDqs1 = 0x00000008,
.EmcDliTrimTxDqs2 = 0x00000005,
.EmcDliTrimTxDqs3 = 0x00000009,
.EmcDliTrimTxDqs4 = 0x00000009,
.EmcDliTrimTxDqs5 = 0x00000007,
.EmcDliTrimTxDqs6 = 0x00000009,
.EmcDliTrimTxDqs7 = 0x00000008,
.EmcDliTrimTxDqs8 = 0x00000008,
.EmcDliTrimTxDqs9 = 0x00000008,
.EmcDliTrimTxDqs10 = 0x00000005,
.EmcDliTrimTxDqs11 = 0x00000009,
.EmcDliTrimTxDqs12 = 0x00000009,
.EmcDliTrimTxDqs13 = 0x00000007,
.EmcDliTrimTxDqs14 = 0x00000009,
.EmcDliTrimTxDqs15 = 0x00000008,
.EmcDllXformDq0 = 0x0000000e,
.EmcDllXformDq1 = 0x0000000e,
.EmcDllXformDq2 = 0x0000000e,
.EmcDllXformDq3 = 0x0000000e,
.EmcDllXformDq4 = 0x0000000e,
.EmcDllXformDq5 = 0x0000000e,
.EmcDllXformDq6 = 0x0000000e,
.EmcDllXformDq7 = 0x0000000e,
.WarmBootWait = 0x00000002,
.EmcCttTermCtrl = 0x00000802,
.EmcOdtWrite = 0x00000000,
.EmcOdtRead = 0x00000000,
.EmcZcalInterval = 0x00020000,
.EmcZcalWaitCnt = 0x00000042,
.EmcZcalMrwCmd = 0x00000000,
.EmcMrsResetDll = 0x00000000,
.EmcZcalInitDev0 = 0x80000011,
.EmcZcalInitDev1 = 0x40000011,
.EmcZcalInitWait = 0x00000001,
.EmcZcalWarmColdBootEnables = 0x00000003,
.EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab,
.EmcZqCalDdr3WarmBoot = 0x00000000,
.EmcZcalWarmBootWait = 0x00000001,
.EmcMrsWarmBootEnable = 0x00000001,
.EmcMrsResetDllWait = 0x00000000,
.EmcMrsExtra = 0x00000d71,
.EmcWarmBootMrsExtra = 0x00100002,
.EmcEmrsDdr2DllEnable = 0x00000000,
.EmcMrsDdr2DllReset = 0x00000000,
.EmcEmrsDdr2OcdCalib = 0x00000000,
.EmcDdr2Wait = 0x00000000,
.EmcClkenOverride = 0x00000000,
.McDisExtraSnapLevels = 0x00000000,
.EmcExtraRefreshNum = 0x00000002,
.EmcClkenOverrideAllWarmBoot = 0x00000000,
.McClkenOverrideAllWarmBoot = 0x00000000,
.EmcCfgDigDllPeriodWarmBoot = 0x00000003,
.PmcVddpSel = 0x00000002,
.PmcVddpSelWait = 0x00000002,
.PmcDdrPwr = 0x00000003,
.PmcDdrCfg = 0x00002002,
.PmcIoDpd3Req = 0x4fffffff,
.PmcIoDpd3ReqWait = 0x00000000,
.PmcRegShort = 0x00000000,
.PmcNoIoPower = 0x00000000,
.PmcPorDpdCtrlWait = 0x00000000,
.EmcXm2CmdPadCtrl = 0x100002a0,
.EmcXm2CmdPadCtrl2 = 0x770c0000,
.EmcXm2CmdPadCtrl3 = 0x050c0000,
.EmcXm2CmdPadCtrl4 = 0x00000000,
.EmcXm2CmdPadCtrl5 = 0x00111111,
.EmcXm2DqsPadCtrl = 0x770c1414,
.EmcXm2DqsPadCtrl2 = 0x0120113d,
.EmcXm2DqsPadCtrl3 = 0x61861820,
.EmcXm2DqsPadCtrl4 = 0x00514514,
.EmcXm2DqsPadCtrl5 = 0x00514514,
.EmcXm2DqsPadCtrl6 = 0x61861800,
.EmcXm2DqPadCtrl = 0x770c2990,
.EmcXm2DqPadCtrl2 = 0x00000000,
.EmcXm2DqPadCtrl3 = 0x00000000,
.EmcXm2ClkPadCtrl = 0x77ffc085,
.EmcXm2ClkPadCtrl2 = 0x00000101,
.EmcXm2CompPadCtrl = 0x81f1f108,
.EmcXm2VttGenPadCtrl = 0x07070004,
.EmcXm2VttGenPadCtrl2 = 0x00000000,
.EmcXm2VttGenPadCtrl3 = 0x016eeeee,
.EmcAcpdControl = 0x00000000,
.EmcSwizzleRank0ByteCfg = 0x00003120,
.EmcSwizzleRank0Byte0 = 0x25143067,
.EmcSwizzleRank0Byte1 = 0x45367102,
.EmcSwizzleRank0Byte2 = 0x47106253,
.EmcSwizzleRank0Byte3 = 0x04362175,
.EmcSwizzleRank1ByteCfg = 0x00003120,
.EmcSwizzleRank1Byte0 = 0x71546032,
.EmcSwizzleRank1Byte1 = 0x35104276,
.EmcSwizzleRank1Byte2 = 0x27043615,
.EmcSwizzleRank1Byte3 = 0x72306145,
.EmcDsrVttgenDrv = 0x0606003f,
.EmcTxdsrvttgen = 0x00000000,
.EmcBgbiasCtl0 = 0x00000000,
.McEmemAdrCfg = 0x00000001,
.McEmemAdrCfgDev0 = 0x00080303,
.McEmemAdrCfgDev1 = 0x00080303,
.McEmemAdrCfgBankMask0 = 0x00001248,
.McEmemAdrCfgBankMask1 = 0x00002490,
.McEmemAdrCfgBankMask2 = 0x00000920,
.McEmemAdrCfgBankSwizzle3 = 0x00000001,
.McEmemCfg = 0x00001000,
.McEmemArbCfg = 0x0e00000b,
.McEmemArbOutstandingReq = 0x80000040,
.McEmemArbTimingRcd = 0x00000004,
.McEmemArbTimingRp = 0x00000004,
.McEmemArbTimingRc = 0x00000013,
.McEmemArbTimingRas = 0x0000000c,
.McEmemArbTimingFaw = 0x0000000f,
.McEmemArbTimingRrd = 0x00000002,
.McEmemArbTimingRap2Pre = 0x00000003,
.McEmemArbTimingWap2Pre = 0x0000000c,
.McEmemArbTimingR2R = 0x00000002,
.McEmemArbTimingW2W = 0x00000002,
.McEmemArbTimingR2W = 0x00000006,
.McEmemArbTimingW2R = 0x00000008,
.McEmemArbDaTurns = 0x08060202,
.McEmemArbDaCovers = 0x00150c13,
.McEmemArbMisc0 = 0x746c2414,
.McEmemArbMisc1 = 0x70000f02,
.McEmemArbRing1Throttle = 0x001f0000,
.McEmemArbOverride = 0x10000000,
.McEmemArbOverride1 = 0x00000000,
.McEmemArbRsv = 0xff00ff00,
.McClkenOverride = 0x00000000,
.McStatControl = 0x00000000,
.McDisplaySnapRing = 0x00000003,
.McVideoProtectBom = 0xfff00000,
.McVideoProtectBomAdrHi = 0x00000000,
.McVideoProtectSizeMb = 0x00000000,
.McVideoProtectVprOverride = 0xe4bac743,
.McVideoProtectVprOverride1 = 0x00000013,
.McVideoProtectGpuOverride0 = 0x00000000,
.McVideoProtectGpuOverride1 = 0x00000000,
.McSecCarveoutBom = 0xfff00000,
.McSecCarveoutAdrHi = 0x00000000,
.McSecCarveoutSizeMb = 0x00000000,
.McVideoProtectWriteAccess = 0x00000000,
.McSecCarveoutProtectWriteAccess = 0x00000000,
.EmcCaTrainingEnable = 0x00000000,
.EmcCaTrainingTimingCntl1 = 0x1f7df7df,
.EmcCaTrainingTimingCntl2 = 0x0000001f,
.SwizzleRankByteEncode = 0x0000006f,
.BootRomPatchControl = 0x00000000,
.BootRomPatchData = 0x00000000,
.McMtsCarveoutBom = 0xfff00000,
.McMtsCarveoutAdrHi = 0x00000000,
.McMtsCarveoutSizeMb = 0x00000000,
.McMtsCarveoutRegCtrl = 0x00000000,
},

4
src/mainboard/google/nyan_big/bct/sdram-unused.inc Normal file
View File

@ -0,0 +1,4 @@
{ /* dummy. */
.MemoryType = NvBootMemoryType_Unused,
0,
},

18
src/mainboard/google/nyan_big/bct/spi.cfg
View File

@ -14,3 +14,21 @@ DeviceParam[0].SpiFlashParams.ClockDivider = 0x16;
DeviceParam[0].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0; DeviceParam[0].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0;
DeviceParam[0].SpiFlashParams.PageSize2kor16k = 0; DeviceParam[0].SpiFlashParams.PageSize2kor16k = 0;
DevType[1] = NvBootDevType_Spi;
DeviceParam[1].SpiFlashParams.ReadCommandTypeFast = NV_FALSE;
DeviceParam[1].SpiFlashParams.ClockDivider = 0x16;
DeviceParam[1].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0;
DeviceParam[1].SpiFlashParams.PageSize2kor16k = 0;
DevType[2] = NvBootDevType_Spi;
DeviceParam[2].SpiFlashParams.ReadCommandTypeFast = NV_FALSE;
DeviceParam[2].SpiFlashParams.ClockDivider = 0x16;
DeviceParam[2].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0;
DeviceParam[2].SpiFlashParams.PageSize2kor16k = 0;
DevType[3] = NvBootDevType_Spi;
DeviceParam[3].SpiFlashParams.ReadCommandTypeFast = NV_FALSE;
DeviceParam[3].SpiFlashParams.ClockDivider = 0x16;
DeviceParam[3].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0;
DeviceParam[3].SpiFlashParams.PageSize2kor16k = 0;

17
src/mainboard/google/nyan_big/boardid.c
View File

@ -19,6 +19,7 @@
#include <console/console.h> #include <console/console.h>
#include <soc/nvidia/tegra124/gpio.h> #include <soc/nvidia/tegra124/gpio.h>
#include <stdlib.h>
#include "boardid.h" #include "boardid.h"
@ -27,11 +28,17 @@ uint8_t board_id(void)
static int id = -1; static int id = -1;
if (id < 0) { if (id < 0) {
id = gpio_get_in_value(GPIO(Q3)) << 0 | gpio_t gpio[] = {GPIO(Q3), GPIO(T1), GPIO(X1), GPIO(X4)};
gpio_get_in_value(GPIO(T1)) << 1 | int value[ARRAY_SIZE(gpio)];
gpio_get_in_value(GPIO(X1)) << 2 |
gpio_get_in_value(GPIO(X4)) << 3; gpio_get_in_tristate_values(gpio, ARRAY_SIZE(gpio), value);
printk(BIOS_SPEW, "Board ID: %#x.\n", id);
/* A gpio state is encoded in every two-bit */
id = value[0] << 0 |
value[1] << 2 |
value[2] << 4 |
value[3] << 6;
printk(BIOS_SPEW, "Board TRISTATE ID: %#x.\n", id);
} }
return id; return id;

18
src/mainboard/google/nyan_big/bootblock.c
View File

@ -72,17 +72,19 @@ void bootblock_mainboard_init(void)
pmic_init(4); pmic_init(4);
/* SPI4 data out (MOSI) */ /* SPI4 data out (MOSI) */
pinmux_set_config(PINMUX_SDMMC1_CMD_INDEX, pinmux_set_config(PINMUX_GPIO_PG6_INDEX,
PINMUX_SDMMC1_CMD_FUNC_SPI4 | PINMUX_INPUT_ENABLE); PINMUX_GPIO_PG6_FUNC_SPI4 | PINMUX_INPUT_ENABLE |
PINMUX_PULL_UP);
/* SPI4 data in (MISO) */ /* SPI4 data in (MISO) */
pinmux_set_config(PINMUX_SDMMC1_DAT1_INDEX, pinmux_set_config(PINMUX_GPIO_PG7_INDEX,
PINMUX_SDMMC1_DAT1_FUNC_SPI4 | PINMUX_INPUT_ENABLE); PINMUX_GPIO_PG7_FUNC_SPI4 | PINMUX_INPUT_ENABLE |
PINMUX_PULL_UP);
/* SPI4 clock */ /* SPI4 clock */
pinmux_set_config(PINMUX_SDMMC1_DAT2_INDEX, pinmux_set_config(PINMUX_GPIO_PG5_INDEX,
PINMUX_SDMMC1_DAT2_FUNC_SPI4 | PINMUX_INPUT_ENABLE); PINMUX_GPIO_PG5_FUNC_SPI4 | PINMUX_INPUT_ENABLE);
/* SPI4 chip select 0 */ /* SPI4 chip select 0 */
pinmux_set_config(PINMUX_SDMMC1_DAT3_INDEX, pinmux_set_config(PINMUX_GPIO_PI3_INDEX,
PINMUX_SDMMC1_DAT3_FUNC_SPI4 | PINMUX_INPUT_ENABLE); PINMUX_GPIO_PI3_FUNC_SPI4 | PINMUX_INPUT_ENABLE);
tegra_spi_init(4); tegra_spi_init(4);
} }

5
src/mainboard/google/nyan_big/pmic.c
View File

@ -83,10 +83,7 @@ void pmic_init(unsigned bus)
pmic_slam_defaults(bus); pmic_slam_defaults(bus);
/* First set VDD_CPU to 1.2V, then enable the VDD_CPU regulator. */ /* First set VDD_CPU to 1.2V, then enable the VDD_CPU regulator. */
if (board_id() == 0) pmic_write_reg(bus, 0x00, 0x50);
pmic_write_reg(bus, 0x00, 0x3c);
else
pmic_write_reg(bus, 0x00, 0x50);
/* First set VDD_GPU to 1.0V, then enable the VDD_GPU regulator. */ /* First set VDD_GPU to 1.0V, then enable the VDD_GPU regulator. */
pmic_write_reg(bus, 0x06, 0x28); pmic_write_reg(bus, 0x06, 0x28);

22
src/mainboard/google/nyan_big/romstage.c
View File

@ -25,15 +25,12 @@
#include <cbfs.h> #include <cbfs.h>
#include <cbmem.h> #include <cbmem.h>
#include <console/console.h> #include <console/console.h>
#include "sdram_configs.h"
#include "soc/nvidia/tegra124/chip.h" #include "soc/nvidia/tegra124/chip.h"
#include "soc/nvidia/tegra124/sdram.h"
#include <soc/display.h> #include <soc/display.h>
#include <timestamp.h> #include <timestamp.h>
// Convenient shorthand (in MB)
#define DRAM_START (CONFIG_SYS_SDRAM_BASE >> 20)
#define DRAM_SIZE CONFIG_DRAM_SIZE_MB
#define DRAM_END (DRAM_START + DRAM_SIZE) /* plus one... */
enum { enum {
L2CTLR_ECC_PARITY = 0x1 << 21, L2CTLR_ECC_PARITY = 0x1 << 21,
L2CTLR_TAG_RAM_LATENCY_MASK = 0x7 << 6, L2CTLR_TAG_RAM_LATENCY_MASK = 0x7 << 6,
@ -74,6 +71,7 @@ static void configure_l2actlr(void)
void main(void) void main(void)
{ {
int dram_size_mb;
#if CONFIG_COLLECT_TIMESTAMPS #if CONFIG_COLLECT_TIMESTAMPS
uint64_t romstage_start_time = timestamp_get(); uint64_t romstage_start_time = timestamp_get();
#endif #endif
@ -97,12 +95,20 @@ void main(void)
console_init(); console_init();
exception_init(); exception_init();
sdram_init(get_sdram_config());
/* used for MMU and CBMEM setup */
dram_size_mb = sdram_size_mb();
u32 dram_start = (CONFIG_SYS_SDRAM_BASE >> 20);
u32 dram_end = dram_start + dram_size_mb; /* plus one... */
mmu_init(); mmu_init();
mmu_config_range(0, DRAM_START, DCACHE_OFF); mmu_config_range(0, dram_start, DCACHE_OFF);
mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK); mmu_config_range(dram_start, dram_size_mb, DCACHE_WRITEBACK);
mmu_config_range(CONFIG_DRAM_DMA_START >> 20, mmu_config_range(CONFIG_DRAM_DMA_START >> 20,
CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF); CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF);
mmu_config_range(DRAM_END, 4096 - DRAM_END, DCACHE_OFF); mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF);
mmu_disable_range(0, 1); mmu_disable_range(0, 1);
dcache_invalidate_all(); dcache_invalidate_all();
dcache_mmu_enable(); dcache_mmu_enable();

62
src/mainboard/google/nyan_big/sdram_configs.c Normal file
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@ -0,0 +1,62 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <console/console.h>
#include <soc/nvidia/tegra124/sdram.h>
#include "sdram_configs.h"
/*
* Note for board bring up, we've temporarily filled SDRAM table with
* hynix-2GB-204 configuration (except the hynix-4GB-204 entry for 0100).
*/
static struct sdram_params sdram_configs[] = {
#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 0000 */
#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 0001 */
#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 0010 */
#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 0011 */
#include "bct/sdram-hynix-4GB-204.inc" /* ram_code = 0100 */
#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 0101 */
#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 0110 */
#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 0111 */
#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 1000 */
#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 1001 */
#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 1010 */
#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 1011 */
#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 1100 */
#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 1101 */
#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 1110 */
#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 1111 */
};
const struct sdram_params *get_sdram_config()
{
uint32_t ramcode = sdram_get_ram_code();
/*
* If we need to apply some special hacks to RAMCODE mapping (ex, by
* board_id), do that now.
*/
printk(BIOS_SPEW, "%s: RAMCODE=%d\n", __func__, ramcode);
if (ramcode >= sizeof(sdram_configs) / sizeof(sdram_configs[0]) ||
sdram_configs[ramcode].MemoryType == NvBootMemoryType_Unused) {
die("Invalid RAMCODE.");
}
return &sdram_configs[ramcode];
}

28
src/mainboard/google/nyan_big/sdram_configs.h Normal file
View File

@ -0,0 +1,28 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __MAINBOARD_GOOGLE_NYAN_BIG_SDRAM_CONFIG_H__
#define __MAINBOARD_GOOGLE_NYAN_BIG_SDRAM_CONFIG_H__
#include <soc/nvidia/tegra124/sdram_param.h>
/* Loads SDRAM configurations for current system. */
const struct sdram_params *get_sdram_config(void);
#endif /* __MAINBOARD_GOOGLE_NYAN_BIG_SDRAM_CONFIG_H__ */

3
src/soc/nvidia/tegra/dc.h
View File

@ -569,4 +569,7 @@ struct disp_ctl_win {
void display_startup(device_t dev); void display_startup(device_t dev);
void dp_bringup(u32 winb_addr); void dp_bringup(u32 winb_addr);
unsigned int fb_base_mb(void);
#endif /* __SOC_NVIDIA_TEGRA_DC_H */ #endif /* __SOC_NVIDIA_TEGRA_DC_H */

53
src/soc/nvidia/tegra/gpio.c
View File

@ -22,6 +22,7 @@
#include <soc/addressmap.h> #include <soc/addressmap.h>
#include <stddef.h> #include <stddef.h>
#include <stdint.h> #include <stdint.h>
#include <delay.h>
#include "gpio.h" #include "gpio.h"
#include "pinmux.h" #include "pinmux.h"
@ -174,6 +175,58 @@ int gpio_get_in_value(gpio_t gpio)
return (port & (1 << bit)) != 0; return (port & (1 << bit)) != 0;
} }
int gpio_get_in_tristate_values(gpio_t gpio[], int num_gpio, int value[])
{
/*
* GPIOs which are tied to stronger external pull up or pull down
* will stay there regardless of the internal pull up or pull
* down setting.
*
* GPIOs which are floating will go to whatever level they're
* internally pulled to.
*/
int temp;
int index;
/* Enable internal pull up */
for (index = 0; index < num_gpio; ++index)
gpio_input_pullup(gpio[index]);
/* Wait until signals become stable */
udelay(10);
/* Get gpio values at internal pull up */
for (index = 0; index < num_gpio; ++index)
value[index] = gpio_get_in_value(gpio[index]);
/* Enable internal pull down */
for (index = 0; index < num_gpio; ++index)
gpio_input_pulldown(gpio[index]);
/* Wait until signals become stable */
udelay(10);
/*
* Get gpio values at internal pull down.
* Compare with gpio pull up value and then
* determine a gpio final value/state:
* 0: pull down
* 1: pull up
* 2: floating
*/
for (index = 0; index < num_gpio; ++index) {
temp = gpio_get_in_value(gpio[index]);
value[index] = ((value[index] ^ temp) << 1) | temp;
}
/* Disable pull up / pull down to conserve power */
for (index = 0; index < num_gpio; ++index)
gpio_input(gpio[index]);
return 0;
}
int gpio_get_int_status(gpio_t gpio) int gpio_get_int_status(gpio_t gpio)
{ {
int bit = gpio % GPIO_GPIOS_PER_PORT; int bit = gpio % GPIO_GPIOS_PER_PORT;

1
src/soc/nvidia/tegra/gpio.h
View File

@ -81,6 +81,7 @@ void gpio_set_out_value(gpio_t gpio, int value);
int gpio_get_out_value(gpio_t gpio); int gpio_get_out_value(gpio_t gpio);
int gpio_get_in_value(gpio_t gpio); int gpio_get_in_value(gpio_t gpio);
int gpio_get_in_tristate_values(gpio_t gpio[], int num_gpio, int value[]);
int gpio_get_int_status(gpio_t gpio); int gpio_get_int_status(gpio_t gpio);

33
src/soc/nvidia/tegra124/Kconfig
View File

@ -26,17 +26,15 @@ config BOOTBLOCK_CPU_INIT
# 0x18080 Free for CBFS data. # 0x18080 Free for CBFS data.
# #
# iRAM (256k) layout. # iRAM (256k) layout.
# 0x4000_0000 BootROM runtime data/stack area, can be reclaimed after BootROM. # (Note: The BootROM uses the address range [0x4000_0000:0x4000_E000) itself,
# +0000 (BootROM) Boot Information Table. # so the bootblock loading address must be placed after that. After the
# +0100 (BootROM) BCT. # handoff that area may be reclaimed for other uses, e.g. CBFS cache.)
# --------------------------------------------------------------------- #
# +0000 (Coreboot) TTB 16KB. # 0x4000_0000 TTB (16KB).
# +4000 (Coreboot) Stack. # 0x4000_4000 CBFS mapping cache (96KB).
# 0x4000_E000 Valid for anything to be executed after BootROM (effective entry # 0x4001_C000 Stack (16KB... don't reduce without comparing LZMA scratchpad!).
# point address specified in BCT). # 0x4002_0000 Bootblock (max 48KB).
# +0000 (Coreboot) Bootblock (max 36k). # 0x4002_C000 ROM stage (max 80KB).
# +9000 (Coreboot) ROM stage (max 36k).
# 0x4002_0000 (Coreboot) Cache of CBFS.
# 0x4003_FFFF End of iRAM. # 0x4003_FFFF End of iRAM.
config BOOTBLOCK_ROM_OFFSET config BOOTBLOCK_ROM_OFFSET
@ -57,11 +55,11 @@ config SYS_SDRAM_BASE
config BOOTBLOCK_BASE config BOOTBLOCK_BASE
hex hex
default 0x4000e000 default 0x40020000
config ROMSTAGE_BASE config ROMSTAGE_BASE
hex hex
default 0x40017000 default 0x4002c000
config RAMSTAGE_BASE config RAMSTAGE_BASE
hex hex
@ -69,12 +67,13 @@ config RAMSTAGE_BASE
config STACK_TOP config STACK_TOP
hex hex
default 0x4000c000 default 0x40020000
config STACK_BOTTOM config STACK_BOTTOM
hex hex
default 0x40004000 default 0x4001c000
# This is the ramstage thread stack, *not* the same as above! Currently unused.
config STACK_SIZE config STACK_SIZE
hex hex
default 0x800 default 0x800
@ -86,10 +85,10 @@ config TTB_BUFFER
config CBFS_CACHE_ADDRESS config CBFS_CACHE_ADDRESS
hex "memory address to put CBFS cache data" hex "memory address to put CBFS cache data"
default 0x40020000 default 0x40004000
config CBFS_CACHE_SIZE config CBFS_CACHE_SIZE
hex "size of CBFS cache data" hex "size of CBFS cache data"
default 0x00020000 default 0x00018000
endif endif

2
src/soc/nvidia/tegra124/Makefile.inc
View File

@ -26,6 +26,7 @@ romstage-y += dma.c
romstage-y += i2c.c romstage-y += i2c.c
romstage-y += monotonic_timer.c romstage-y += monotonic_timer.c
romstage-y += sdram.c romstage-y += sdram.c
romstage-y += sdram_lp0.c
romstage-y += spi.c romstage-y += spi.c
romstage-y += ../tegra/gpio.c romstage-y += ../tegra/gpio.c
romstage-y += ../tegra/i2c.c romstage-y += ../tegra/i2c.c
@ -41,6 +42,7 @@ ramstage-y += dma.c
ramstage-y += i2c.c ramstage-y += i2c.c
ramstage-y += maincpu.S ramstage-y += maincpu.S
ramstage-y += monotonic_timer.c ramstage-y += monotonic_timer.c
ramstage-y += sdram.c
ramstage-y += soc.c ramstage-y += soc.c
ramstage-y += sor.c ramstage-y += sor.c
ramstage-y += spi.c ramstage-y += spi.c

5
src/soc/nvidia/tegra124/cbmem.c
View File

@ -18,10 +18,11 @@
*/ */
#include <cbmem.h> #include <cbmem.h>
#include <soc/addressmap.h> #include <soc/display.h>
#include <soc/nvidia/tegra124/sdram.h>
void *cbmem_top(void) void *cbmem_top(void)
{ {
return (void *)(CONFIG_SYS_SDRAM_BASE + return (void *)(CONFIG_SYS_SDRAM_BASE +
((CONFIG_DRAM_SIZE_MB - FB_SIZE_MB)<< 20UL)); ((sdram_size_mb() - FB_SIZE_MB)<< 20UL));
} }

8
src/soc/nvidia/tegra124/display.c
View File

@ -33,6 +33,7 @@
#include <edid.h> #include <edid.h>
#include <soc/clock.h> #include <soc/clock.h>
#include <soc/nvidia/tegra/dc.h> #include <soc/nvidia/tegra/dc.h>
#include <soc/nvidia/tegra124/sdram.h>
#include "chip.h" #include "chip.h"
#include <soc/display.h> #include <soc/display.h>
@ -225,6 +226,11 @@ static void update_window(struct display_controller *dc,
WRITEL(val, &dc->cmd.state_ctrl); WRITEL(val, &dc->cmd.state_ctrl);
} }
uint32_t fb_base_mb(void)
{
return CONFIG_SYS_SDRAM_BASE/MiB + (sdram_size_mb() - FB_SIZE_MB);
}
/* this is really aimed at the lcd panel. That said, there are two display /* this is really aimed at the lcd panel. That said, there are two display
* devices on this part and we may someday want to extend it for other boards. * devices on this part and we may someday want to extend it for other boards.
*/ */
@ -279,7 +285,7 @@ void display_startup(device_t dev)
} }
if (! framebuffer_base_mb) if (! framebuffer_base_mb)
framebuffer_base_mb = FB_BASE_MB; framebuffer_base_mb = fb_base_mb();
mmu_config_range(framebuffer_base_mb, framebuffer_size_mb, mmu_config_range(framebuffer_base_mb, framebuffer_size_mb,
config->cache_policy); config->cache_policy);

5
src/soc/nvidia/tegra124/include/soc/addressmap.h
View File

@ -80,9 +80,4 @@ enum {
TEGRA_I2C_BASE_COUNT = 6, TEGRA_I2C_BASE_COUNT = 6,
}; };
enum {
FB_SIZE_MB = (32),
FB_BASE_MB = (CONFIG_SYS_SDRAM_BASE/MiB + (CONFIG_DRAM_SIZE_MB - FB_SIZE_MB)),
};
#endif /* __SOC_NVIDIA_TEGRA124_INCLUDE_SOC_ADDRESS_MAP_H__ */ #endif /* __SOC_NVIDIA_TEGRA124_INCLUDE_SOC_ADDRESS_MAP_H__ */

4
src/soc/nvidia/tegra124/include/soc/display.h
View File

@ -188,6 +188,7 @@
#define COLORDEPTH 0x6 #define COLORDEPTH 0x6
#define COLOR_WHITE 0xFFFFFF #define COLOR_WHITE 0xFFFFFF
struct soc_nvidia_tegra124_config; /* forward declaration */
void setup_display(struct soc_nvidia_tegra124_config *config); void setup_display(struct soc_nvidia_tegra124_config *config);
void init_dca_regs(void); void init_dca_regs(void);
void dp_io_powerup(void); void dp_io_powerup(void);
@ -195,4 +196,7 @@ u32 dp_setup_timing(u32 width, u32 height);
void dp_misc_setting(u32 panel_bpp, u32 width, u32 height, u32 winb_addr, void dp_misc_setting(u32 panel_bpp, u32 width, u32 height, u32 winb_addr,
u32 lane_count, u32 enhanced_framing, u32 panel_edp, u32 lane_count, u32 enhanced_framing, u32 panel_edp,
u32 pclkfreq, u32 linkfreq); u32 pclkfreq, u32 linkfreq);
#define FB_SIZE_MB (32)
#endif /* __SOC_NVIDIA_TEGRA124_INCLUDE_SOC_DISPLAY_H__ */ #endif /* __SOC_NVIDIA_TEGRA124_INCLUDE_SOC_DISPLAY_H__ */

3
src/soc/nvidia/tegra124/mc.h
View File

@ -115,6 +115,9 @@ struct tegra_mc_regs {
}; };
enum { enum {
MC_EMEM_CFG_SIZE_MB_SHIFT = 0,
MC_EMEM_CFG_SIZE_MB_MASK = 0x3fff,
MC_EMEM_ARB_MISC0_MC_EMC_SAME_FREQ_SHIFT = 27, MC_EMEM_ARB_MISC0_MC_EMC_SAME_FREQ_SHIFT = 27,
MC_EMEM_ARB_MISC0_MC_EMC_SAME_FREQ_MASK = 1 << 27, MC_EMEM_ARB_MISC0_MC_EMC_SAME_FREQ_MASK = 1 << 27,

30
src/soc/nvidia/tegra124/sdram.c
View File

@ -568,6 +568,13 @@ void sdram_init(const struct sdram_params *param)
struct tegra_mc_regs *mc = (struct tegra_mc_regs*)TEGRA_MC_BASE; struct tegra_mc_regs *mc = (struct tegra_mc_regs*)TEGRA_MC_BASE;
struct tegra_emc_regs *emc = (struct tegra_emc_regs*)TEGRA_EMC_BASE; struct tegra_emc_regs *emc = (struct tegra_emc_regs*)TEGRA_EMC_BASE;
printk(BIOS_DEBUG, "Initializing SDRAM of type %d with %dKHz\n",
param->MemoryType, clock_get_osc_khz() *
param->PllMFeedbackDivider / param->PllMInputDivider /
(1 + param->PllMSelectDiv2));
if (param->MemoryType != NvBootMemoryType_Ddr3)
die("Unsupported memory type!\n");
sdram_configure_pmc(param, pmc); sdram_configure_pmc(param, pmc);
sdram_patch(param->EmcBctSpare0, param->EmcBctSpare1); sdram_patch(param->EmcBctSpare0, param->EmcBctSpare1);
@ -600,6 +607,8 @@ void sdram_init(const struct sdram_params *param)
sdram_set_refresh(param, emc); sdram_set_refresh(param, emc);
sdram_enable_arbiter(param); sdram_enable_arbiter(param);
sdram_lock_carveouts(param, mc); sdram_lock_carveouts(param, mc);
sdram_lp0_save_params(param);
} }
uint32_t sdram_get_ram_code(void) uint32_t sdram_get_ram_code(void)
@ -609,3 +618,24 @@ uint32_t sdram_get_ram_code(void)
PMC_STRAPPING_OPT_A_RAM_CODE_MASK) >> PMC_STRAPPING_OPT_A_RAM_CODE_MASK) >>
PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT); PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT);
} }
/* returns total amount of DRAM (in MB) from memory controller registers */
int sdram_size_mb(void)
{
struct tegra_mc_regs *mc = (struct tegra_mc_regs *)TEGRA_MC_BASE;
static int total_size = 0;
if (total_size)
return total_size;
/*
* This obtains memory size from the External Memory Aperture
* Configuration register. Nvidia confirmed that it is safe to assume
* this value represents the total physical DRAM size.
*/
total_size = (read32(&mc->emem_cfg) >>
MC_EMEM_CFG_SIZE_MB_SHIFT) & MC_EMEM_CFG_SIZE_MB_MASK;
printk(BIOS_DEBUG, "%s: Total SDRAM (MB): %u\n", __func__, total_size);
return total_size;
}

4
src/soc/nvidia/tegra124/sdram.h
View File

@ -24,5 +24,9 @@
uint32_t sdram_get_ram_code(void); uint32_t sdram_get_ram_code(void);
void sdram_init(const struct sdram_params *param); void sdram_init(const struct sdram_params *param);
int sdram_size_mb(void);
/* Save params to PMC scratch registers for use by BootROM on LP0 resume. */
void sdram_lp0_save_params(const struct sdram_params *sdram);
#endif /* __SOC_NVIDIA_TEGRA124_SDRAM_H__ */ #endif /* __SOC_NVIDIA_TEGRA124_SDRAM_H__ */

633
src/soc/nvidia/tegra124/sdram_lp0.c Normal file
View File

@ -0,0 +1,633 @@
/*
* Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <arch/cache.h>
#include <console/console.h>
#include <stdlib.h>
#include <soc/addressmap.h>
#include "clk_rst.h"
#include "pmc.h"
#include "sdram.h"
/*
* This function reads SDRAM parameters (and a few CLK_RST regsiter values) from
* the common BCT format and writes them into PMC scratch registers (where the
* BootROM expects them on LP0 resume). Since those store the same values in a
* different format, we follow a "translation table" taken from Nvidia's U-Boot
* implementation to shift bits into the right position.
*
* Contrary to U-Boot, we transform the same macros directly into hardcoded
* assignments (without any pesky function calls or volatile qualifiers) to give
* the compiler as much room for optimization as possible. For that reason, we
* also intentionally avoid <arch/io.h> read/write macros, under the assumption
* that PMC scratch register accesses should not have side effects and can be
* arbitrarily reordered. For the few accesses that do have side-effects, the
* code must contain explicit memory barriers.
*/
void sdram_lp0_save_params(const struct sdram_params *sdram)
{
struct tegra_pmc_regs * pmc = (void *)TEGRA_PMC_BASE;
struct clk_rst_ctlr * clk_rst = (void *)TEGRA_CLK_RST_BASE;
#define pack(src, src_bits, dst, dst_bits) { \
_Static_assert((1 ? src_bits) >= (0 ? src_bits) && (1 ? dst_bits) >= \
(0 ? dst_bits), "byte range flipped (must be MSB:LSB)" ); \
_Static_assert((1 ? src_bits) - (0 ? src_bits) == (1 ? dst_bits) - \
(0 ? dst_bits), "src and dst byte range lengths differ" ); \
u32 mask = 0xffffffff >> (31 - ((1 ? src_bits) - (0 ? src_bits))); \
dst &= ~(mask << (0 ? dst_bits)); \
dst |= ((src >> (0 ? src_bits)) & mask) << (0 ? dst_bits); \
}
#define s(param, src_bits, pmcreg, dst_bits) \
pack(sdram->param, src_bits, pmc->pmcreg, dst_bits)
#define m(clkreg, src_bits, pmcreg, dst_bits) \
pack(clk_rst->clkreg, src_bits, pmc->pmcreg, dst_bits)
#define c(value, pmcreg, dst_bits) \
pack(value, (1 ? dst_bits) - (0 ? dst_bits) : 0, pmc->pmcreg, dst_bits)
s(EmcClockSource, 7:0, scratch6, 15:8);
s(EmcClockSource, 31:29, scratch6, 18:16);
s(EmcClockSource, 26:26, scratch6, 19:19);
s(EmcOdtWrite, 5:0, scratch6, 25:20);
s(EmcOdtWrite, 11:8, scratch6, 29:26);
s(EmcOdtWrite, 30:30, scratch6, 30:30);
s(EmcOdtWrite, 31:31, scratch6, 31:31);
s(EmcXm2DqPadCtrl2, 18:16, scratch7, 22:20);
s(EmcXm2DqPadCtrl2, 22:20, scratch7, 25:23);
s(EmcXm2DqPadCtrl2, 26:24, scratch7, 28:26);
s(EmcXm2DqPadCtrl2, 30:28, scratch7, 31:29);
s(EmcXm2DqPadCtrl3, 18:16, scratch8, 22:20);
s(EmcXm2DqPadCtrl3, 22:20, scratch8, 25:23);
s(EmcXm2DqPadCtrl3, 26:24, scratch8, 28:26);
s(EmcXm2DqPadCtrl3, 30:28, scratch8, 31:29);
s(EmcTxsrDll, 11:0, scratch9, 31:20);
c(0, scratch10, 31:0);
s(EmcDsrVttgenDrv, 5:0, scratch10, 25:20);
s(EmcDsrVttgenDrv, 18:16, scratch10, 28:26);
s(EmcDsrVttgenDrv, 26:24, scratch10, 31:29);
s(EmcFbioSpare, 31:24, scratch11, 7:0);
s(EmcFbioSpare, 23:16, scratch11, 15:8);
s(EmcFbioSpare, 15:8, scratch11, 23:16);
s(EmcFbioSpare, 7:0, scratch11, 31:24);
s(EmcCfgRsv, 31:0, scratch12, 31:0);
s(EmcCdbCntl2, 31:0, scratch13, 31:0);
s(McEmemArbDaTurns, 31:0, scratch14, 31:0);
s(EmcCfgDigDll, 0:0, scratch17, 0:0);
s(EmcCfgDigDll, 25:2, scratch17, 24:1);
s(EmcCfgDigDll, 31:27, scratch17, 29:25);
s(EmcCdbCntl1, 29:0, scratch18, 29:0);
s(McEmemArbMisc0, 14:0, scratch19, 14:0);
s(McEmemArbMisc0, 30:16, scratch19, 29:15);
s(EmcXm2DqsPadCtrl, 4:0, scratch22, 4:0);
s(EmcXm2DqsPadCtrl, 12:8, scratch22, 9:5);
s(EmcXm2DqsPadCtrl, 31:14, scratch22, 27:10);
s(EmcRrd, 3:0, scratch22, 31:28);
s(EmcXm2DqPadCtrl, 31:4, scratch23, 27:0);
s(EmcRext, 3:0, scratch23, 31:28);
s(EmcXm2CompPadCtrl, 16:0, scratch24, 16:0);
s(EmcXm2CompPadCtrl, 24:20, scratch24, 21:17);
s(EmcXm2CompPadCtrl, 27:27, scratch24, 22:22);
s(EmcXm2CompPadCtrl, 31:28, scratch24, 26:23);
s(EmcR2w, 4:0, scratch24, 31:27);
s(EmcCfg, 9:1, scratch25, 8:0);
s(EmcCfg, 26:16, scratch25, 19:9);
s(EmcCfg, 31:28, scratch25, 23:20);
s(EmcXm2VttGenPadCtrl, 0:0, scratch25, 24:24);
s(EmcXm2VttGenPadCtrl, 2:2, scratch25, 25:25);
s(EmcXm2VttGenPadCtrl, 18:16, scratch25, 28:26);
s(EmcXm2VttGenPadCtrl, 26:24, scratch25, 31:29);
s(EmcZcalInterval, 23:10, scratch26, 13:0);
s(EmcZcalInterval, 9:0, scratch26, 23:14);
s(EmcSelDpdCtrl, 5:2, scratch26, 27:24);
s(EmcSelDpdCtrl, 8:8, scratch26, 28:28);
s(EmcSelDpdCtrl, 18:16, scratch26, 31:29);
s(EmcXm2VttGenPadCtrl3, 22:0, scratch27, 22:0);
s(EmcXm2VttGenPadCtrl3, 24:24, scratch27, 23:23);
s(EmcSwizzleRank0ByteCfg, 1:0, scratch27, 25:24);
s(EmcSwizzleRank0ByteCfg, 5:4, scratch27, 27:26);
s(EmcSwizzleRank0ByteCfg, 9:8, scratch27, 29:28);
s(EmcSwizzleRank0ByteCfg, 13:12, scratch27, 31:30);
s(EmcXm2ClkPadCtrl2, 5:0, scratch28, 5:0);
s(EmcXm2ClkPadCtrl2, 13:8, scratch28, 11:6);
s(EmcXm2ClkPadCtrl2, 20:16, scratch28, 16:12);
s(EmcXm2ClkPadCtrl2, 23:23, scratch28, 17:17);
s(EmcXm2ClkPadCtrl2, 28:24, scratch28, 22:18);
s(EmcXm2ClkPadCtrl2, 31:31, scratch28, 23:23);
s(EmcSwizzleRank1ByteCfg, 1:0, scratch28, 25:24);
s(EmcSwizzleRank1ByteCfg, 5:4, scratch28, 27:26);
s(EmcSwizzleRank1ByteCfg, 9:8, scratch28, 29:28);
s(EmcSwizzleRank1ByteCfg, 13:12, scratch28, 31:30);
s(McEmemArbDaCovers, 23:0, scratch29, 23:0);
s(McEmemArbRsv, 7:0, scratch29, 31:24);
s(EmcAutoCalConfig, 4:0, scratch30, 4:0);
s(EmcAutoCalConfig, 12:8, scratch30, 9:5);
s(EmcAutoCalConfig, 18:16, scratch30, 12:10);
s(EmcAutoCalConfig, 25:20, scratch30, 18:13);
s(EmcAutoCalConfig, 31:28, scratch30, 22:19);
s(EmcRfc, 8:0, scratch30, 31:23);
s(EmcXm2DqsPadCtrl2, 21:0, scratch31, 21:0);
s(EmcXm2DqsPadCtrl2, 24:24, scratch31, 22:22);
s(EmcAr2Pden, 8:0, scratch31, 31:23);
s(EmcXm2ClkPadCtrl, 0:0, scratch32, 0:0);
s(EmcXm2ClkPadCtrl, 4:2, scratch32, 3:1);
s(EmcXm2ClkPadCtrl, 7:7, scratch32, 4:4);
s(EmcXm2ClkPadCtrl, 31:14, scratch32, 22:5);
s(EmcRfcSlr, 8:0, scratch32, 31:23);
s(EmcXm2DqsPadCtrl3, 0:0, scratch33, 0:0);
s(EmcXm2DqsPadCtrl3, 5:5, scratch33, 1:1);
s(EmcXm2DqsPadCtrl3, 12:8, scratch33, 6:2);
s(EmcXm2DqsPadCtrl3, 18:14, scratch33, 11:7);
s(EmcXm2DqsPadCtrl3, 24:20, scratch33, 16:12);
s(EmcXm2DqsPadCtrl3, 30:26, scratch33, 21:17);
s(EmcTxsr, 9:0, scratch33, 31:22);
s(McEmemArbCfg, 8:0, scratch40, 8:0);
s(McEmemArbCfg, 20:16, scratch40, 13:9);
s(McEmemArbCfg, 27:24, scratch40, 17:14);
s(McEmemArbCfg, 31:28, scratch40, 21:18);
s(EmcMc2EmcQ, 2:0, scratch40, 24:22);
s(EmcMc2EmcQ, 10:8, scratch40, 27:25);
s(EmcMc2EmcQ, 27:24, scratch40, 31:28);
s(EmcAutoCalInterval, 20:0, scratch42, 20:0);
s(McEmemArbOutstandingReq, 8:0, scratch42, 29:21);
s(McEmemArbOutstandingReq, 31:30, scratch42, 31:30);
s(EmcMrsWaitCnt2, 9:0, scratch44, 9:0);
s(EmcMrsWaitCnt2, 25:16, scratch44, 19:10);
s(EmcTxdsrvttgen, 11:0, scratch44, 31:20);
s(EmcMrsWaitCnt, 9:0, scratch45, 9:0);
s(EmcMrsWaitCnt, 25:16, scratch45, 19:10);
s(EmcCfgPipe, 1:0, scratch45, 21:20);
s(EmcCfgPipe, 9:4, scratch45, 27:22);
s(EmcCfgPipe, 15:12, scratch45, 31:28);
s(EmcXm2DqsPadCtrl4, 22:18, scratch46, 4:0);
s(EmcXm2DqsPadCtrl4, 16:12, scratch46, 9:5);
s(EmcXm2DqsPadCtrl4, 10:6, scratch46, 14:10);
s(EmcXm2DqsPadCtrl4, 4:0, scratch46, 19:15);
s(EmcZcalWaitCnt, 9:0, scratch46, 29:20);
s(EmcXm2DqsPadCtrl5, 22:18, scratch47, 4:0);
s(EmcXm2DqsPadCtrl5, 16:12, scratch47, 9:5);
s(EmcXm2DqsPadCtrl5, 10:6, scratch47, 14:10);
s(EmcXm2DqsPadCtrl5, 4:0, scratch47, 19:15);
s(EmcXm2VttGenPadCtrl2, 5:0, scratch47, 25:20);
s(EmcXm2VttGenPadCtrl2, 31:28, scratch47, 29:26);
s(EmcXm2DqsPadCtrl6, 12:8, scratch48, 4:0);
s(EmcXm2DqsPadCtrl6, 18:14, scratch48, 9:5);
s(EmcXm2DqsPadCtrl6, 24:20, scratch48, 14:10);
s(EmcXm2DqsPadCtrl6, 30:26, scratch48, 19:15);
s(EmcAutoCalConfig3, 4:0, scratch48, 24:20);
s(EmcAutoCalConfig3, 12:8, scratch48, 29:25);
s(EmcFbioCfg5, 1:0, scratch48, 31:30);
s(EmcDllXformQUse8, 4:0, scratch50, 4:0);
s(EmcDllXformQUse8, 22:8, scratch50, 19:5);
s(McEmemArbRing1Throttle, 4:0, scratch50, 24:20);
s(McEmemArbRing1Throttle, 20:16, scratch50, 29:25);
s(EmcFbioCfg5, 3:2, scratch50, 31:30);
s(EmcDllXformQUse9, 4:0, scratch51, 4:0);
s(EmcDllXformQUse9, 22:8, scratch51, 19:5);
s(EmcCttTermCtrl, 2:0, scratch51, 22:20);
s(EmcCttTermCtrl, 12:8, scratch51, 27:23);
s(EmcCttTermCtrl, 31:31, scratch51, 28:28);
s(EmcFbioCfg6, 2:0, scratch51, 31:29);
s(EmcDllXformQUse10, 4:0, scratch56, 4:0);
s(EmcDllXformQUse10, 22:8, scratch56, 19:5);
s(EmcXm2CmdPadCtrl, 10:3, scratch56, 27:20);
s(EmcXm2CmdPadCtrl, 28:28, scratch56, 28:28);
s(EmcPutermAdj, 1:0, scratch56, 30:29);
s(EmcPutermAdj, 7:7, scratch56, 31:31);
s(EmcDllXformQUse11, 4:0, scratch57, 4:0);
s(EmcDllXformQUse11, 22:8, scratch57, 19:5);
s(EmcWdv, 3:0, scratch57, 31:28);
s(EmcDllXformQUse12, 4:0, scratch58, 4:0);
s(EmcDllXformQUse12, 22:8, scratch58, 19:5);
s(EmcBurstRefreshNum, 3:0, scratch58, 31:28);
s(EmcDllXformQUse13, 4:0, scratch59, 4:0);
s(EmcDllXformQUse13, 22:8, scratch59, 19:5);
s(EmcWext, 3:0, scratch59, 31:28);
s(EmcDllXformQUse14, 4:0, scratch60, 4:0);
s(EmcDllXformQUse14, 22:8, scratch60, 19:5);
s(EmcClkenOverride, 3:1, scratch60, 30:28);
s(EmcClkenOverride, 6:6, scratch60, 31:31);
s(EmcDllXformQUse15, 4:0, scratch61, 4:0);
s(EmcDllXformQUse15, 22:8, scratch61, 19:5);
s(EmcR2r, 3:0, scratch61, 31:28);
s(EmcDllXformDq4, 4:0, scratch62, 4:0);
s(EmcDllXformDq4, 22:8, scratch62, 19:5);
s(EmcRc, 6:0, scratch62, 26:20);
s(EmcW2r, 4:0, scratch62, 31:27);
s(EmcDllXformDq5, 4:0, scratch63, 4:0);
s(EmcDllXformDq5, 22:8, scratch63, 19:5);
s(EmcTfaw, 6:0, scratch63, 26:20);
s(EmcR2p, 4:0, scratch63, 31:27);
s(EmcDllXformDq6, 4:0, scratch64, 4:0);
s(EmcDllXformDq6, 22:8, scratch64, 19:5);
s(EmcDliTrimTxDqs0, 6:0, scratch64, 26:20);
s(EmcQSafe, 4:0, scratch64, 31:27);
s(EmcDllXformDq7, 4:0, scratch65, 4:0);
s(EmcDllXformDq7, 22:8, scratch65, 19:5);
s(EmcDliTrimTxDqs1, 6:0, scratch65, 26:20);
s(EmcTClkStable, 4:0, scratch65, 31:27);
s(EmcAutoCalConfig2, 4:0, scratch66, 4:0);
s(EmcAutoCalConfig2, 12:8, scratch66, 9:5);
s(EmcAutoCalConfig2, 20:16, scratch66, 14:10);
s(EmcAutoCalConfig2, 28:24, scratch66, 19:15);
s(EmcDliTrimTxDqs2, 6:0, scratch66, 26:20);
s(EmcTClkStop, 4:0, scratch66, 31:27);
s(McEmemArbMisc1, 1:0, scratch67, 1:0);
s(McEmemArbMisc1, 12:4, scratch67, 10:2);
s(McEmemArbMisc1, 25:21, scratch67, 15:11);
s(McEmemArbMisc1, 31:28, scratch67, 19:16);
s(EmcDliTrimTxDqs3, 6:0, scratch67, 26:20);
s(EmcEInputDuration, 4:0, scratch67, 31:27);
s(EmcZcalMrwCmd, 7:0, scratch68, 7:0);
s(EmcZcalMrwCmd, 23:16, scratch68, 15:8);
s(EmcZcalMrwCmd, 31:30, scratch68, 17:16);
s(EmcTRefBw, 13:0, scratch68, 31:18);
s(EmcXm2CmdPadCtrl2, 31:14, scratch69, 17:0);
s(EmcDliTrimTxDqs4, 6:0, scratch69, 24:18);
s(EmcDliTrimTxDqs5, 6:0, scratch69, 31:25);
s(EmcXm2CmdPadCtrl3, 31:14, scratch70, 17:0);
s(EmcDliTrimTxDqs6, 6:0, scratch70, 24:18);
s(EmcDliTrimTxDqs7, 6:0, scratch70, 31:25);
s(EmcXm2CmdPadCtrl5, 2:0, scratch71, 2:0);
s(EmcXm2CmdPadCtrl5, 6:4, scratch71, 5:3);
s(EmcXm2CmdPadCtrl5, 10:8, scratch71, 8:6);
s(EmcXm2CmdPadCtrl5, 14:12, scratch71, 11:9);
s(EmcXm2CmdPadCtrl5, 18:16, scratch71, 14:12);
s(EmcXm2CmdPadCtrl5, 22:20, scratch71, 17:15);
s(EmcDliTrimTxDqs8, 6:0, scratch71, 24:18);
s(EmcDliTrimTxDqs9, 6:0, scratch71, 31:25);
s(EmcCdbCntl3, 17:0, scratch72, 17:0);
s(EmcDliTrimTxDqs10, 6:0, scratch72, 24:18);
s(EmcDliTrimTxDqs11, 6:0, scratch72, 31:25);
s(EmcSwizzleRank0Byte0, 2:0, scratch73, 2:0);
s(EmcSwizzleRank0Byte0, 6:4, scratch73, 5:3);
s(EmcSwizzleRank0Byte0, 10:8, scratch73, 8:6);
s(EmcSwizzleRank0Byte0, 14:12, scratch73, 11:9);
s(EmcSwizzleRank0Byte0, 18:16, scratch73, 14:12);
s(EmcSwizzleRank0Byte0, 22:20, scratch73, 17:15);
s(EmcDliTrimTxDqs12, 6:0, scratch73, 24:18);
s(EmcDliTrimTxDqs13, 6:0, scratch73, 31:25);
s(EmcSwizzleRank0Byte1, 2:0, scratch74, 2:0);
s(EmcSwizzleRank0Byte1, 6:4, scratch74, 5:3);
s(EmcSwizzleRank0Byte1, 10:8, scratch74, 8:6);
s(EmcSwizzleRank0Byte1, 14:12, scratch74, 11:9);
s(EmcSwizzleRank0Byte1, 18:16, scratch74, 14:12);
s(EmcSwizzleRank0Byte1, 22:20, scratch74, 17:15);
s(EmcDliTrimTxDqs14, 6:0, scratch74, 24:18);
s(EmcDliTrimTxDqs15, 6:0, scratch74, 31:25);
s(EmcSwizzleRank0Byte2, 2:0, scratch75, 2:0);
s(EmcSwizzleRank0Byte2, 6:4, scratch75, 5:3);
s(EmcSwizzleRank0Byte2, 10:8, scratch75, 8:6);
s(EmcSwizzleRank0Byte2, 14:12, scratch75, 11:9);
s(EmcSwizzleRank0Byte2, 18:16, scratch75, 14:12);
s(EmcSwizzleRank0Byte2, 22:20, scratch75, 17:15);
s(McEmemArbTimingRp, 6:0, scratch75, 24:18);
s(McEmemArbTimingRc, 6:0, scratch75, 31:25);
s(EmcSwizzleRank0Byte3, 2:0, scratch76, 2:0);
s(EmcSwizzleRank0Byte3, 6:4, scratch76, 5:3);
s(EmcSwizzleRank0Byte3, 10:8, scratch76, 8:6);
s(EmcSwizzleRank0Byte3, 14:12, scratch76, 11:9);
s(EmcSwizzleRank0Byte3, 18:16, scratch76, 14:12);
s(EmcSwizzleRank0Byte3, 22:20, scratch76, 17:15);
s(McEmemArbTimingFaw, 6:0, scratch76, 24:18);
s(McEmemArbTimingWap2Pre, 6:0, scratch76, 31:25);
s(EmcSwizzleRank1Byte0, 2:0, scratch77, 2:0);
s(EmcSwizzleRank1Byte0, 6:4, scratch77, 5:3);
s(EmcSwizzleRank1Byte0, 10:8, scratch77, 8:6);
s(EmcSwizzleRank1Byte0, 14:12, scratch77, 11:9);
s(EmcSwizzleRank1Byte0, 18:16, scratch77, 14:12);
s(EmcSwizzleRank1Byte0, 22:20, scratch77, 17:15);
s(EmcRas, 5:0, scratch77, 23:18);
s(EmcRp, 5:0, scratch77, 29:24);
s(EmcCfg2, 9:8, scratch77, 31:30);
s(EmcSwizzleRank1Byte1, 2:0, scratch78, 2:0);
s(EmcSwizzleRank1Byte1, 6:4, scratch78, 5:3);
s(EmcSwizzleRank1Byte1, 10:8, scratch78, 8:6);
s(EmcSwizzleRank1Byte1, 14:12, scratch78, 11:9);
s(EmcSwizzleRank1Byte1, 18:16, scratch78, 14:12);
s(EmcSwizzleRank1Byte1, 22:20, scratch78, 17:15);
s(EmcW2p, 5:0, scratch78, 23:18);
s(EmcRdRcd, 5:0, scratch78, 29:24);
s(EmcCfg2, 27:26, scratch78, 31:30);
s(EmcSwizzleRank1Byte2, 2:0, scratch79, 2:0);
s(EmcSwizzleRank1Byte2, 6:4, scratch79, 5:3);
s(EmcSwizzleRank1Byte2, 10:8, scratch79, 8:6);
s(EmcSwizzleRank1Byte2, 14:12, scratch79, 11:9);
s(EmcSwizzleRank1Byte2, 18:16, scratch79, 14:12);
s(EmcSwizzleRank1Byte2, 22:20, scratch79, 17:15);
s(EmcWrRcd, 5:0, scratch79, 23:18);
s(EmcQUse, 5:0, scratch79, 29:24);
s(EmcFbioCfg5, 4:4, scratch79, 31:31);
s(EmcSwizzleRank1Byte3, 2:0, scratch80, 2:0);
s(EmcSwizzleRank1Byte3, 6:4, scratch80, 5:3);
s(EmcSwizzleRank1Byte3, 10:8, scratch80, 8:6);
s(EmcSwizzleRank1Byte3, 14:12, scratch80, 11:9);
s(EmcSwizzleRank1Byte3, 18:16, scratch80, 14:12);
s(EmcSwizzleRank1Byte3, 22:20, scratch80, 17:15);
s(EmcQRst, 5:0, scratch80, 23:18);
s(EmcRdv, 5:0, scratch80, 29:24);
s(EmcFbioCfg5, 6:5, scratch80, 31:30);
s(EmcDynSelfRefControl, 15:0, scratch81, 15:0);
s(EmcDynSelfRefControl, 31:31, scratch81, 16:16);
s(EmcPdEx2Wr, 5:0, scratch81, 22:17);
s(EmcPdEx2Rd, 5:0, scratch81, 28:23);
s(EmcRefresh, 5:0, scratch82, 5:0);
s(EmcRefresh, 15:6, scratch82, 15:6);
s(EmcCmdQ, 4:0, scratch82, 20:16);
s(EmcCmdQ, 10:8, scratch82, 23:21);
s(EmcCmdQ, 14:12, scratch82, 26:24);
s(EmcCmdQ, 28:24, scratch82, 31:27);
s(EmcAcpdControl, 15:0, scratch83, 15:0);
s(EmcCfgDigDllPeriod, 15:0, scratch83, 31:16);
s(EmcDllXformDqs0, 4:0, scratch84, 4:0);
s(EmcDllXformDqs0, 22:12, scratch84, 15:5);
s(EmcDllXformDqs1, 4:0, scratch84, 20:16);
s(EmcDllXformDqs1, 22:12, scratch84, 31:21);
s(EmcDllXformDqs2, 4:0, scratch85, 4:0);
s(EmcDllXformDqs2, 22:12, scratch85, 15:5);
s(EmcDllXformDqs3, 4:0, scratch85, 20:16);
s(EmcDllXformDqs3, 22:12, scratch85, 31:21);
s(EmcDllXformDqs4, 4:0, scratch86, 4:0);
s(EmcDllXformDqs4, 22:12, scratch86, 15:5);
s(EmcDllXformDqs5, 4:0, scratch86, 20:16);
s(EmcDllXformDqs5, 22:12, scratch86, 31:21);
s(EmcDllXformDqs6, 4:0, scratch87, 4:0);
s(EmcDllXformDqs6, 22:12, scratch87, 15:5);
s(EmcDllXformDqs7, 4:0, scratch87, 20:16);
s(EmcDllXformDqs7, 22:12, scratch87, 31:21);
s(EmcDllXformDqs8, 4:0, scratch88, 4:0);
s(EmcDllXformDqs8, 22:12, scratch88, 15:5);
s(EmcDllXformDqs9, 4:0, scratch88, 20:16);
s(EmcDllXformDqs9, 22:12, scratch88, 31:21);
s(EmcDllXformDqs10, 4:0, scratch89, 4:0);
s(EmcDllXformDqs10, 22:12, scratch89, 15:5);
s(EmcDllXformDqs11, 4:0, scratch89, 20:16);
s(EmcDllXformDqs11, 22:12, scratch89, 31:21);
s(EmcDllXformDqs12, 4:0, scratch90, 4:0);
s(EmcDllXformDqs12, 22:12, scratch90, 15:5);
s(EmcDllXformDqs13, 4:0, scratch90, 20:16);
s(EmcDllXformDqs13, 22:12, scratch90, 31:21);
s(EmcDllXformDqs14, 4:0, scratch91, 4:0);
s(EmcDllXformDqs14, 22:12, scratch91, 15:5);
s(EmcDllXformDqs15, 4:0, scratch91, 20:16);
s(EmcDllXformDqs15, 22:12, scratch91, 31:21);
s(EmcDllXformQUse0, 4:0, scratch92, 4:0);
s(EmcDllXformQUse0, 22:12, scratch92, 15:5);
s(EmcDllXformQUse1, 4:0, scratch92, 20:16);
s(EmcDllXformQUse1, 22:12, scratch92, 31:21);
s(EmcDllXformQUse2, 4:0, scratch93, 4:0);
s(EmcDllXformQUse2, 22:12, scratch93, 15:5);
s(EmcDllXformQUse3, 4:0, scratch93, 20:16);
s(EmcDllXformQUse3, 22:12, scratch93, 31:21);
s(EmcDllXformQUse4, 4:0, scratch94, 4:0);
s(EmcDllXformQUse4, 22:12, scratch94, 15:5);
s(EmcDllXformQUse5, 4:0, scratch94, 20:16);
s(EmcDllXformQUse5, 22:12, scratch94, 31:21);
s(EmcDllXformQUse6, 4:0, scratch95, 4:0);
s(EmcDllXformQUse6, 22:12, scratch95, 15:5);
s(EmcDllXformQUse7, 4:0, scratch95, 20:16);
s(EmcDllXformQUse7, 22:12, scratch95, 31:21);
s(EmcDllXformDq0, 4:0, scratch96, 4:0);
s(EmcDllXformDq0, 22:12, scratch96, 15:5);
s(EmcDllXformDq1, 4:0, scratch96, 20:16);
s(EmcDllXformDq1, 22:12, scratch96, 31:21);
s(EmcDllXformDq2, 4:0, scratch97, 4:0);
s(EmcDllXformDq2, 22:12, scratch97, 15:5);
s(EmcDllXformDq3, 4:0, scratch97, 20:16);
s(EmcDllXformDq3, 22:12, scratch97, 31:21);
s(EmcPreRefreshReqCnt, 15:0, scratch98, 15:0);
s(EmcDllXformAddr0, 4:0, scratch98, 20:16);
s(EmcDllXformAddr0, 22:12, scratch98, 31:21);
s(EmcDllXformAddr1, 4:0, scratch99, 4:0);
s(EmcDllXformAddr1, 22:12, scratch99, 15:5);
s(EmcDllXformAddr2, 4:0, scratch99, 20:16);
s(EmcDllXformAddr2, 22:12, scratch99, 31:21);
s(EmcDllXformAddr3, 4:0, scratch100, 4:0);
s(EmcDllXformAddr3, 22:12, scratch100, 15:5);
s(EmcDllXformAddr4, 4:0, scratch100, 20:16);
s(EmcDllXformAddr4, 22:12, scratch100, 31:21);
s(EmcDllXformAddr5, 4:0, scratch101, 4:0);
s(EmcDllXformAddr5, 22:12, scratch101, 15:5);
s(EmcPChg2Pden, 5:0, scratch102, 5:0);
s(EmcAct2Pden, 5:0, scratch102, 11:6);
s(EmcRw2Pden, 5:0, scratch102, 17:12);
s(EmcTcke, 5:0, scratch102, 23:18);
s(EmcTrpab, 5:0, scratch102, 29:24);
s(EmcFbioCfg5, 8:7, scratch102, 31:30);
s(EmcCtt, 5:0, scratch103, 5:0);
s(EmcEInput, 5:0, scratch103, 11:6);
s(EmcPutermExtra, 21:16, scratch103, 17:12);
s(EmcTckesr, 5:0, scratch103, 23:18);
s(EmcTpd, 5:0, scratch103, 29:24);
s(EmcFbioCfg5, 10:9, scratch103, 31:30);
s(EmcRdvMask, 5:0, scratch104, 5:0);
s(EmcXm2CmdPadCtrl4, 0:0, scratch104, 6:6);
s(EmcXm2CmdPadCtrl4, 2:2, scratch104, 7:7);
s(EmcXm2CmdPadCtrl4, 4:4, scratch104, 8:8);
s(EmcXm2CmdPadCtrl4, 6:6, scratch104, 9:9);
s(EmcXm2CmdPadCtrl4, 8:8, scratch104, 10:10);
s(EmcXm2CmdPadCtrl4, 10:10, scratch104, 11:11);
s(EmcQpop, 5:0, scratch104, 17:12);
s(McEmemArbTimingRcd, 5:0, scratch104, 23:18);
s(McEmemArbTimingRas, 5:0, scratch104, 29:24);
s(EmcFbioCfg5, 12:11, scratch104, 31:30);
s(McEmemArbTimingRap2Pre, 5:0, scratch105, 5:0);
s(McEmemArbTimingR2W, 5:0, scratch105, 11:6);
s(McEmemArbTimingW2R, 5:0, scratch105, 17:12);
s(EmcIbdly, 4:0, scratch105, 22:18);
s(McEmemArbTimingR2R, 4:0, scratch105, 27:23);
s(EmcW2w, 3:0, scratch105, 31:28);
s(McEmemArbTimingW2W, 4:0, scratch106, 4:0);
s(McEmemArbOverride, 27:27, scratch106, 5:5);
s(McEmemArbOverride, 26:26, scratch106, 6:6);
s(McEmemArbOverride, 16:16, scratch106, 7:7);
s(McEmemArbOverride, 10:10, scratch106, 8:8);
s(McEmemArbOverride, 4:4, scratch106, 9:9);
s(EmcWdvMask, 3:0, scratch106, 13:10);
s(EmcCttDuration, 3:0, scratch106, 17:14);
s(EmcQuseWidth, 3:0, scratch106, 21:18);
s(EmcPutermWidth, 3:0, scratch106, 25:22);
s(EmcBgbiasCtl0, 3:0, scratch106, 29:26);
s(EmcFbioCfg5, 25:24, scratch106, 31:30);
s(McEmemArbTimingRrd, 3:0, scratch107, 3:0);
s(EmcFbioCfg5, 23:20, scratch107, 10:7);
s(EmcFbioCfg5, 15:13, scratch107, 13:11);
s(EmcCfg2, 5:3, scratch107, 16:14);
s(EmcFbioCfg5, 26:26, scratch107, 17:17);
s(EmcFbioCfg5, 28:28, scratch107, 18:18);
s(EmcCfg2, 2:0, scratch107, 21:19);
s(EmcCfg2, 7:6, scratch107, 23:22);
s(EmcCfg2, 15:10, scratch107, 29:24);
s(EmcCfg2, 23:22, scratch107, 31:30);
s(EmcCfg2, 25:24, scratch108, 1:0);
s(EmcCfg2, 31:28, scratch108, 5:2);
s(BootRomPatchData, 31:0, scratch15, 31:0);
s(BootRomPatchControl, 31:0, scratch16, 31:0);
s(EmcDevSelect, 1:0, scratch17, 31:30);
s(EmcZcalWarmColdBootEnables, 1:0, scratch18, 31:30);
s(EmcCfgDigDllPeriodWarmBoot, 1:0, scratch19, 31:30);
s(EmcWarmBootExtraModeRegWriteEnable, 0:0, scratch46, 30:30);
s(McClkenOverrideAllWarmBoot, 0:0, scratch46, 31:31);
s(EmcClkenOverrideAllWarmBoot, 0:0, scratch47, 30:30);
s(EmcMrsWarmBootEnable, 0:0, scratch47, 31:31);
s(EmcTimingControlWait, 7:0, scratch57, 27:20);
s(EmcZcalWarmBootWait, 7:0, scratch58, 27:20);
s(EmcAutoCalWait, 7:0, scratch59, 27:20);
s(WarmBootWait, 7:0, scratch60, 27:20);
s(EmcPinProgramWait, 7:0, scratch61, 27:20);
s(AhbArbitrationXbarCtrlMemInitDone, 0:0, scratch79, 30:30);
s(EmcExtraRefreshNum, 2:0, scratch81, 31:29);
s(SwizzleRankByteEncode, 15:0, scratch101, 31:16);
s(MemoryType, 2:0, scratch107, 6:4);
switch (sdram->MemoryType) {
case NvBootMemoryType_LpDdr2:
s(EmcMrwLpddr2ZcalWarmBoot, 23:16, scratch5, 7:0);
s(EmcMrwLpddr2ZcalWarmBoot, 7:0, scratch5, 15:8);
s(EmcWarmBootMrwExtra, 23:16, scratch5, 23:16);
s(EmcWarmBootMrwExtra, 7:0, scratch5, 31:24);
s(EmcMrwLpddr2ZcalWarmBoot, 31:30, scratch6, 1:0);
s(EmcWarmBootMrwExtra, 31:30, scratch6, 3:2);
s(EmcMrwLpddr2ZcalWarmBoot, 27:26, scratch6, 5:4);
s(EmcWarmBootMrwExtra, 27:26, scratch6, 7:6);
s(EmcMrw1, 7:0, scratch7, 7:0);
s(EmcMrw1, 23:16, scratch7, 15:8);
s(EmcMrw1, 27:26, scratch7, 17:16);
s(EmcMrw1, 31:30, scratch7, 19:18);
s(EmcMrw2, 7:0, scratch8, 7:0);
s(EmcMrw2, 23:16, scratch8, 15:8);
s(EmcMrw2, 27:26, scratch8, 17:16);
s(EmcMrw2, 31:30, scratch8, 19:18);
s(EmcMrw3, 7:0, scratch9, 7:0);
s(EmcMrw3, 23:16, scratch9, 15:8);
s(EmcMrw3, 27:26, scratch9, 17:16);
s(EmcMrw3, 31:30, scratch9, 19:18);
s(EmcMrw4, 7:0, scratch10, 7:0);
s(EmcMrw4, 23:16, scratch10, 15:8);
s(EmcMrw4, 27:26, scratch10, 17:16);
s(EmcMrw4, 31:30, scratch10, 19:18);
break;
case NvBootMemoryType_Ddr3:
s(EmcMrs, 13:0, scratch5, 13:0);
s(EmcEmrs, 13:0, scratch5, 27:14);
s(EmcMrs, 21:20, scratch5, 29:28);
s(EmcMrs, 31:30, scratch5, 31:30);
s(EmcEmrs2, 13:0, scratch7, 13:0);
s(EmcEmrs, 21:20, scratch7, 15:14);
s(EmcEmrs, 31:30, scratch7, 17:16);
s(EmcEmrs2, 21:20, scratch7, 19:18);
s(EmcEmrs3, 13:0, scratch8, 13:0);
s(EmcEmrs2, 31:30, scratch8, 15:14);
s(EmcEmrs3, 21:20, scratch8, 17:16);
s(EmcEmrs3, 31:30, scratch8, 19:18);
s(EmcWarmBootMrsExtra, 13:0, scratch9, 13:0);
s(EmcWarmBootMrsExtra, 31:30, scratch9, 15:14);
s(EmcWarmBootMrsExtra, 21:20, scratch9, 17:16);
s(EmcZqCalDdr3WarmBoot, 31:30, scratch9, 19:18);
s(EmcMrs, 27:26, scratch10, 1:0);
s(EmcEmrs, 27:26, scratch10, 3:2);
s(EmcEmrs2, 27:26, scratch10, 5:4);
s(EmcEmrs3, 27:26, scratch10, 7:6);
s(EmcWarmBootMrsExtra, 27:27, scratch10, 8:8);
s(EmcWarmBootMrsExtra, 26:26, scratch10, 9:9);
s(EmcZqCalDdr3WarmBoot, 0:0, scratch10, 10:10);
s(EmcZqCalDdr3WarmBoot, 4:4, scratch10, 11:11);
c(0, scratch116, 31:0);
c(0, scratch117, 31:0);
break;
default:
printk(BIOS_CRIT, "ERROR: %s() unrecognized MemoryType %d!\n",
__func__, sdram->MemoryType);
}
s(McVideoProtectGpuOverride0, 31:0, secure_scratch8, 31:0);
s(McVideoProtectVprOverride, 3:0, secure_scratch9, 3:0);
s(McVideoProtectVprOverride, 11:6, secure_scratch9, 9:4);
s(McVideoProtectVprOverride, 23:14, secure_scratch9, 19:10);
s(McVideoProtectVprOverride, 26:26, secure_scratch9, 20:20);
s(McVideoProtectVprOverride, 31:29, secure_scratch9, 23:21);
s(EmcFbioCfg5, 19:16, secure_scratch9, 27:24);
s(McDisplaySnapRing, 1:0, secure_scratch9, 29:28);
s(McDisplaySnapRing, 31:31, secure_scratch9, 30:30);
s(EmcAdrCfg, 0:0, secure_scratch9, 31:31);
s(McVideoProtectGpuOverride1, 15:0, secure_scratch10, 15:0);
s(McEmemAdrCfgBankMask0, 15:0, secure_scratch10, 31:16);
s(McEmemAdrCfgBankMask1, 15:0, secure_scratch11, 15:0);
s(McEmemAdrCfgBankMask2, 15:0, secure_scratch11, 31:16);
s(McEmemCfg, 13:0, secure_scratch12, 13:0);
s(McEmemCfg, 31:31, secure_scratch12, 14:14);
s(McVideoProtectBom, 31:20, secure_scratch12, 26:15);
s(McVideoProtectVprOverride1, 1:0, secure_scratch12, 28:27);
s(McVideoProtectVprOverride1, 4:4, secure_scratch12, 29:29);
s(McVideoProtectBomAdrHi, 1:0, secure_scratch12, 31:30);
s(McVideoProtectSizeMb, 11:0, secure_scratch13, 11:0);
s(McSecCarveoutBom, 31:20, secure_scratch13, 23:12);
s(McEmemAdrCfgBankSwizzle3, 2:0, secure_scratch13, 26:24);
s(McVideoProtectWriteAccess, 1:0, secure_scratch13, 28:27);
s(McSecCarveoutAdrHi, 1:0, secure_scratch13, 30:29);
s(McEmemAdrCfg, 0:0, secure_scratch13, 31:31);
s(McSecCarveoutSizeMb, 11:0, secure_scratch14, 11:0);
s(McMtsCarveoutBom, 31:20, secure_scratch14, 23:12);
s(McMtsCarveoutAdrHi, 1:0, secure_scratch14, 25:24);
s(McSecCarveoutProtectWriteAccess, 0:0, secure_scratch14, 26:26);
s(McMtsCarveoutRegCtrl, 0:0, secure_scratch14, 27:27);
s(McMtsCarveoutSizeMb, 11:0, secure_scratch15, 11:0);
s(McEmemAdrCfgDev0, 2:0, secure_scratch15, 14:12);
s(McEmemAdrCfgDev0, 9:8, secure_scratch15, 16:15);
s(McEmemAdrCfgDev0, 19:16, secure_scratch15, 20:17);
s(McEmemAdrCfgDev1, 2:0, secure_scratch15, 23:21);
s(McEmemAdrCfgDev1, 9:8, secure_scratch15, 25:24);
s(McEmemAdrCfgDev1, 19:16, secure_scratch15, 29:26);
/* Make sure all writes complete before we lock the secure_scratchs. */
dmb();
c(0x1555555, sec_disable2, 25:0);
c(0xff, sec_disable, 19:12);
c(0, scratch2, 31:0);
m(pllm_base, 15:0, scratch2, 15:0);
m(pllm_base, 20:20, scratch2, 16:16);
m(pllm_misc2, 2:0, scratch2, 19:17);
c(0, scratch35, 31:0);
m(pllm_misc1, 23:0, scratch35, 23:0);
m(pllm_misc1, 30:28, scratch35, 30:28);
c(0, scratch3, 31:0);
s(PllMInputDivider, 7:0, scratch3, 7:0);
c(0x3e, scratch3, 15:8);
c(0, scratch3, 19:16);
s(PllMKVCO, 0:0, scratch3, 20:20);
s(PllMKCP, 1:0, scratch3, 22:21);
c(0, scratch36, 31:0);
s(PllMSetupControl, 23:0, scratch36, 23:0);
c(0, scratch4, 31:0);
s(PllMStableTime, 9:0, scratch4, 9:0);
s(PllMStableTime, 9:0, scratch4, 19:10);
s(PllMSelectDiv2, 0:0, pllm_wb0_override2, 27:27);
s(PllMKVCO, 0:0, pllm_wb0_override2, 26:26);
s(PllMKCP, 1:0, pllm_wb0_override2, 25:24);
s(PllMSetupControl, 23:0, pllm_wb0_override2, 23:0);
s(PllMFeedbackDivider, 7:0, pllm_wb0_override_freq, 15:8);
s(PllMInputDivider, 7:0, pllm_wb0_override_freq, 7:0);
/* Need to ensure override params are written before we activate it. */
dmb();
c(3, pllp_wb0_override, 12:11);
}

20
src/soc/nvidia/tegra124/sdram_param.h
View File

@ -33,25 +33,27 @@
enum { enum {
/* Specifies the memory type to be undefined */ /* Specifies the memory type to be undefined */
MEMORY_TYPE_NONE = 0, NvBootMemoryType_None = 0,
/* Specifies the memory type to be DDR SDRAM */ /* Specifies the memory type to be DDR SDRAM */
MEMORY_TYPE_DDR = 0, NvBootMemoryType_Ddr = 0,
/* Specifies the memory type to be LPDDR SDRAM */ /* Specifies the memory type to be LPDDR SDRAM */
MEMORY_TYPE_LPDDR = 0, NvBootMemoryType_LpDdr = 0,
/* Specifies the memory type to be DDR2 SDRAM */ /* Specifies the memory type to be DDR2 SDRAM */
MEMORY_TYPE_DDR2 = 0, NvBootMemoryType_Ddr2 = 0,
/* Specifies the memory type to be LPDDR2 SDRAM */ /* Specifies the memory type to be LPDDR2 SDRAM */
MEMORY_TYPE_LPDDR2, NvBootMemoryType_LpDdr2,
/* Specifies the memory type to be DDR3 SDRAM */ /* Specifies the memory type to be DDR3 SDRAM */
MEMORY_TYPE_DDR3, NvBootMemoryType_Ddr3,
MEMORY_TYPE_NUM, NvBootMemoryType_Num,
MEMORY_TYPE_FORCE32 = 0X7FFFFFF
/* Specifies an entry in the ram_code table that's not in use */
NvBootMemoryType_Unused = 0X7FFFFFF,
}; };
enum { enum {
@ -69,7 +71,7 @@ enum {
struct sdram_params { struct sdram_params {
/* Specifies the type of memory device */ /* Specifies the type of memory device */
uint32_t memory_type; uint32_t MemoryType;
/* MC/EMC clock source configuration */ /* MC/EMC clock source configuration */

8
src/soc/nvidia/tegra124/soc.c
View File

@ -22,7 +22,8 @@
#include <console/console.h> #include <console/console.h>
#include <device/device.h> #include <device/device.h>
#include <soc/nvidia/tegra/dc.h> #include <soc/nvidia/tegra/dc.h>
#include <soc/addressmap.h> #include <soc/nvidia/tegra124/sdram.h>
#include <soc/display.h>
/* this sucks, but for now, fb size/location are hardcoded. /* this sucks, but for now, fb size/location are hardcoded.
* Will break if we get 2. Sigh. * Will break if we get 2. Sigh.
@ -30,10 +31,11 @@
*/ */
static void soc_enable(device_t dev) static void soc_enable(device_t dev)
{ {
u32 lcdbase = fb_base_mb();
unsigned long fb_size = FB_SIZE_MB; unsigned long fb_size = FB_SIZE_MB;
u32 lcdbase = FB_BASE_MB;
ram_resource(dev, 0, CONFIG_SYS_SDRAM_BASE/KiB, ram_resource(dev, 0, CONFIG_SYS_SDRAM_BASE/KiB,
(CONFIG_DRAM_SIZE_MB - fb_size)*KiB); (sdram_size_mb() - fb_size)*KiB);
mmio_resource(dev, 1, lcdbase*KiB, fb_size*KiB); mmio_resource(dev, 1, lcdbase*KiB, fb_size*KiB);
} }