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ck804 whitespace fixes 

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3584 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Myles Watson 2008-09-18 16:27:00 +00:00
parent a67c354cbf
commit 64caf3607e
20 changed files with 783 additions and 791 deletions
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2
src/southbridge/nvidia/ck804/ck804.c
View File

@ -157,13 +157,11 @@ void ck804_enable(device_t dev)
final_reg &= ~((1<<16)|(1<<8)|(1<<20)|(1<<10)|(1<<12)|(1<<13)|(1<<14)|(1<<22)|(1<<18)|(1<<15));
pci_write_config32(lpc_dev, 0xe8, final_reg);
#if 1
reg_old = reg = pci_read_config32(lpc_dev, 0xe4);
reg |= (1<<20);
if (reg != reg_old) {
pci_write_config32(lpc_dev, 0xe4, reg);
}
#endif
byte = pci_read_config8(lpc_dev, 0x74);
byte |= ((1<<1));

288
src/southbridge/nvidia/ck804/ck804_early_setup.c
View File

@ -4,14 +4,14 @@
*/
static int set_ht_link_ck804(uint8_t ht_c_num)
{
unsigned vendorid = 0x10de;
unsigned val = 0x01610169;
return set_ht_link_buffer_counts_chain(ht_c_num, vendorid, val);
unsigned vendorid = 0x10de;
unsigned val = 0x01610169;
return set_ht_link_buffer_counts_chain(ht_c_num, vendorid, val);
}
static void setup_ss_table(unsigned index, unsigned where, unsigned control, const unsigned int *register_values, int max)
{
int i;
int i;
unsigned val;
@ -19,16 +19,16 @@ static void setup_ss_table(unsigned index, unsigned where, unsigned control, con
val &= 0xfffffffe;
outl(val, control);
outl(0, index);
outl(0, index);
for(i = 0; i < max; i++) {
unsigned long reg;
reg = register_values[i];
outl(reg, where);
}
val = inl(control);
val |= 1;
outl(val, control);
for(i = 0; i < max; i++) {
unsigned long reg;
reg = register_values[i];
outl(reg, where);
}
val = inl(control);
val |= 1;
outl(val, control);
}
@ -40,11 +40,11 @@ static void setup_ss_table(unsigned index, unsigned where, unsigned control, con
#define SYSCTRL_REG_POS 0x64
/*
16 1 1 2 :0
8 8 2 2 :1
8 8 4 :2
8 4 4 4 :3
16 4 :4
16 1 1 2 :0
8 8 2 2 :1
8 8 4 :2
8 4 4 4 :3
16 4 :4
*/
#ifndef CK804_PCI_E_X
@ -75,32 +75,32 @@ static void setup_ss_table(unsigned index, unsigned where, unsigned control, con
#define CK804_CHIP_REV 3
#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
#define CK804_DEVN_BASE HT_CHAIN_END_UNITID_BASE
#define CK804_DEVN_BASE HT_CHAIN_END_UNITID_BASE
#else
#define CK804_DEVN_BASE HT_CHAIN_UNITID_BASE
#define CK804_DEVN_BASE HT_CHAIN_UNITID_BASE
#endif
#if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
#define CK804B_DEVN_BASE 1
#define CK804B_DEVN_BASE 1
#else
#define CK804B_DEVN_BASE CK804_DEVN_BASE
#define CK804B_DEVN_BASE CK804_DEVN_BASE
#endif
static void ck804_early_set_port(void)
{
static const unsigned int ctrl_devport_conf[] = {
PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE,
static const unsigned int ctrl_devport_conf[] = {
PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE,
#if CK804_NUM > 1
PCI_ADDR(CK804B_BUSN, (CK804B_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), CK804B_ANACTRL_IO_BASE,
PCI_ADDR(CK804B_BUSN, (CK804B_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), CK804B_ANACTRL_IO_BASE,
#endif
PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE,
PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE,
#if CK804_NUM > 1
PCI_ADDR(CK804B_BUSN, (CK804B_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), CK804B_SYSCTRL_IO_BASE,
PCI_ADDR(CK804B_BUSN, (CK804B_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), CK804B_SYSCTRL_IO_BASE,
#endif
};
};
setup_resource_map(ctrl_devport_conf, sizeof(ctrl_devport_conf)/sizeof(ctrl_devport_conf[0]));
@ -109,17 +109,17 @@ static void ck804_early_set_port(void)
static void ck804_early_clear_port(void)
{
static const unsigned int ctrl_devport_conf_clear[] = {
PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0,
static const unsigned int ctrl_devport_conf_clear[] = {
PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0,
#if CK804_NUM > 1
PCI_ADDR(CK804B_BUSN, (CK804B_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0,
PCI_ADDR(CK804B_BUSN, (CK804B_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0,
#endif
PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0,
PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0,
#if CK804_NUM > 1
PCI_ADDR(CK804B_BUSN, (CK804B_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0,
PCI_ADDR(CK804B_BUSN, (CK804B_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0,
#endif
};
};
setup_resource_map(ctrl_devport_conf_clear, sizeof(ctrl_devport_conf_clear)/sizeof(ctrl_devport_conf_clear[0]));
@ -128,75 +128,75 @@ static void ck804_early_clear_port(void)
static void ck804_early_setup(void)
{
static const unsigned int ctrl_conf[] = {
static const unsigned int ctrl_conf[] = {
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0x8c), 0xffff0000, 0x00009880,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0x90), 0xffff000f, 0x000074a0,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0xa0), 0xfffff0ff, 0x00000a00,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0xac), 0xffffff00, 0x00000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0x8c), 0xffff0000, 0x00009880,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0x90), 0xffff000f, 0x000074a0,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0xa0), 0xfffff0ff, 0x00000a00,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0xac), 0xffffff00, 0x00000000,
#if CK804_NUM > 1
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0x8c), 0xffff0000, 0x00009880,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0x90), 0xffff000f, 0x000074a0,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0xa0), 0xfffff0ff, 0x00000a00,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0x8c), 0xffff0000, 0x00009880,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0x90), 0xffff000f, 0x000074a0,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0xa0), 0xfffff0ff, 0x00000a00,
#endif
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x48), 0xfffffffd, 0x00000002,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x74), 0xfffff00f, 0x000009d0,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x8c), 0xffff0000, 0x0000007f,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xcc), 0xfffffff8, 0x00000003,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd0), 0xff000000, 0x00000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd4), 0xff000000, 0x00000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd8), 0xff000000, 0x00000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xdc), 0x7f000000, 0x00000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x48), 0xfffffffd, 0x00000002,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x74), 0xfffff00f, 0x000009d0,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x8c), 0xffff0000, 0x0000007f,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xcc), 0xfffffff8, 0x00000003,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd0), 0xff000000, 0x00000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd4), 0xff000000, 0x00000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd8), 0xff000000, 0x00000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xdc), 0x7f000000, 0x00000000,
#if CK804_NUM > 1
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x48), 0xfffffffd, 0x00000002,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x74), 0xfffff00f, 0x000009d0,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x8c), 0xffff0000, 0x0000007f,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xcc), 0xfffffff8, 0x00000003,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd0), 0xff000000, 0x00000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd4), 0xff000000, 0x00000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd8), 0xff000000, 0x00000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xdc), 0x7f000000, 0x00000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x48), 0xfffffffd, 0x00000002,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x74), 0xfffff00f, 0x000009d0,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x8c), 0xffff0000, 0x0000007f,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xcc), 0xfffffff8, 0x00000003,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd0), 0xff000000, 0x00000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd4), 0xff000000, 0x00000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd8), 0xff000000, 0x00000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xdc), 0x7f000000, 0x00000000,
#endif
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xf0), 0xfffffffd, 0x00000002,
RES_PCI_IO, PCI_ADDR(0,CK804_DEVN_BASE+1,0,0xf8), 0xffffffcf, 0x00000010,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xf0), 0xfffffffd, 0x00000002,
RES_PCI_IO, PCI_ADDR(0,CK804_DEVN_BASE+1,0,0xf8), 0xffffffcf, 0x00000010,
#if CK804_NUM > 1
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xf0), 0xfffffffd, 0x00000002,
RES_PCI_IO,PCI_ADDR(CK804B_BUSN,CK804B_DEVN_BASE+1,0,0xf8), 0xffffffcf, 0x00000010,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xf0), 0xfffffffd, 0x00000002,
RES_PCI_IO,PCI_ADDR(CK804B_BUSN,CK804B_DEVN_BASE+1,0,0xf8), 0xffffffcf, 0x00000010,
#endif
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x40), 0xfff8ffff, 0x00030000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x4c), 0xfe00ffff, 0x00440000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x74), 0xffffffc0, 0x00000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x40), 0xfff8ffff, 0x00030000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x4c), 0xfe00ffff, 0x00440000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x74), 0xffffffc0, 0x00000000,
#if CK804_NUM > 1
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x40), 0xfff8ffff, 0x00030000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x4c), 0xfe00ffff, 0x00440000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x74), 0xffffffc0, 0x00000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x40), 0xfff8ffff, 0x00030000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x4c), 0xfe00ffff, 0x00440000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x74), 0xffffffc0, 0x00000000,
#endif
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0x78), 0xc0ffffff, 0x19000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xe0), 0xfffffeff, 0x00000100,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0x78), 0xc0ffffff, 0x19000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xe0), 0xfffffeff, 0x00000100,
#if CK804_NUM > 1
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0x78), 0xc0ffffff, 0x20000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN,CK804B_DEVN_BASE+1,0,0xe0), 0xfffffeff, 0x00000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xe8), 0xffffff00, 0x000000ff,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0x78), 0xc0ffffff, 0x20000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN,CK804B_DEVN_BASE+1,0,0xe0), 0xfffffeff, 0x00000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xe8), 0xffffff00, 0x000000ff,
#endif
@ -223,93 +223,93 @@ static void ck804_early_setup(void)
#endif
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0,
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0,
#if CK804_NUM > 1
RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0,
RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0,
#endif
// Activate master port on primary SATA controller
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0x50), ~(0x1f000013), 0x15000013,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0x64), ~(0x00000001), 0x00000001,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0x68), ~(0x02000000), 0x02000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0x70), ~(0x000f0000), 0x00040000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0xa0), ~(0x000001ff), 0x00000150,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0xac), ~(0xffff8f00), 0x02aa8b00,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0x7c), ~(0x00000010), 0x00000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0xc8), ~(0x0fff0fff), 0x000a000a,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0xd0), ~(0xf0000000), 0x00000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0xe0), ~(0xf0000000), 0x00000000,
// Activate master port on primary SATA controller
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0x50), ~(0x1f000013), 0x15000013,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0x64), ~(0x00000001), 0x00000001,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0x68), ~(0x02000000), 0x02000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0x70), ~(0x000f0000), 0x00040000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0xa0), ~(0x000001ff), 0x00000150,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0xac), ~(0xffff8f00), 0x02aa8b00,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0x7c), ~(0x00000010), 0x00000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0xc8), ~(0x0fff0fff), 0x000a000a,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0xd0), ~(0xf0000000), 0x00000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0xe0), ~(0xf0000000), 0x00000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x50), ~(0x1f000013), 0x15000013,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x64), ~(0x00000001), 0x00000001,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x68), ~(0x02000000), 0x02000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x70), ~(0x000f0000), 0x00040000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xa0), ~(0x000001ff), 0x00000150,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xac), ~(0xffff8f00), 0x02aa8b00,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x7c), ~(0x00000010), 0x00000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xc8), ~(0x0fff0fff), 0x000a000a,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xd0), ~(0xf0000000), 0x00000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xe0), ~(0xf0000000), 0x00000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x50), ~(0x1f000013), 0x15000013,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x64), ~(0x00000001), 0x00000001,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x68), ~(0x02000000), 0x02000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x70), ~(0x000f0000), 0x00040000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xa0), ~(0x000001ff), 0x00000150,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xac), ~(0xffff8f00), 0x02aa8b00,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x7c), ~(0x00000010), 0x00000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xc8), ~(0x0fff0fff), 0x000a000a,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xd0), ~(0xf0000000), 0x00000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xe0), ~(0xf0000000), 0x00000000,
#if CK804_NUM > 1
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x50), ~(0x1f000013), 0x15000013,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x64), ~(0x00000001), 0x00000001,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x68), ~(0x02000000), 0x02000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x70), ~(0x000f0000), 0x00040000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xa0), ~(0x000001ff), 0x00000150,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xac), ~(0xffff8f00), 0x02aa8b00,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x7c), ~(0x00000010), 0x00000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xc8), ~(0x0fff0fff), 0x000a000a,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xd0), ~(0xf0000000), 0x00000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xe0), ~(0xf0000000), 0x00000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x50), ~(0x1f000013), 0x15000013,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x64), ~(0x00000001), 0x00000001,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x68), ~(0x02000000), 0x02000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x70), ~(0x000f0000), 0x00040000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xa0), ~(0x000001ff), 0x00000150,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xac), ~(0xffff8f00), 0x02aa8b00,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x7c), ~(0x00000010), 0x00000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xc8), ~(0x0fff0fff), 0x000a000a,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xd0), ~(0xf0000000), 0x00000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xe0), ~(0xf0000000), 0x00000000,
#endif
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x04, ~((0x3ff<<0)|(0x3ff<<10)), (0x21<<0)|(0x22<<10),
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x04, ~((0x3ff<<0)|(0x3ff<<10)), (0x21<<0)|(0x22<<10),
#if CK804_NUM > 1
RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x04, ~((0x3ff<<0)|(0x3ff<<10)), (0x21<<0)|(0x22<<10),
RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x04, ~((0x3ff<<0)|(0x3ff<<10)), (0x21<<0)|(0x22<<10),
#endif
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c<<10)|0x1b,
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c<<10)|0x1b,
#if CK804_NUM > 1
RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c<<10)|0x1b,
RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c<<10)|0x1b,
#endif
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1<<3), 0x00000000,
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1<<3), 0x00000000,
RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7<<4)|(1<<8)), (CK804_PCI_E_X<<4)|(1<<8),
RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7<<4)|(1<<8)), (CK804_PCI_E_X<<4)|(1<<8),
#if CK804_NUM > 1
RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, ~((7<<4)|(1<<8)), (CK804B_PCI_E_X<<4)|(1<<8),
RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, ~((7<<4)|(1<<8)), (CK804B_PCI_E_X<<4)|(1<<8),
#endif
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 8, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 9, ~(0xff), ((0<<4)|(1<<2)|(1<<0)),
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 8, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 9, ~(0xff), ((0<<4)|(1<<2)|(1<<0)),
#if CK804_USE_NIC == 1
RES_PCI_IO, PCI_ADDR(0, CK804B_DEVN_BASE+0xa , 0, 0xf8), 0xffffffbf, 0x00000040,
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+19, ~(0xff), ((0<<4)|(1<<2)|(0<<0)),
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(0<<0)),
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(1<<0)),
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xe4), ~(1<<23), (1<<23),
RES_PCI_IO, PCI_ADDR(0, CK804B_DEVN_BASE+0xa , 0, 0xf8), 0xffffffbf, 0x00000040,
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+19, ~(0xff), ((0<<4)|(1<<2)|(0<<0)),
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(0<<0)),
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(1<<0)),
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xe4), ~(1<<23), (1<<23),
#endif
#if CK804_USE_ACI == 1
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+0x0d, ~(0xff), ((0<<4)|(2<<2)|(0<<0)),
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+0x1a, ~(0xff), ((0<<4)|(2<<2)|(0<<0)),
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+0x0d, ~(0xff), ((0<<4)|(2<<2)|(0<<0)),
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+0x1a, ~(0xff), ((0<<4)|(2<<2)|(0<<0)),
#endif
#if CK804_NUM > 1
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 0, ~(3<<2), (0<<2),
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 0, ~(3<<2), (0<<2),
#endif
#if CK804_NUM > 1
#if CK804_USE_NIC == 1
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+0xa , 0, 0xf8), 0xffffffbf, 0x00000040,
RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0+19, ~(0xff), ((0<<4)|(1<<2)|(0<<0)),
RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(0<<0)),
RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(1<<0)),
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+0xa , 0, 0xf8), 0xffffffbf, 0x00000040,
RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0+19, ~(0xff), ((0<<4)|(1<<2)|(0<<0)),
RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(0<<0)),
RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(1<<0)),
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xe4), ~(1<<23), (1<<23),
#endif
#endif
@ -320,25 +320,25 @@ static void ck804_early_setup(void)
CK804_MB_SETUP
#endif
};
};
setup_resource_map_x(ctrl_conf, sizeof(ctrl_conf)/sizeof(ctrl_conf[0]));
setup_ss_table(ANACTRL_IO_BASE+0x40, ANACTRL_IO_BASE+0x44, ANACTRL_IO_BASE+0x48, pcie_ss_tbl, 64);
setup_ss_table(ANACTRL_IO_BASE+0xb0, ANACTRL_IO_BASE+0xb4, ANACTRL_IO_BASE+0xb8, sata_ss_tbl, 64);
setup_ss_table(ANACTRL_IO_BASE+0xc0, ANACTRL_IO_BASE+0xc4, ANACTRL_IO_BASE+0xc8, cpu_ss_tbl, 64);
setup_ss_table(ANACTRL_IO_BASE+0x40, ANACTRL_IO_BASE+0x44, ANACTRL_IO_BASE+0x48, pcie_ss_tbl, 64);
setup_ss_table(ANACTRL_IO_BASE+0xb0, ANACTRL_IO_BASE+0xb4, ANACTRL_IO_BASE+0xb8, sata_ss_tbl, 64);
setup_ss_table(ANACTRL_IO_BASE+0xc0, ANACTRL_IO_BASE+0xc4, ANACTRL_IO_BASE+0xc8, cpu_ss_tbl, 64);
#if CK804_NUM > 1
setup_ss_table(CK804B_ANACTRL_IO_BASE+0x40, CK804B_ANACTRL_IO_BASE+0x44, CK804B_ANACTRL_IO_BASE+0x48, pcie_ss_tbl,64);
setup_ss_table(CK804B_ANACTRL_IO_BASE+0xb0, CK804B_ANACTRL_IO_BASE+0xb4, CK804B_ANACTRL_IO_BASE+0xb8, sata_ss_tbl,64);
setup_ss_table(CK804B_ANACTRL_IO_BASE+0xc0, CK804B_ANACTRL_IO_BASE+0xc4, CK804B_ANACTRL_IO_BASE+0xc8, cpu_ss_tbl,64);
setup_ss_table(CK804B_ANACTRL_IO_BASE+0x40, CK804B_ANACTRL_IO_BASE+0x44, CK804B_ANACTRL_IO_BASE+0x48, pcie_ss_tbl,64);
setup_ss_table(CK804B_ANACTRL_IO_BASE+0xb0, CK804B_ANACTRL_IO_BASE+0xb4, CK804B_ANACTRL_IO_BASE+0xb8, sata_ss_tbl,64);
setup_ss_table(CK804B_ANACTRL_IO_BASE+0xc0, CK804B_ANACTRL_IO_BASE+0xc4, CK804B_ANACTRL_IO_BASE+0xc8, cpu_ss_tbl,64);
#endif
#if 0
dump_io_resources(ANACTRL_IO_BASE);
dump_io_resources(SYSCTRL_IO_BASE);
dump_io_resources(ANACTRL_IO_BASE);
dump_io_resources(SYSCTRL_IO_BASE);
#endif
}
@ -353,20 +353,20 @@ static int ck804_early_setup_x(void)
static void hard_reset(void)
{
set_bios_reset();
set_bios_reset();
/* full reset */
outb(0x0a, 0x0cf9);
outb(0x0e, 0x0cf9);
/* full reset */
outb(0x0a, 0x0cf9);
outb(0x0e, 0x0cf9);
}
static void soft_reset(void)
{
set_bios_reset();
set_bios_reset();
#if 1
/* link reset */
outb(0x02, 0x0cf9);
outb(0x06, 0x0cf9);
/* link reset */
outb(0x02, 0x0cf9);
outb(0x06, 0x0cf9);
#endif
}

399
src/southbridge/nvidia/ck804/ck804_early_setup_car.c
View File

@ -6,31 +6,31 @@
static int set_ht_link_ck804(uint8_t ht_c_num)
{
unsigned vendorid = 0x10de;
unsigned val = 0x01610169;
return set_ht_link_buffer_counts_chain(ht_c_num, vendorid, val);
unsigned vendorid = 0x10de;
unsigned val = 0x01610169;
return set_ht_link_buffer_counts_chain(ht_c_num, vendorid, val);
}
static void setup_ss_table(unsigned index, unsigned where, unsigned control, const unsigned int *register_values, int max)
{
int i;
int i;
unsigned val;
val = inl(control);
val &= 0xfffffffe;
outl(val, control);
outl(0, index);
outl(0, index);
for(i = 0; i < max; i++) {
unsigned long reg;
for(i = 0; i < max; i++) {
unsigned long reg;
reg = register_values[i];
outl(reg, where);
}
val = inl(control);
val |= 1;
outl(val, control);
reg = register_values[i];
outl(reg, where);
}
val = inl(control);
val |= 1;
outl(val, control);
}
@ -42,11 +42,11 @@ static void setup_ss_table(unsigned index, unsigned where, unsigned control, con
#define SYSCTRL_REG_POS 0x64
/*
16 1 1 2 :0
8 8 2 2 :1
8 8 4 :2
8 4 4 4 :3
16 4 :4
16 1 1 2 :0
8 8 2 2 :1
8 8 4 :2
8 4 4 4 :3
16 4 :4
*/
#ifndef CK804_PCI_E_X
@ -77,69 +77,69 @@ static void setup_ss_table(unsigned index, unsigned where, unsigned control, con
#define CK804_CHIP_REV 3
#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
#define CK804_DEVN_BASE HT_CHAIN_END_UNITID_BASE
#define CK804_DEVN_BASE HT_CHAIN_END_UNITID_BASE
#else
#define CK804_DEVN_BASE HT_CHAIN_UNITID_BASE
#define CK804_DEVN_BASE HT_CHAIN_UNITID_BASE
#endif
#if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
#define CK804B_DEVN_BASE 1
#define CK804B_DEVN_BASE 1
#else
#define CK804B_DEVN_BASE CK804_DEVN_BASE
#define CK804B_DEVN_BASE CK804_DEVN_BASE
#endif
static void ck804_early_set_port(unsigned ck804_num, unsigned *busn, unsigned *io_base)
{
static const unsigned int ctrl_devport_conf[] = {
PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE,
PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE,
};
static const unsigned int ctrl_devport_conf[] = {
PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE,
PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE,
};
static const unsigned int ctrl_devport_conf_b[] = {
PCI_ADDR(0, (CK804B_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE,
PCI_ADDR(0, (CK804B_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE,
};
static const unsigned int ctrl_devport_conf_b[] = {
PCI_ADDR(0, (CK804B_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE,
PCI_ADDR(0, (CK804B_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE,
};
int j;
for(j = 0; j < ck804_num; j++ ) {
if(busn[j]==0) { //sb chain
setup_resource_map_offset(ctrl_devport_conf,
sizeof(ctrl_devport_conf)/sizeof(ctrl_devport_conf[0]),
PCI_DEV(busn[j], 0, 0) , io_base[j]);
continue;
}
setup_resource_map_offset(ctrl_devport_conf_b,
sizeof(ctrl_devport_conf_b)/sizeof(ctrl_devport_conf_b[0]),
PCI_DEV(busn[j], 0, 0) , io_base[j]);
}
int j;
for(j = 0; j < ck804_num; j++ ) {
if(busn[j]==0) { //sb chain
setup_resource_map_offset(ctrl_devport_conf,
sizeof(ctrl_devport_conf)/sizeof(ctrl_devport_conf[0]),
PCI_DEV(busn[j], 0, 0) , io_base[j]);
continue;
}
setup_resource_map_offset(ctrl_devport_conf_b,
sizeof(ctrl_devport_conf_b)/sizeof(ctrl_devport_conf_b[0]),
PCI_DEV(busn[j], 0, 0) , io_base[j]);
}
}
static void ck804_early_clear_port(unsigned ck804_num, unsigned *busn, unsigned *io_base)
{
static const unsigned int ctrl_devport_conf_clear[] = {
PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0,
PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0,
};
static const unsigned int ctrl_devport_conf_clear[] = {
PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0,
PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0,
};
static const unsigned int ctrl_devport_conf_clear_b[] = {
PCI_ADDR(0, (CK804B_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0,
PCI_ADDR(0, (CK804B_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0,
};
static const unsigned int ctrl_devport_conf_clear_b[] = {
PCI_ADDR(0, (CK804B_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0,
PCI_ADDR(0, (CK804B_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0,
};
int j;
for(j = 0; j < ck804_num; j++ ) {
if(busn[j]==0) { //sb chain
setup_resource_map_offset(ctrl_devport_conf_clear,
sizeof(ctrl_devport_conf_clear)/sizeof(ctrl_devport_conf_clear[0]),
PCI_DEV(busn[j], 0, 0) , io_base[j]);
continue;
}
setup_resource_map_offset(ctrl_devport_conf_clear_b,
sizeof(ctrl_devport_conf_clear_b)/sizeof(ctrl_devport_conf_clear_b[0]),
PCI_DEV(busn[j], 0, 0) , io_base[j]);
}
int j;
for(j = 0; j < ck804_num; j++ ) {
if(busn[j]==0) { //sb chain
setup_resource_map_offset(ctrl_devport_conf_clear,
sizeof(ctrl_devport_conf_clear)/sizeof(ctrl_devport_conf_clear[0]),
PCI_DEV(busn[j], 0, 0) , io_base[j]);
continue;
}
setup_resource_map_offset(ctrl_devport_conf_clear_b,
sizeof(ctrl_devport_conf_clear_b)/sizeof(ctrl_devport_conf_clear_b[0]),
PCI_DEV(busn[j], 0, 0) , io_base[j]);
}
}
@ -148,206 +148,206 @@ static void ck804_early_clear_port(unsigned ck804_num, unsigned *busn, unsigned
static void ck804_early_setup(unsigned ck804_num, unsigned *busn, unsigned *io_base)
{
static const unsigned int ctrl_conf_master[] = {
static const unsigned int ctrl_conf_master[] = {
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0x8c), 0xffff0000, 0x00009880,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0x90), 0xffff000f, 0x000074a0,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0xa0), 0xfffff0ff, 0x00000a00,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0xac), 0xffffff00, 0x00000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0x8c), 0xffff0000, 0x00009880,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0x90), 0xffff000f, 0x000074a0,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0xa0), 0xfffff0ff, 0x00000a00,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0xac), 0xffffff00, 0x00000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x48), 0xfffffffd, 0x00000002,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x74), 0xfffff00f, 0x000009d0,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x8c), 0xffff0000, 0x0000007f,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xcc), 0xfffffff8, 0x00000003,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd0), 0xff000000, 0x00000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd4), 0xff000000, 0x00000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd8), 0xff000000, 0x00000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xdc), 0x7f000000, 0x00000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x48), 0xfffffffd, 0x00000002,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x74), 0xfffff00f, 0x000009d0,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x8c), 0xffff0000, 0x0000007f,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xcc), 0xfffffff8, 0x00000003,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd0), 0xff000000, 0x00000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd4), 0xff000000, 0x00000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd8), 0xff000000, 0x00000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xdc), 0x7f000000, 0x00000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xf0), 0xfffffffd, 0x00000002,
RES_PCI_IO, PCI_ADDR(0,CK804_DEVN_BASE+1,0,0xf8), 0xffffffcf, 0x00000010,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xf0), 0xfffffffd, 0x00000002,
RES_PCI_IO, PCI_ADDR(0,CK804_DEVN_BASE+1,0,0xf8), 0xffffffcf, 0x00000010,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x40), 0xfff8ffff, 0x00030000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x4c), 0xfe00ffff, 0x00440000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x74), 0xffffffc0, 0x00000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x40), 0xfff8ffff, 0x00030000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x4c), 0xfe00ffff, 0x00440000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x74), 0xffffffc0, 0x00000000,
#ifdef CK804_MB_SETUP
CK804_MB_SETUP
CK804_MB_SETUP
#endif
#if CK804_NUM > 1
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0x78), 0xc0ffffff, 0x19000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xe0), 0xfffffeff, 0x00000100,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0x78), 0xc0ffffff, 0x19000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xe0), 0xfffffeff, 0x00000100,
#endif
#if CK804_NUM == 1
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0x78), 0xc0ffffff, 0x19000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xe0), 0xfffffeff, 0x00000100,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0x78), 0xc0ffffff, 0x19000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xe0), 0xfffffeff, 0x00000100,
#endif
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000,
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000,
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120,
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010,
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000,
RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000,
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000,
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000,
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120,
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010,
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000,
RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000,
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x74, ~(0xffff), 0x0f008,
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x78, ~((0xff)|(0xff<<16)), (0x41<<16)|(0x32),
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x7c, ~(0xff<<16), (0xa0<<16),
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x74, ~(0xffff), 0x0f008,
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x78, ~((0xff)|(0xff<<16)), (0x41<<16)|(0x32),
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x7c, ~(0xff<<16), (0xa0<<16),
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x50), ~(0x1f000013), 0x15000013,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x64), ~(0x00000001), 0x00000001,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x68), ~(0x02000000), 0x02000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x70), ~(0x000f0000), 0x00040000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xa0), ~(0x000001ff), 0x00000150,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xac), ~(0xffff8f00), 0x02aa8b00,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x7c), ~(0x00000010), 0x00000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xc8), ~(0x0fff0fff), 0x000a000a,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xd0), ~(0xf0000000), 0x00000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xe0), ~(0xf0000000), 0x00000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x50), ~(0x1f000013), 0x15000013,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x64), ~(0x00000001), 0x00000001,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x68), ~(0x02000000), 0x02000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x70), ~(0x000f0000), 0x00040000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xa0), ~(0x000001ff), 0x00000150,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xac), ~(0xffff8f00), 0x02aa8b00,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x7c), ~(0x00000010), 0x00000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xc8), ~(0x0fff0fff), 0x000a000a,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xd0), ~(0xf0000000), 0x00000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xe0), ~(0xf0000000), 0x00000000,
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x04, ~((0x3ff<<0)|(0x3ff<<10)), (0x21<<0)|(0x22<<10),
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x04, ~((0x3ff<<0)|(0x3ff<<10)), (0x21<<0)|(0x22<<10),
//PANTA RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c<<10)|0x1b,
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1<<3), 0x00000000,
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1<<3), 0x00000000,
RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7<<4)|(1<<8)), (CK804_PCI_E_X<<4)|(1<<8),
RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7<<4)|(1<<8)), (CK804_PCI_E_X<<4)|(1<<8),
//SYSCTRL
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 8, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 9, ~(0xff), ((0<<4)|(1<<2)|(1<<0)),
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 8, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 9, ~(0xff), ((0<<4)|(1<<2)|(1<<0)),
#if CK804_USE_NIC == 1
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+0xa , 0, 0xf8), 0xffffffbf, 0x00000040,
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+19, ~(0xff), ((0<<4)|(1<<2)|(0<<0)),
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(0<<0)),
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(1<<0)),
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xe4), ~(1<<23), (1<<23),
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+0xa , 0, 0xf8), 0xffffffbf, 0x00000040,
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+19, ~(0xff), ((0<<4)|(1<<2)|(0<<0)),
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(0<<0)),
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(1<<0)),
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xe4), ~(1<<23), (1<<23),
#endif
#if CK804_USE_ACI == 1
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+0x0d, ~(0xff), ((0<<4)|(2<<2)|(0<<0)),
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+0x1a, ~(0xff), ((0<<4)|(2<<2)|(0<<0)),
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+0x0d, ~(0xff), ((0<<4)|(2<<2)|(0<<0)),
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+0x1a, ~(0xff), ((0<<4)|(2<<2)|(0<<0)),
#endif
#if CK804_NUM > 1
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 0, ~(3<<2), (0<<2),
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 0, ~(3<<2), (0<<2),
#endif
};
};
static const unsigned int ctrl_conf_slave[] = {
static const unsigned int ctrl_conf_slave[] = {
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0x8c), 0xffff0000, 0x00009880,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0x90), 0xffff000f, 0x000074a0,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0xa0), 0xfffff0ff, 0x00000a00,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0x8c), 0xffff0000, 0x00009880,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0x90), 0xffff000f, 0x000074a0,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0xa0), 0xfffff0ff, 0x00000a00,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x48), 0xfffffffd, 0x00000002,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x74), 0xfffff00f, 0x000009d0,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x8c), 0xffff0000, 0x0000007f,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xcc), 0xfffffff8, 0x00000003,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd0), 0xff000000, 0x00000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd4), 0xff000000, 0x00000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd8), 0xff000000, 0x00000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xdc), 0x7f000000, 0x00000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x48), 0xfffffffd, 0x00000002,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x74), 0xfffff00f, 0x000009d0,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x8c), 0xffff0000, 0x0000007f,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xcc), 0xfffffff8, 0x00000003,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd0), 0xff000000, 0x00000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd4), 0xff000000, 0x00000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd8), 0xff000000, 0x00000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xdc), 0x7f000000, 0x00000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xf0), 0xfffffffd, 0x00000002,
RES_PCI_IO,PCI_ADDR(CK804B_BUSN,CK804B_DEVN_BASE+1,0,0xf8), 0xffffffcf, 0x00000010,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xf0), 0xfffffffd, 0x00000002,
RES_PCI_IO,PCI_ADDR(CK804B_BUSN,CK804B_DEVN_BASE+1,0,0xf8), 0xffffffcf, 0x00000010,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x40), 0xfff8ffff, 0x00030000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x4c), 0xfe00ffff, 0x00440000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x74), 0xffffffc0, 0x00000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x40), 0xfff8ffff, 0x00030000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x4c), 0xfe00ffff, 0x00440000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x74), 0xffffffc0, 0x00000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0x78), 0xc0ffffff, 0x20000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN,CK804B_DEVN_BASE+1,0,0xe0), 0xfffffeff, 0x00000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xe8), 0xffffff00, 0x000000ff,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0x78), 0xc0ffffff, 0x20000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN,CK804B_DEVN_BASE+1,0,0xe0), 0xfffffeff, 0x00000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xe8), 0xffffff00, 0x000000ff,
RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000,
RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000,
RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120,
RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010,
RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000,
RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000,
RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000,
RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000,
RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120,
RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010,
RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000,
RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000,
RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x50), ~(0x1f000013), 0x15000013,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x64), ~(0x00000001), 0x00000001,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x68), ~(0x02000000), 0x02000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x70), ~(0x000f0000), 0x00040000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xa0), ~(0x000001ff), 0x00000150,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xac), ~(0xffff8f00), 0x02aa8b00,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x7c), ~(0x00000010), 0x00000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xc8), ~(0x0fff0fff), 0x000a000a,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xd0), ~(0xf0000000), 0x00000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xe0), ~(0xf0000000), 0x00000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x50), ~(0x1f000013), 0x15000013,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x64), ~(0x00000001), 0x00000001,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x68), ~(0x02000000), 0x02000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x70), ~(0x000f0000), 0x00040000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xa0), ~(0x000001ff), 0x00000150,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xac), ~(0xffff8f00), 0x02aa8b00,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x7c), ~(0x00000010), 0x00000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xc8), ~(0x0fff0fff), 0x000a000a,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xd0), ~(0xf0000000), 0x00000000,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xe0), ~(0xf0000000), 0x00000000,
RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x04, ~((0x3ff<<0)|(0x3ff<<10)), (0x21<<0)|(0x22<<10),
RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x04, ~((0x3ff<<0)|(0x3ff<<10)), (0x21<<0)|(0x22<<10),
//PANTA RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c<<10)|0x1b,
RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x80, ~(1<<3), 0x00000000,
RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x80, ~(1<<3), 0x00000000,
RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, ~((7<<4)|(1<<8)), (CK804B_PCI_E_X<<4)|(1<<8),
RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, ~((7<<4)|(1<<8)), (CK804B_PCI_E_X<<4)|(1<<8),
#if CK804_USE_NIC == 1
RES_PCI_IO, PCI_ADDR(0, CK804B_DEVN_BASE+0xa , 0, 0xf8), 0xffffffbf, 0x00000040,
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+19, ~(0xff), ((0<<4)|(1<<2)|(0<<0)),
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(0<<0)),
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(1<<0)),
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xe4), ~(1<<23), (1<<23),
RES_PCI_IO, PCI_ADDR(0, CK804B_DEVN_BASE+0xa , 0, 0xf8), 0xffffffbf, 0x00000040,
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+19, ~(0xff), ((0<<4)|(1<<2)|(0<<0)),
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(0<<0)),
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(1<<0)),
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xe4), ~(1<<23), (1<<23),
#endif
};
};
int j;
int j;
for(j=0; j<ck804_num; j++) {
if(busn[j] == 0) {
setup_resource_map_x_offset(ctrl_conf_master, sizeof(ctrl_conf_master)/sizeof(ctrl_conf_master[0]),
PCI_DEV(busn[0],0,0), io_base[0]);
continue;
}
for(j=0; j<ck804_num; j++) {
if(busn[j] == 0) {
setup_resource_map_x_offset(ctrl_conf_master, sizeof(ctrl_conf_master)/sizeof(ctrl_conf_master[0]),
PCI_DEV(busn[0],0,0), io_base[0]);
continue;
}
setup_resource_map_x_offset(ctrl_conf_slave, sizeof(ctrl_conf_slave)/sizeof(ctrl_conf_slave[0]),
PCI_DEV(busn[j],0,0), io_base[j]);
}
setup_resource_map_x_offset(ctrl_conf_slave, sizeof(ctrl_conf_slave)/sizeof(ctrl_conf_slave[0]),
PCI_DEV(busn[j],0,0), io_base[j]);
}
for(j=0; j< ck804_num; j++) {
// PCI-E (XSPLL) SS table 0x40, x044, 0x48
// SATA (SPPLL) SS table 0xb0, 0xb4, 0xb8
// CPU (PPLL) SS table 0xc0, 0xc4, 0xc8
setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0x40, io_base[j] + ANACTRL_IO_BASE+0x44,
io_base[j] + ANACTRL_IO_BASE+0x48, pcie_ss_tbl, 64);
setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0xb0, io_base[j] + ANACTRL_IO_BASE+0xb4,
io_base[j] + ANACTRL_IO_BASE+0xb8, sata_ss_tbl, 64);
//PANTA setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0xc0, io_base[j] + ANACTRL_IO_BASE+0xc4,
// io_base[j] + ANACTRL_IO_BASE+0xc8, cpu_ss_tbl, 64);
}
for(j=0; j< ck804_num; j++) {
// PCI-E (XSPLL) SS table 0x40, x044, 0x48
// SATA (SPPLL) SS table 0xb0, 0xb4, 0xb8
// CPU (PPLL) SS table 0xc0, 0xc4, 0xc8
setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0x40, io_base[j] + ANACTRL_IO_BASE+0x44,
io_base[j] + ANACTRL_IO_BASE+0x48, pcie_ss_tbl, 64);
setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0xb0, io_base[j] + ANACTRL_IO_BASE+0xb4,
io_base[j] + ANACTRL_IO_BASE+0xb8, sata_ss_tbl, 64);
//PANTA setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0xc0, io_base[j] + ANACTRL_IO_BASE+0xc4,
// io_base[j] + ANACTRL_IO_BASE+0xc8, cpu_ss_tbl, 64);
}
}
@ -362,12 +362,12 @@ static int ck804_early_setup_x(void)
for(i=0;i<4;i++) {
uint32_t id;
device_t dev;
if(i == 0) { // SB chain
dev = PCI_DEV(i*0x40, CK804_DEVN_BASE, 0);
}
else {
dev = PCI_DEV(i*0x40, CK804B_DEVN_BASE, 0);
}
if(i == 0) { // SB chain
dev = PCI_DEV(i*0x40, CK804_DEVN_BASE, 0);
}
else {
dev = PCI_DEV(i*0x40, CK804B_DEVN_BASE, 0);
}
id = pci_read_config32(dev, PCI_VENDOR_ID);
if(id == 0x005e10de) {
busn[ck804_num] = i * 0x40;
@ -384,20 +384,19 @@ static int ck804_early_setup_x(void)
static void hard_reset(void)
{
set_bios_reset();
set_bios_reset();
/* full reset */
outb(0x0a, 0x0cf9);
outb(0x0e, 0x0cf9);
/* full reset */
outb(0x0a, 0x0cf9);
outb(0x0e, 0x0cf9);
}
static void soft_reset(void)
{
set_bios_reset();
#if 1
/* link reset */
outb(0x02, 0x0cf9);
outb(0x06, 0x0cf9);
#endif
set_bios_reset();
/* link reset */
outb(0x02, 0x0cf9);
outb(0x06, 0x0cf9);
}

4
src/southbridge/nvidia/ck804/ck804_early_smbus.c
View File

@ -26,9 +26,9 @@ static void enable_smbus(void)
static int smbus_read_byte(unsigned device, unsigned address)
{
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
static int smbus_write_byte(unsigned device, unsigned address, unsigned char val)
{
return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val);
return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val);
}

4
src/southbridge/nvidia/ck804/ck804_enable_rom.c
View File

@ -3,9 +3,9 @@
* by yhlu@tyan.com
*/
#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
#define CK804_DEVN_BASE HT_CHAIN_END_UNITID_BASE
#define CK804_DEVN_BASE HT_CHAIN_END_UNITID_BASE
#else
#define CK804_DEVN_BASE HT_CHAIN_UNITID_BASE
#define CK804_DEVN_BASE HT_CHAIN_UNITID_BASE
#endif
static void ck804_enable_rom(void)

6
src/southbridge/nvidia/ck804/ck804_ht.c
View File

@ -11,11 +11,11 @@
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
pci_write_config32(dev, 0x40,
((device & 0xffff) << 16) | (vendor & 0xffff));
pci_write_config32(dev, 0x40,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
static struct pci_operations lops_pci = {
.set_subsystem = lpci_set_subsystem,
.set_subsystem = lpci_set_subsystem,
};
static struct device_operations ht_ops = {

24
src/southbridge/nvidia/ck804/ck804_ide.c
View File

@ -39,12 +39,12 @@ static void ide_init(struct device *dev)
pci_write_config16(dev, 0x50, word);
byte = 0x20 ; // Latency: 64-->32
pci_write_config8(dev, 0xd, byte);
byte = 0x20 ; // Latency: 64-->32
pci_write_config8(dev, 0xd, byte);
dword = pci_read_config32(dev, 0xf8);
dword |= 12;
pci_write_config32(dev, 0xf8, dword);
dword = pci_read_config32(dev, 0xf8);
dword |= 12;
pci_write_config32(dev, 0xf8, dword);
#if CONFIG_PCI_ROM_RUN == 1
pci_dev_init(dev);
#endif
@ -53,21 +53,21 @@ static void ide_init(struct device *dev)
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
pci_write_config32(dev, 0x40,
((device & 0xffff) << 16) | (vendor & 0xffff));
pci_write_config32(dev, 0x40,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
static struct pci_operations lops_pci = {
.set_subsystem = lpci_set_subsystem,
.set_subsystem = lpci_set_subsystem,
};
static struct device_operations ide_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = ide_init,
.scan_bus = 0,
// .enable = ck804_enable,
.ops_pci = &lops_pci,
.init = ide_init,
.scan_bus = 0,
// .enable = ck804_enable,
.ops_pci = &lops_pci,
};
static const struct pci_driver ide_driver __pci_driver = {

174
src/southbridge/nvidia/ck804/ck804_lpc.c
View File

@ -113,21 +113,21 @@ static void setup_ioapic(unsigned long ioapic_base)
static void lpc_common_init(device_t dev)
{
uint8_t byte;
uint32_t dword;
uint8_t byte;
uint32_t dword;
/* IO APIC initialization */
byte = pci_read_config8(dev, 0x74);
byte |= (1<<0); // enable APIC
pci_write_config8(dev, 0x74, byte);
dword = pci_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14
/* IO APIC initialization */
byte = pci_read_config8(dev, 0x74);
byte |= (1<<0); // enable APIC
pci_write_config8(dev, 0x74, byte);
dword = pci_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14
setup_ioapic(dword);
setup_ioapic(dword);
#if 1
dword = pci_read_config32(dev, 0xe4);
dword |= (1<<23);
pci_write_config32(dev, 0xe4, dword);
dword = pci_read_config32(dev, 0xe4);
dword |= (1<<23);
pci_write_config32(dev, 0xe4, dword);
#endif
}
@ -138,20 +138,20 @@ static void lpc_slave_init(device_t dev)
}
static void rom_dummy_write(device_t dev){
uint8_t old, new;
uint8_t old, new;
uint8_t *p;
old = pci_read_config8(dev, 0x88);
new = old | 0xc0;
if (new != old) {
pci_write_config8(dev, 0x88, new);
}
old = pci_read_config8(dev, 0x88);
new = old | 0xc0;
if (new != old) {
pci_write_config8(dev, 0x88, new);
}
// enable write
old = pci_read_config8(dev, 0x6d);
new = old | 0x01;
if (new != old) {
pci_write_config8(dev, 0x6d, new);
}
old = pci_read_config8(dev, 0x6d);
new = old | 0x01;
if (new != old) {
pci_write_config8(dev, 0x6d, new);
}
/* dummy write */
p = (uint8_t *)0xffffffe0;
@ -160,22 +160,22 @@ static void rom_dummy_write(device_t dev){
old = *p;
// disable write
old = pci_read_config8(dev, 0x6d);
new = old & 0xfe;
if (new != old) {
pci_write_config8(dev, 0x6d, new);
old = pci_read_config8(dev, 0x6d);
new = old & 0xfe;
if (new != old) {
pci_write_config8(dev, 0x6d, new);
}
}
}
#if 0
static void enable_hpet(struct device *dev)
{
unsigned long hpet_address;
unsigned long hpet_address;
pci_write_config32(dev,0x44, 0xfed00001);
hpet_address=pci_read_config32(dev,0x44)& 0xfffffffe;
printk_debug("enabling HPET @0x%x\n", hpet_address);
pci_write_config32(dev,0x44, 0xfed00001);
hpet_address=pci_read_config32(dev,0x44)& 0xfffffffe;
printk_debug("enabling HPET @0x%x\n", hpet_address);
}
#endif
@ -200,29 +200,29 @@ static void lpc_init(device_t dev)
#endif
/* power after power fail */
on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
get_option(&on, "power_on_after_fail");
byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
byte &= ~0x40;
if (!on) {
byte |= 0x40;
}
pci_write_config8(dev, PREVIOUS_POWER_STATE, byte);
printk_info("set power %s after power fail\n", on?"on":"off");
on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
get_option(&on, "power_on_after_fail");
byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
byte &= ~0x40;
if (!on) {
byte |= 0x40;
}
pci_write_config8(dev, PREVIOUS_POWER_STATE, byte);
printk_info("set power %s after power fail\n", on?"on":"off");
/* Throttle the CPU speed down for testing */
on = SLOW_CPU_OFF;
get_option(&on, "slow_cpu");
if(on) {
/* Throttle the CPU speed down for testing */
on = SLOW_CPU_OFF;
get_option(&on, "slow_cpu");
if(on) {
uint16_t pm10_bar;
uint32_t dword;
pm10_bar = (pci_read_config16(dev, 0x60)&0xff00);
outl(((on<<1)+0x10) ,(pm10_bar + 0x10));
dword = inl(pm10_bar + 0x10);
on = 8-on;
printk_debug("Throttling CPU %2d.%1.1d percent.\n",
(on*12)+(on>>1),(on&1)*5);
}
pm10_bar = (pci_read_config16(dev, 0x60)&0xff00);
outl(((on<<1)+0x10) ,(pm10_bar + 0x10));
dword = inl(pm10_bar + 0x10);
on = 8-on;
printk_debug("Throttling CPU %2d.%1.1d percent.\n",
(on*12)+(on>>1),(on&1)*5);
}
#if 0
// default is enabled
@ -258,8 +258,8 @@ static void lpc_init(device_t dev)
/* Initialize isa dma */
isa_dma_init();
/* Initialize the High Precision Event Timers */
// enable_hpet(dev);
/* Initialize the High Precision Event Timers */
// enable_hpet(dev);
rom_dummy_write(dev);
@ -279,12 +279,12 @@ static void ck804_lpc_read_resources(device_t dev)
}
compact_resources(dev);
/* Add an extra subtractive resource for both memory and I/O */
res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
/* Add an extra subtractive resource for both memory and I/O */
res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
}
@ -303,25 +303,25 @@ static void ck804_lpc_read_resources(device_t dev)
*/
static void ck804_lpc_enable_childrens_resources(device_t dev)
{
unsigned link;
unsigned link;
uint32_t reg, reg_var[4];
int i;
int var_num = 0;
reg = pci_read_config32(dev, 0xa0);
for (link = 0; link < dev->links; link++) {
device_t child;
for (child = dev->link[link].children; child; child = child->sibling) {
enable_resources(child);
for (link = 0; link < dev->links; link++) {
device_t child;
for (child = dev->link[link].children; child; child = child->sibling) {
enable_resources(child);
if(child->have_resources && (child->path.type == DEVICE_PATH_PNP)) {
for(i=0;i<child->resources;i++) {
struct resource *res;
unsigned long base, end; // don't need long long
unsigned long base, end; // don't need long long
res = &child->resource[i];
if(!(res->flags & IORESOURCE_IO)) continue;
base = res->base;
end = resource_end(res);
base = res->base;
end = resource_end(res);
printk_debug("ck804 lpc decode:%s, base=0x%08x, end=0x%08x\r\n",dev_path(child),base, end);
switch(base) {
case 0x3f8: // COM1
@ -344,8 +344,8 @@ static void ck804_lpc_enable_childrens_resources(device_t dev)
}
}
}
}
}
}
}
pci_write_config32(dev, 0xa0, reg);
for(i=0;i<var_num;i++) {
pci_write_config32(dev, 0xa8 + i*4, reg_var[i]);
@ -356,18 +356,18 @@ static void ck804_lpc_enable_childrens_resources(device_t dev)
static void ck804_lpc_enable_resources(device_t dev)
{
pci_dev_enable_resources(dev);
ck804_lpc_enable_childrens_resources(dev);
pci_dev_enable_resources(dev);
ck804_lpc_enable_childrens_resources(dev);
}
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
pci_write_config32(dev, 0x40,
((device & 0xffff) << 16) | (vendor & 0xffff));
pci_write_config32(dev, 0x40,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
static struct pci_operations lops_pci = {
.set_subsystem = lpci_set_subsystem,
.set_subsystem = lpci_set_subsystem,
};
static struct device_operations lpc_ops = {
@ -386,30 +386,30 @@ static const struct pci_driver lpc_driver __pci_driver = {
};
static const struct pci_driver lpc_driver_pro __pci_driver = {
.ops = &lpc_ops,
.vendor = PCI_VENDOR_ID_NVIDIA,
.device = PCI_DEVICE_ID_NVIDIA_CK804_PRO,
.ops = &lpc_ops,
.vendor = PCI_VENDOR_ID_NVIDIA,
.device = PCI_DEVICE_ID_NVIDIA_CK804_PRO,
};
#if CK804_CHIP_REV == 1
static const struct pci_driver lpc_driver_slave __pci_driver = {
.ops = &lpc_ops,
.vendor = PCI_VENDOR_ID_NVIDIA,
.device = PCI_DEVICE_ID_NVIDIA_CK804_SLAVE,
.ops = &lpc_ops,
.vendor = PCI_VENDOR_ID_NVIDIA,
.device = PCI_DEVICE_ID_NVIDIA_CK804_SLAVE,
};
#else
static struct device_operations lpc_slave_ops = {
.read_resources = ck804_lpc_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = lpc_slave_init,
// .enable = ck804_enable,
.read_resources = ck804_lpc_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = lpc_slave_init,
// .enable = ck804_enable,
.ops_pci = &lops_pci,
};
static const struct pci_driver lpc_driver_slave __pci_driver = {
.ops = &lpc_slave_ops,
.vendor = PCI_VENDOR_ID_NVIDIA,
.device = PCI_DEVICE_ID_NVIDIA_CK804_SLAVE,
.ops = &lpc_slave_ops,
.vendor = PCI_VENDOR_ID_NVIDIA,
.device = PCI_DEVICE_ID_NVIDIA_CK804_SLAVE,
};
#endif

50
src/southbridge/nvidia/ck804/ck804_nic.c
View File

@ -21,30 +21,30 @@ static void nic_init(struct device *dev)
static uint32_t nic_index = 0;
uint8_t *base;
struct resource *res;
uint8_t *base;
struct resource *res;
res = find_resource(dev, 0x10);
res = find_resource(dev, 0x10);
base = res->base;
base = res->base;
#define NvRegPhyInterface 0xC0
#define PHY_RGMII 0x10000000
writel(PHY_RGMII, base + NvRegPhyInterface);
writel(PHY_RGMII, base + NvRegPhyInterface);
old = dword = pci_read_config32(dev, 0x30);
dword &= ~(0xf);
dword |= 0xf;
if(old != dword) {
pci_write_config32(dev, 0x30 , dword);
}
old = dword = pci_read_config32(dev, 0x30);
dword &= ~(0xf);
dword |= 0xf;
if(old != dword) {
pci_write_config32(dev, 0x30 , dword);
}
conf = dev->chip_info;
conf = dev->chip_info;
if(conf->mac_eeprom_smbus != 0) {
// read MAC address from EEPROM at first
struct device *dev_eeprom;
struct device *dev_eeprom;
dev_eeprom = dev_find_slot_on_smbus(conf->mac_eeprom_smbus, conf->mac_eeprom_addr);
if(dev_eeprom) {
@ -65,11 +65,11 @@ static void nic_init(struct device *dev)
}
if(mac_l != 0xffffffff) {
mac_l += nic_index;
mac_h = 0;
for(i=5;i>=4;i--) {
mac_h = 0;
for(i=5;i>=4;i--) {
mac_h <<= 8;
mac_h += dat[i];
}
mac_h += dat[i];
}
eeprom_valid = 1;
}
}
@ -86,8 +86,8 @@ static void nic_init(struct device *dev)
// set that into NIC MMIO
#define NvRegMacAddrA 0xA8
#define NvRegMacAddrB 0xAC
writel(mac_l, base + NvRegMacAddrA);
writel(mac_h, base + NvRegMacAddrB);
writel(mac_l, base + NvRegMacAddrA);
writel(mac_h, base + NvRegMacAddrB);
#else
// set that into NIC
pci_write_config32(dev, 0xa8, mac_l);
@ -104,12 +104,12 @@ static void nic_init(struct device *dev)
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
pci_write_config32(dev, 0x40,
((device & 0xffff) << 16) | (vendor & 0xffff));
pci_write_config32(dev, 0x40,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
static struct pci_operations lops_pci = {
.set_subsystem = lpci_set_subsystem,
.set_subsystem = lpci_set_subsystem,
};
static struct device_operations nic_ops = {
@ -127,7 +127,7 @@ static const struct pci_driver nic_driver __pci_driver = {
.device = PCI_DEVICE_ID_NVIDIA_CK804_NIC,
};
static const struct pci_driver nic_bridge_driver __pci_driver = {
.ops = &nic_ops,
.vendor = PCI_VENDOR_ID_NVIDIA,
.device = PCI_DEVICE_ID_NVIDIA_CK804_NIC_BRIDGE,
.ops = &nic_ops,
.vendor = PCI_VENDOR_ID_NVIDIA,
.device = PCI_DEVICE_ID_NVIDIA_CK804_NIC_BRIDGE,
};

18
src/southbridge/nvidia/ck804/ck804_pci.c
View File

@ -26,16 +26,16 @@ static void pci_init(struct device *dev)
pci_write_config32(dev, 0x04, dword);
#if 0
word = pci_read_config16(dev, 0x48);
word |= (1<<0); /* MRL2MRM */
word |= (1<<2); /* MR2MRM */
pci_write_config16(dev, 0x48, word);
word = pci_read_config16(dev, 0x48);
word |= (1<<0); /* MRL2MRM */
word |= (1<<2); /* MR2MRM */
pci_write_config16(dev, 0x48, word);
#endif
#if 1
dword = pci_read_config32(dev, 0x4c);
dword |= 0x00440000; /*TABORT_SER_ENABLE Park Last Enable.*/
pci_write_config32(dev, 0x4c, dword);
dword = pci_read_config32(dev, 0x4c);
dword |= 0x00440000; /*TABORT_SER_ENABLE Park Last Enable.*/
pci_write_config32(dev, 0x4c, dword);
#endif
#if CONFIG_PCI_64BIT_PREF_MEM == 1
@ -61,12 +61,12 @@ static void pci_init(struct device *dev)
#endif
printk_debug("[0x50] <-- 0x%08x\n", dword);
pci_write_config32(dev, 0x50, dword); //TOM
pci_write_config32(dev, 0x50, dword); //TOM
}
static struct pci_operations lops_pci = {
.set_subsystem = 0,
.set_subsystem = 0,
};
static struct device_operations pci_ops = {

2
src/southbridge/nvidia/ck804/ck804_pcie.c
View File

@ -25,7 +25,7 @@ static void pcie_init(struct device *dev)
}
static struct pci_operations lops_pci = {
.set_subsystem = 0,
.set_subsystem = 0,
};
static struct device_operations pcie_ops = {

24
src/southbridge/nvidia/ck804/ck804_reset.c
View File

@ -6,26 +6,26 @@
#include <arch/io.h>
#define PCI_DEV(BUS, DEV, FN) ( \
(((BUS) & 0xFFF) << 20) | \
(((DEV) & 0x1F) << 15) | \
(((FN) & 0x7) << 12))
(((BUS) & 0xFFF) << 20) | \
(((DEV) & 0x1F) << 15) | \
(((FN) & 0x7) << 12))
typedef unsigned device_t;
static void pci_write_config32(device_t dev, unsigned where, unsigned value)
{
unsigned addr;
addr = (dev>>4) | where;
outl(0x80000000 | (addr & ~3), 0xCF8);
outl(value, 0xCFC);
unsigned addr;
addr = (dev>>4) | where;
outl(0x80000000 | (addr & ~3), 0xCF8);
outl(value, 0xCFC);
}
static unsigned pci_read_config32(device_t dev, unsigned where)
{
unsigned addr;
addr = (dev>>4) | where;
outl(0x80000000 | (addr & ~3), 0xCF8);
return inl(0xCFC);
unsigned addr;
addr = (dev>>4) | where;
outl(0x80000000 | (addr & ~3), 0xCF8);
return inl(0xCFC);
}
#include "../../../northbridge/amd/amdk8/reset_test.c"
@ -33,7 +33,7 @@ static unsigned pci_read_config32(device_t dev, unsigned where)
void hard_reset(void)
{
set_bios_reset();
/* Try rebooting through port 0xcf9 */
/* Try rebooting through port 0xcf9 */
outb((0 <<3)|(0<<2)|(1<<1), 0xcf9);
outb((0 <<3)|(1<<2)|(1<<1), 0xcf9);
}

113
src/southbridge/nvidia/ck804/ck804_sata.c
View File

@ -15,90 +15,85 @@ static void sata_com_reset(struct device *dev, unsigned reset)
// reset = 1 : reset
// reset = 0 : clear
{
uint32_t *base;
uint32_t *base;
uint32_t dword;
int loop;
base = (uint32_t *) pci_read_config32(dev, 0x24);
base = (uint32_t *) pci_read_config32(dev, 0x24);
printk_debug("base = %08x\r\n", base);
if(reset) {
*(base + 4) = 0xffffffff;
*(base + 0x44) = 0xffffffff;
}
if(reset) {
*(base + 4) = 0xffffffff;
*(base + 0x44) = 0xffffffff;
}
dword = *(base +8);
dword &= ~(0xf);
dword |= reset;
dword = *(base +8);
dword &= ~(0xf);
dword |= reset;
*(base + 8) = dword;
*(base + 0x48) = dword;
*(base + 8) = dword;
*(base + 0x48) = dword;
#if 0
udelay(1000);
dword &= ~(0xf);
*(base + 8) = dword;
*(base + 0x48) = dword;
*(base + 8) = dword;
*(base + 0x48) = dword;
#endif
if(reset) return;
if(reset) return;
dword = *(base+ 0);
dword = *(base+ 0);
printk_debug("*(base+0)=%08x\r\n",dword);
if(dword == 0x113) {
if(dword == 0x113) {
loop = 200000;// 2
do {
dword = *(base + 4);
if((dword & 0x10000)!=0) break;
if((dword & 0x10000)!=0) break;
udelay(10);
} while (--loop>0);
printk_debug("loop=%d, *(base+4)=%08x\r\n",loop, dword);
}
dword = *(base+ 0x40);
dword = *(base+ 0x40);
printk_debug("*(base+0x40)=%08x\r\n",dword);
if(dword == 0x113) {
if(dword == 0x113) {
loop = 200000;//2
do {
dword = *(base + 0x44);
if((dword & 0x10000)!=0) break;
dword = *(base + 0x44);
if((dword & 0x10000)!=0) break;
udelay(10);
} while (--loop>0);
} while (--loop>0);
printk_debug("loop=%d, *(base+0x44)=%08x\r\n",loop, dword);
}
}
static void sata_init(struct device *dev)
{
uint32_t dword;
uint32_t dword;
struct southbridge_nvidia_ck804_config *conf;
conf = dev->chip_info;
dword = pci_read_config32(dev, 0x50);
/* Ensure prefetch is disabled */
dword &= ~((1 << 15) | (1 << 13));
if (conf->sata1_enable) {
/* Enable secondary SATA interface */
dword |= (1<<0);
printk_debug("SATA S \t");
}
if (conf->sata0_enable) {
/* Enable primary SATA interface */
dword |= (1<<1);
printk_debug("SATA P \n");
}
dword = pci_read_config32(dev, 0x50);
/* Ensure prefetch is disabled */
dword &= ~((1 << 15) | (1 << 13));
if (conf->sata1_enable) {
/* Enable secondary SATA interface */
dword |= (1<<0);
printk_debug("SATA S \t");
}
if (conf->sata0_enable) {
/* Enable primary SATA interface */
dword |= (1<<1);
printk_debug("SATA P \n");
}
#if 0
// write back
dword |= (1<<12);
dword |= (1<<14);
dword |= (1<<12);
dword |= (1<<14);
#endif
#if 0
@ -112,28 +107,28 @@ static void sata_init(struct device *dev)
dword &= ~(0x1f<<24);
dword |= (0x15<<24);
#endif
pci_write_config32(dev, 0x50, dword);
pci_write_config32(dev, 0x50, dword);
#if 0
//SLUMBER_DURING_D3.
dword = pci_read_config32(dev, 0x7c);
dword &= ~(1<<4);
pci_write_config32(dev, 0x7c, dword);
dword = pci_read_config32(dev, 0x7c);
dword &= ~(1<<4);
pci_write_config32(dev, 0x7c, dword);
dword = pci_read_config32(dev, 0xd0);
dword &= ~(0xff<<24);
dword |= (0x68<<24);
pci_write_config32(dev, 0xd0, dword);
dword = pci_read_config32(dev, 0xe0);
dword &= ~(0xff<<24);
dword |= (0x68<<24);
dword = pci_read_config32(dev, 0xe0);
dword &= ~(0xff<<24);
dword |= (0x68<<24);
pci_write_config32(dev, 0xe0, dword);
#endif
dword = pci_read_config32(dev, 0xf8);
dword |= 2;
pci_write_config32(dev, 0xf8, dword);
dword = pci_read_config32(dev, 0xf8);
dword |= 2;
pci_write_config32(dev, 0xf8, dword);
#if 0
dword = pci_read_config32(dev, 0xac);
@ -148,11 +143,11 @@ static void sata_init(struct device *dev)
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
pci_write_config32(dev, 0x40,
((device & 0xffff) << 16) | (vendor & 0xffff));
pci_write_config32(dev, 0x40,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
static struct pci_operations lops_pci = {
.set_subsystem = lpci_set_subsystem,
.set_subsystem = lpci_set_subsystem,
};
static struct device_operations sata_ops = {
@ -172,7 +167,7 @@ static const struct pci_driver sata0_driver __pci_driver = {
};
static const struct pci_driver sata1_driver __pci_driver = {
.ops = &sata_ops,
.vendor = PCI_VENDOR_ID_NVIDIA,
.device = PCI_DEVICE_ID_NVIDIA_CK804_SATA1,
.ops = &sata_ops,
.vendor = PCI_VENDOR_ID_NVIDIA,
.device = PCI_DEVICE_ID_NVIDIA_CK804_SATA1,
};

88
src/southbridge/nvidia/ck804/ck804_smbus.c
View File

@ -15,88 +15,88 @@
static int lsmbus_recv_byte(device_t dev)
{
unsigned device;
struct resource *res;
unsigned device;
struct resource *res;
struct bus *pbus;
device = dev->path.u.i2c.device;
device = dev->path.u.i2c.device;
pbus = get_pbus_smbus(dev);
res = find_resource(pbus->dev, 0x20 + (pbus->link * 4));
res = find_resource(pbus->dev, 0x20 + (pbus->link * 4));
return do_smbus_recv_byte(res->base, device);
return do_smbus_recv_byte(res->base, device);
}
static int lsmbus_send_byte(device_t dev, uint8_t val)
{
unsigned device;
struct resource *res;
struct bus *pbus;
unsigned device;
struct resource *res;
struct bus *pbus;
device = dev->path.u.i2c.device;
pbus = get_pbus_smbus(dev);
device = dev->path.u.i2c.device;
pbus = get_pbus_smbus(dev);
res = find_resource(pbus->dev, 0x20 + (pbus->link * 4));
res = find_resource(pbus->dev, 0x20 + (pbus->link * 4));
return do_smbus_send_byte(res->base, device, val);
return do_smbus_send_byte(res->base, device, val);
}
static int lsmbus_read_byte(device_t dev, uint8_t address)
{
unsigned device;
struct resource *res;
struct bus *pbus;
unsigned device;
struct resource *res;
struct bus *pbus;
device = dev->path.u.i2c.device;
pbus = get_pbus_smbus(dev);
device = dev->path.u.i2c.device;
pbus = get_pbus_smbus(dev);
res = find_resource(pbus->dev, 0x20 + (pbus->link * 4));
res = find_resource(pbus->dev, 0x20 + (pbus->link * 4));
return do_smbus_read_byte(res->base, device, address);
return do_smbus_read_byte(res->base, device, address);
}
static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val)
{
unsigned device;
struct resource *res;
struct bus *pbus;
unsigned device;
struct resource *res;
struct bus *pbus;
device = dev->path.u.i2c.device;
pbus = get_pbus_smbus(dev);
device = dev->path.u.i2c.device;
pbus = get_pbus_smbus(dev);
res = find_resource(pbus->dev, 0x20 + (pbus->link * 4));
res = find_resource(pbus->dev, 0x20 + (pbus->link * 4));
return do_smbus_write_byte(res->base, device, address, val);
return do_smbus_write_byte(res->base, device, address, val);
}
static struct smbus_bus_operations lops_smbus_bus = {
.recv_byte = lsmbus_recv_byte,
.send_byte = lsmbus_send_byte,
.read_byte = lsmbus_read_byte,
.write_byte = lsmbus_write_byte,
.recv_byte = lsmbus_recv_byte,
.send_byte = lsmbus_send_byte,
.read_byte = lsmbus_read_byte,
.write_byte = lsmbus_write_byte,
};
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
pci_write_config32(dev, 0x40,
((device & 0xffff) << 16) | (vendor & 0xffff));
pci_write_config32(dev, 0x40,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
static struct pci_operations lops_pci = {
.set_subsystem = lpci_set_subsystem,
.set_subsystem = lpci_set_subsystem,
};
static struct device_operations smbus_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = 0,
.scan_bus = scan_static_bus,
// .enable = ck804_enable,
.ops_pci = &lops_pci,
.ops_smbus_bus = &lops_smbus_bus,
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = 0,
.scan_bus = scan_static_bus,
// .enable = ck804_enable,
.ops_pci = &lops_pci,
.ops_smbus_bus = &lops_smbus_bus,
};
static const struct pci_driver smbus_driver __pci_driver = {
.ops = &smbus_ops,
.vendor = PCI_VENDOR_ID_NVIDIA,
.device = PCI_DEVICE_ID_NVIDIA_CK804_SM,
.ops = &smbus_ops,
.vendor = PCI_VENDOR_ID_NVIDIA,
.device = PCI_DEVICE_ID_NVIDIA_CK804_SM,
};

132
src/southbridge/nvidia/ck804/ck804_smbus.h
View File

@ -55,75 +55,75 @@ static int smbus_wait_until_done(unsigned smbus_io_base)
}
static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device)
{
unsigned char global_status_register;
unsigned char byte;
unsigned char global_status_register;
unsigned char byte;
#if 0
// Don't need, when you write to PRTCL, the status will be cleared automatically
if (smbus_wait_until_ready(smbus_io_base) < 0) {
return -2;
}
if (smbus_wait_until_ready(smbus_io_base) < 0) {
return -2;
}
#endif
/* set the device I'm talking too */
outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBXMITADD);
smbus_delay();
/* set the command/address... */
outb(0, smbus_io_base + SMBHSTCMD);
smbus_delay();
/* byte data recv */
outb(0x05, smbus_io_base + SMBHSTPRTCL);
smbus_delay();
/* set the device I'm talking too */
outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBXMITADD);
smbus_delay();
/* set the command/address... */
outb(0, smbus_io_base + SMBHSTCMD);
smbus_delay();
/* byte data recv */
outb(0x05, smbus_io_base + SMBHSTPRTCL);
smbus_delay();
/* poll for transaction completion */
if (smbus_wait_until_done(smbus_io_base) < 0) {
return -3;
}
/* poll for transaction completion */
if (smbus_wait_until_done(smbus_io_base) < 0) {
return -3;
}
global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */
global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */
/* read results of transaction */
byte = inb(smbus_io_base + SMBHSTDAT0);
/* read results of transaction */
byte = inb(smbus_io_base + SMBHSTDAT0);
if (global_status_register != 0x80) { // lose check, otherwise it should be 0
return -1;
}
return byte;
if (global_status_register != 0x80) { // lose check, otherwise it should be 0
return -1;
}
return byte;
}
static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned char val)
{
unsigned global_status_register;
unsigned global_status_register;
#if 0
// Don't need, when you write to PRTCL, the status will be cleared automatically
if (smbus_wait_until_ready(smbus_io_base) < 0) {
return -2;
}
if (smbus_wait_until_ready(smbus_io_base) < 0) {
return -2;
}
#endif
outb(val, smbus_io_base + SMBHSTDAT0);
smbus_delay();
outb(val, smbus_io_base + SMBHSTDAT0);
smbus_delay();
/* set the device I'm talking too */
outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD);
smbus_delay();
/* set the device I'm talking too */
outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD);
smbus_delay();
outb(0, smbus_io_base + SMBHSTCMD);
smbus_delay();
outb(0, smbus_io_base + SMBHSTCMD);
smbus_delay();
/* set up for a byte data write */
outb(0x04, smbus_io_base + SMBHSTPRTCL);
smbus_delay();
/* set up for a byte data write */
outb(0x04, smbus_io_base + SMBHSTPRTCL);
smbus_delay();
/* poll for transaction completion */
if (smbus_wait_until_done(smbus_io_base) < 0) {
return -3;
}
global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */;
/* poll for transaction completion */
if (smbus_wait_until_done(smbus_io_base) < 0) {
return -3;
}
global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */;
if (global_status_register != 0x80) {
return -1;
}
return 0;
if (global_status_register != 0x80) {
return -1;
}
return 0;
}
static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address)
{
@ -165,38 +165,38 @@ static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned
static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, unsigned address, unsigned char val)
{
unsigned global_status_register;
unsigned global_status_register;
#if 0
// Don't need, when you write to PRTCL, the status will be cleared automatically
if (smbus_wait_until_ready(smbus_io_base) < 0) {
return -2;
}
if (smbus_wait_until_ready(smbus_io_base) < 0) {
return -2;
}
#endif
outb(val, smbus_io_base + SMBHSTDAT0);
smbus_delay();
/* set the device I'm talking too */
outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD);
/* set the device I'm talking too */
outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD);
smbus_delay();
outb(address & 0xff, smbus_io_base + SMBHSTCMD);
outb(address & 0xff, smbus_io_base + SMBHSTCMD);
smbus_delay();
/* set up for a byte data write */
outb(0x06, smbus_io_base + SMBHSTPRTCL);
/* set up for a byte data write */
outb(0x06, smbus_io_base + SMBHSTPRTCL);
smbus_delay();
/* poll for transaction completion */
if (smbus_wait_until_done(smbus_io_base) < 0) {
return -3;
}
global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */;
/* poll for transaction completion */
if (smbus_wait_until_done(smbus_io_base) < 0) {
return -3;
}
global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */;
if (global_status_register != 0x80) {
return -1;
}
return 0;
if (global_status_register != 0x80) {
return -1;
}
return 0;
}

6
src/southbridge/nvidia/ck804/ck804_usb.c
View File

@ -24,11 +24,11 @@ static void usb1_init(struct device *dev) {
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
pci_write_config32(dev, 0x40,
((device & 0xffff) << 16) | (vendor & 0xffff));
pci_write_config32(dev, 0x40,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
static struct pci_operations lops_pci = {
.set_subsystem = lpci_set_subsystem,
.set_subsystem = lpci_set_subsystem,
};
static struct device_operations usb_ops = {

14
src/southbridge/nvidia/ck804/ck804_usb2.c
View File

@ -12,19 +12,19 @@
static void usb2_init(struct device *dev)
{
uint32_t dword;
dword = pci_read_config32(dev, 0xf8);
dword |= 40;
pci_write_config32(dev, 0xf8, dword);
uint32_t dword;
dword = pci_read_config32(dev, 0xf8);
dword |= 40;
pci_write_config32(dev, 0xf8, dword);
}
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
pci_write_config32(dev, 0x40,
((device & 0xffff) << 16) | (vendor & 0xffff));
pci_write_config32(dev, 0x40,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
static struct pci_operations lops_pci = {
.set_subsystem = lpci_set_subsystem,
.set_subsystem = lpci_set_subsystem,
};
static struct device_operations usb2_ops = {

8
src/southbridge/nvidia/ck804/romstrap.inc
View File

@ -8,10 +8,10 @@
.globl __romstrap_start
__romstrap_start:
rstables:
.long 0x2b16d065
.long 0x0
.long 0x0
.long linkedlist
.long 0x2b16d065
.long 0x0
.long 0x0
.long linkedlist
linkedlist:
.long 0x0003001C // 10h