Fix whitespace in tyan s289{1,2,5} files. Also removes some #if 0 and #if 1
that don't seem to clarify anything. Abuild tested. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3583 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
parent
297b91c6cd
commit
a67c354cbf
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@ -14,9 +14,9 @@ end
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## Compute the start location and size size of
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## The coreboot bootloader.
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##
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default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
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default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
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default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
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default CONFIG_ROM_PAYLOAD = 1
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default CONFIG_ROM_PAYLOAD = 1
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##
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## Compute where this copy of coreboot will start in the boot rom
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@ -33,7 +33,7 @@ default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
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default XIP_ROM_SIZE=65536
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default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
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arch i386 end
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arch i386 end
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##
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@ -53,46 +53,42 @@ if HAVE_PIRQ_TABLE object irq_tables.o end
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if USE_DCACHE_RAM
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if CONFIG_USE_INIT
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makerule ./auto.o
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depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
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action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
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end
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else
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makerule ./auto.inc
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depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
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action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
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action "perl -e 's/.rodata/.rom.data/g' -pi $@"
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action "perl -e 's/.text/.section .rom.text/g' -pi $@"
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end
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if CONFIG_USE_INIT
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makerule ./auto.o
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depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
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action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
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end
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else
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makerule ./auto.inc
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depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
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action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
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action "perl -e 's/.rodata/.rom.data/g' -pi $@"
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action "perl -e 's/.text/.section .rom.text/g' -pi $@"
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end
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end
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else
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##
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## Romcc output
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##
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makerule ./failover.E
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depends "$(MAINBOARD)/failover.c ../romcc"
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action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
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depends "$(MAINBOARD)/failover.c ../romcc"
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action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
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end
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makerule ./failover.inc
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depends "$(MAINBOARD)/failover.c ../romcc"
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action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
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depends "$(MAINBOARD)/failover.c ../romcc"
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action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
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end
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makerule ./auto.E
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depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
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action "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
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depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
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action "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
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end
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makerule ./auto.inc
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depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
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action "../romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
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depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
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action "../romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
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end
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end
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@ -101,13 +97,12 @@ end
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## Build our 16 bit and 32 bit coreboot entry code
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##
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if USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/entry16.inc
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ldscript /cpu/x86/16bit/entry16.lds
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mainboardinit cpu/x86/16bit/entry16.inc
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ldscript /cpu/x86/16bit/entry16.lds
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end
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mainboardinit cpu/x86/32bit/entry32.inc
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if USE_DCACHE_RAM
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if CONFIG_USE_INIT
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ldscript /cpu/x86/32bit/entry32.lds
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@ -121,12 +116,12 @@ end
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##
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## Build our reset vector (This is where coreboot is entered)
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##
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if USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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if USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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else
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/x86/32bit/reset32.lds
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/x86/32bit/reset32.lds
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end
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if USE_DCACHE_RAM
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@ -157,7 +152,7 @@ if USE_DCACHE_RAM
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end
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###
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### This is the early phase of coreboot startup
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### This is the early phase of coreboot startup
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### Things are delicate and we test to see if we should
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### failover to another image.
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###
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@ -195,171 +190,169 @@ else
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end
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##
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## Include the secondary Configuration files
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## Include the secondary Configuration files
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##
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if CONFIG_CHIP_NAME
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config chip.h
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config chip.h
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end
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# sample config for tyan/s2891
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chip northbridge/amd/amdk8/root_complex
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device apic_cluster 0 on
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chip cpu/amd/socket_940
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device apic 0 on end
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end
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end
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device apic_cluster 0 on
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chip cpu/amd/socket_940
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device apic 0 on end
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end
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end
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device pci_domain 0 on
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chip northbridge/amd/amdk8 #mc0
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device pci 18.0 on # northbridge
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# devices on link 0, link 0 == LDT 0
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chip southbridge/nvidia/ck804
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device pci 18.0 on # northbridge
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# devices on link 0, link 0 == LDT 0
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chip southbridge/nvidia/ck804
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device pci 0.0 on end # HT
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device pci 1.0 on # LPC
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chip superio/winbond/w83627hf
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device pnp 2e.0 off # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 2e.1 off # Parallel Port
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io 0x60 = 0x378
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irq 0x70 = 7
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end
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device pnp 2e.2 on # Com1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.3 off # Com2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 2e.5 on # Keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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irq 0x72 = 12
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end
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device pnp 2e.6 off # CIR
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io 0x60 = 0x100
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end
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device pnp 2e.7 off # GAME_MIDI_GIPO1
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io 0x60 = 0x220
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io 0x62 = 0x300
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irq 0x70 = 9
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end
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device pnp 2e.8 off end # GPIO2
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device pnp 2e.9 off end # GPIO3
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device pnp 2e.a off end # ACPI
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device pnp 2e.b off # HW Monitor
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io 0x60 = 0x290
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irq 0x70 = 5
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end
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end
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device pci 1.0 on # LPC
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chip superio/winbond/w83627hf
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device pnp 2e.0 off # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 2e.1 off # Parallel Port
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io 0x60 = 0x378
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irq 0x70 = 7
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end
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device pnp 2e.2 on # Com1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.3 off # Com2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 2e.5 on # Keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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irq 0x72 = 12
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end
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device pnp 2e.6 off # CIR
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io 0x60 = 0x100
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end
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device pnp 2e.7 off # GAME_MIDI_GIPO1
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io 0x60 = 0x220
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io 0x62 = 0x300
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irq 0x70 = 9
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end
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device pnp 2e.8 off end # GPIO2
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device pnp 2e.9 off end # GPIO3
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device pnp 2e.a off end # ACPI
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device pnp 2e.b off # HW Monitor
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io 0x60 = 0x290
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irq 0x70 = 5
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end
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end
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end
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device pci 1.1 on # SM 0
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# chip drivers/generic/generic #dimm 0-0-0
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# device i2c 50 on end
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# end
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# chip drivers/generic/generic #dimm 0-0-1
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# device i2c 51 on end
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# end
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# chip drivers/generic/generic #dimm 0-1-0
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# device i2c 52 on end
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# end
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# chip drivers/generic/generic #dimm 0-1-1
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# device i2c 53 on end
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# end
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# chip drivers/generic/generic #dimm 1-0-0
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# device i2c 54 on end
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# end
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# chip drivers/generic/generic #dimm 1-0-1
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# device i2c 55 on end
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# end
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# chip drivers/generic/generic #dimm 1-1-0
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# device i2c 56 on end
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# end
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# chip drivers/generic/generic #dimm 1-1-1
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# device i2c 57 on end
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# end
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end # SM
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# device pci 1.1 on # SM 1
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device pci 1.1 on # SM 0
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# chip drivers/generic/generic #dimm 0-0-0
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# device i2c 50 on end
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# end
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# chip drivers/generic/generic #dimm 0-0-1
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# device i2c 51 on end
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# end
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# chip drivers/generic/generic #dimm 0-1-0
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# device i2c 52 on end
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# end
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# chip drivers/generic/generic #dimm 0-1-1
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# device i2c 53 on end
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# end
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# chip drivers/generic/generic #dimm 1-0-0
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# device i2c 54 on end
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# end
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# chip drivers/generic/generic #dimm 1-0-1
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# device i2c 55 on end
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# end
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# chip drivers/generic/generic #dimm 1-1-0
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# device i2c 56 on end
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# end
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# chip drivers/generic/generic #dimm 1-1-1
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# device i2c 57 on end
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# end
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end # SM
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# device pci 1.1 on # SM 1
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# chip drivers/i2c/adm1027 # ADT7463A CPU0 temp, SYS FAN 2/3/4
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# device i2c 2d on end
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# end
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# chip drivers/i2c/adm1027 # ADT7463A CPU1 temp, CPU0/1 FAN , SYS FAN 1/5
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# device i2c 2e on end
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# end
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# chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 6/7, SB FAN
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# device i2c 2a on end
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# end
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# chip drivers/generic/generic # Winbond HWM 0x92
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# device i2c 49 on end
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# end
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# chip drivers/generic/generic # Winbond HWM 0x94
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# device i2c 4a on end
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# end
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# device i2c 2d on end
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# end
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# chip drivers/i2c/adm1027 # ADT7463A CPU1 temp, CPU0/1 FAN , SYS FAN 1/5
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# device i2c 2e on end
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# end
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# chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 6/7, SB FAN
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# device i2c 2a on end
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# end
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# chip drivers/generic/generic # Winbond HWM 0x92
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# device i2c 49 on end
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# end
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# chip drivers/generic/generic # Winbond HWM 0x94
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# device i2c 4a on end
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# end
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# end #SM
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device pci 2.0 on end # USB 1.1
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device pci 2.1 on end # USB 2
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device pci 4.0 off end # ACI
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device pci 4.1 off end # MCI
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device pci 6.0 on end # IDE
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device pci 7.0 on end # SATA 1
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device pci 8.0 on end # SATA 0
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device pci 9.0 on # PCI
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device pci 2.0 on end # USB 1.1
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device pci 2.1 on end # USB 2
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device pci 4.0 off end # ACI
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device pci 4.1 off end # MCI
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device pci 6.0 on end # IDE
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device pci 7.0 on end # SATA 1
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device pci 8.0 on end # SATA 0
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device pci 9.0 on # PCI
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# chip drivers/ati/ragexl
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chip drivers/pci/onboard
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device pci 7.0 on end
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#register "rom_address" = "0xfff80000" #for 512K
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register "rom_address" = "0xfff00000" #for 1M
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end
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chip drivers/pci/onboard
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device pci 7.0 on end
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#register "rom_address" = "0xfff80000" #for 512K
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register "rom_address" = "0xfff00000" #for 1M
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end
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end
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device pci a.0 off end # NIC
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device pci b.0 off end # PCI E 3
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device pci c.0 off end # PCI E 2
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device pci d.0 on end # PCI E 1
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device pci e.0 on end # PCI E 0
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register "ide0_enable" = "1"
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register "ide1_enable" = "1"
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register "sata0_enable" = "1"
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register "sata1_enable" = "1"
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device pci a.0 off end # NIC
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device pci b.0 off end # PCI E 3
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device pci c.0 off end # PCI E 2
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device pci d.0 on end # PCI E 1
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device pci e.0 on end # PCI E 0
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register "ide0_enable" = "1"
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register "ide1_enable" = "1"
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register "sata0_enable" = "1"
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register "sata1_enable" = "1"
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end
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end # device pci 18.0
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end # device pci 18.0
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device pci 18.0 on end # Link 1
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device pci 18.0 on
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# devices on link 2, link 2 == LDT 2
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chip southbridge/amd/amd8131
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# the on/off keyword is mandatory
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device pci 0.0 on end
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device pci 0.1 on end
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device pci 1.0 on
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chip drivers/pci/onboard
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device pci 9.0 on end
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# devices on link 2, link 2 == LDT 2
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chip southbridge/amd/amd8131
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# the on/off keyword is mandatory
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device pci 0.0 on end
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device pci 0.1 on end
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||||
device pci 1.0 on
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chip drivers/pci/onboard
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device pci 9.0 on end
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||||
device pci 9.1 on end
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||||
end
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||||
end
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||||
end
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||||
device pci 1.1 on end
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||||
end
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||||
device pci 1.1 on end
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||||
end
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||||
end # device pci 18.0
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device pci 18.1 on end
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device pci 18.2 on end
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device pci 18.3 on end
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end #mc0
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||||
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end # pci_domain
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# chip drivers/generic/debug
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# device pnp 0.0 off end # chip name
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# device pnp 0.1 off end # pci_regs_all
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# device pnp 0.2 off end # mem
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# device pnp 0.3 off end # cpuid
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# device pnp 0.4 off end # smbus_regs_all
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# device pnp 0.5 off end # dual core msr
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# device pnp 0.6 off end # cache size
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# device pnp 0.7 off end # tsc
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||||
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# chip drivers/generic/debug
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# device pnp 0.0 off end # chip name
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# device pnp 0.1 off end # pci_regs_all
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# device pnp 0.2 off end # mem
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# device pnp 0.3 off end # cpuid
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# device pnp 0.4 off end # smbus_regs_all
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# device pnp 0.5 off end # dual core msr
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# device pnp 0.6 off end # cache size
|
||||
# device pnp 0.7 off end # tsc
|
||||
# device pnp 0.8 on end # hard_reset
|
||||
# end
|
||||
# end
|
||||
end # root_complex
|
||||
|
|
|
@ -30,9 +30,9 @@ uses USE_OPTION_TABLE
|
|||
uses LB_CKS_RANGE_START
|
||||
uses LB_CKS_RANGE_END
|
||||
uses LB_CKS_LOC
|
||||
uses MAINBOARD
|
||||
uses MAINBOARD_PART_NUMBER
|
||||
uses MAINBOARD_VENDOR
|
||||
uses MAINBOARD
|
||||
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
|
||||
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
|
||||
uses COREBOOT_EXTRA_VERSION
|
||||
|
@ -75,7 +75,6 @@ uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
|
|||
|
||||
uses CONFIG_LB_MEM_TOPK
|
||||
|
||||
|
||||
## ROM_SIZE is the size of boot ROM that this board will use.
|
||||
#512K bytes
|
||||
default ROM_SIZE=524288
|
||||
|
@ -83,7 +82,6 @@ default ROM_SIZE=524288
|
|||
#1M bytes
|
||||
#default ROM_SIZE=1048576
|
||||
|
||||
|
||||
##
|
||||
## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
|
||||
##
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
#define ASSEMBLY 1
|
||||
|
||||
|
||||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <arch/io.h>
|
||||
|
@ -33,20 +33,20 @@
|
|||
|
||||
static void hard_reset(void)
|
||||
{
|
||||
set_bios_reset();
|
||||
set_bios_reset();
|
||||
|
||||
/* full reset */
|
||||
/* full reset */
|
||||
outb(0x0a, 0x0cf9);
|
||||
outb(0x0e, 0x0cf9);
|
||||
outb(0x0e, 0x0cf9);
|
||||
}
|
||||
|
||||
static void soft_reset(void)
|
||||
{
|
||||
set_bios_reset();
|
||||
set_bios_reset();
|
||||
#if 1
|
||||
/* link reset */
|
||||
/* link reset */
|
||||
outb(0x02, 0x0cf9);
|
||||
outb(0x06, 0x0cf9);
|
||||
outb(0x06, 0x0cf9);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
@ -69,15 +69,14 @@ static inline int spd_read_byte(unsigned device, unsigned address)
|
|||
}
|
||||
|
||||
#define QRANK_DIMM_SUPPORT 1
|
||||
|
||||
#include "northbridge/amd/amdk8/raminit.c"
|
||||
#include "northbridge/amd/amdk8/coherent_ht.c"
|
||||
#include "sdram/generic_sdram.c"
|
||||
|
||||
/* tyan does not want the default */
|
||||
#include "resourcemap.c"
|
||||
/* tyan does not want the default */
|
||||
#include "resourcemap.c"
|
||||
|
||||
#define FIRST_CPU 1
|
||||
#define FIRST_CPU 1
|
||||
#define SECOND_CPU 1
|
||||
#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
|
||||
|
||||
|
@ -112,38 +111,36 @@ static void main(unsigned long bist)
|
|||
#endif
|
||||
};
|
||||
|
||||
int needs_reset;
|
||||
int needs_reset;
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
struct node_core_id id;
|
||||
struct node_core_id id;
|
||||
#else
|
||||
unsigned nodeid;
|
||||
unsigned nodeid;
|
||||
#endif
|
||||
|
||||
if (bist == 0) {
|
||||
k8_init_and_stop_secondaries();
|
||||
}
|
||||
if (bist == 0) {
|
||||
k8_init_and_stop_secondaries();
|
||||
}
|
||||
|
||||
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
|
||||
uart_init();
|
||||
console_init();
|
||||
|
||||
// post_code(0x32);
|
||||
|
||||
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
|
||||
uart_init();
|
||||
console_init();
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
report_bist_failure(bist);
|
||||
|
||||
setup_s2891_resource_map();
|
||||
setup_s2891_resource_map();
|
||||
|
||||
needs_reset = setup_coherent_ht_domain();
|
||||
|
||||
|
||||
needs_reset |= ht_setup_chains_x();
|
||||
|
||||
needs_reset |= ck804_early_setup_x();
|
||||
needs_reset |= ck804_early_setup_x();
|
||||
|
||||
if (needs_reset) {
|
||||
print_info("ht reset -\r\n");
|
||||
soft_reset();
|
||||
}
|
||||
if (needs_reset) {
|
||||
print_info("ht reset -\r\n");
|
||||
soft_reset();
|
||||
}
|
||||
|
||||
enable_smbus();
|
||||
|
||||
|
|
|
@ -8,7 +8,6 @@
|
|||
#define SET_NB_CFG_54 1
|
||||
#endif
|
||||
|
||||
|
||||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <arch/io.h>
|
||||
|
@ -21,17 +20,6 @@
|
|||
#include "arch/i386/lib/console.c"
|
||||
#include "ram/ramtest.c"
|
||||
|
||||
#if 0
|
||||
static void post_code(uint8_t value) {
|
||||
#if 1
|
||||
int i;
|
||||
for(i=0;i<0x80000;i++) {
|
||||
outb(value, 0x80);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
#include <cpu/amd/model_fxx_rev.h>
|
||||
|
||||
#include "northbridge/amd/amdk8/incoherent_ht.c"
|
||||
|
@ -54,7 +42,6 @@ static void post_code(uint8_t value) {
|
|||
|
||||
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
|
||||
|
||||
|
||||
static void memreset_setup(void)
|
||||
{
|
||||
}
|
||||
|
@ -78,7 +65,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
|
|||
#include "sdram/generic_sdram.c"
|
||||
|
||||
/* tyan does not want the default */
|
||||
#include "resourcemap.c"
|
||||
#include "resourcemap.c"
|
||||
|
||||
#include "cpu/amd/dualcore/dualcore.c"
|
||||
|
||||
|
@ -92,7 +79,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
|
|||
|
||||
#include "cpu/amd/model_fxx/init_cpus.c"
|
||||
|
||||
|
||||
#if USE_FALLBACK_IMAGE == 1
|
||||
|
||||
#include "southbridge/nvidia/ck804/ck804_enable_rom.c"
|
||||
|
@ -101,28 +87,28 @@ static inline int spd_read_byte(unsigned device, unsigned address)
|
|||
static void sio_setup(void)
|
||||
{
|
||||
|
||||
unsigned value;
|
||||
uint32_t dword;
|
||||
uint8_t byte;
|
||||
unsigned value;
|
||||
uint32_t dword;
|
||||
uint8_t byte;
|
||||
|
||||
/* subject decoding*/
|
||||
byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
|
||||
byte |= 0x20;
|
||||
pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
|
||||
/* subject decoding*/
|
||||
byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
|
||||
byte |= 0x20;
|
||||
pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
|
||||
|
||||
/* LPC Positive Decode 0 */
|
||||
dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
|
||||
/* Serial 0, Serial 1 */
|
||||
dword |= (1<<0) | (1<<1);
|
||||
pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
|
||||
/* LPC Positive Decode 0 */
|
||||
dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
|
||||
/* Serial 0, Serial 1 */
|
||||
dword |= (1<<0) | (1<<1);
|
||||
pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
|
||||
|
||||
#if 1
|
||||
/* s2891 has onboard LPC port 80 */
|
||||
/*Hope I can enable port 80 here
|
||||
It will decode port 80 to LPC, If you are using PCI post code you can not do this */
|
||||
dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4);
|
||||
dword |= (1<<16);
|
||||
pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword);
|
||||
#if 1
|
||||
/* s2891 has onboard LPC port 80 */
|
||||
/*Hope I can enable port 80 here
|
||||
It will decode port 80 to LPC, If you are using PCI post code you can not do this */
|
||||
dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4);
|
||||
dword |= (1<<16);
|
||||
pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword);
|
||||
|
||||
#endif
|
||||
|
||||
|
@ -130,48 +116,48 @@ static void sio_setup(void)
|
|||
|
||||
void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
{
|
||||
unsigned last_boot_normal_x = last_boot_normal();
|
||||
unsigned last_boot_normal_x = last_boot_normal();
|
||||
|
||||
/* Is this a cpu only reset? or Is this a secondary cpu? */
|
||||
if ((cpu_init_detectedx) || (!boot_cpu())) {
|
||||
if (last_boot_normal_x) {
|
||||
goto normal_image;
|
||||
} else {
|
||||
goto fallback_image;
|
||||
}
|
||||
}
|
||||
/* Is this a cpu only reset? or Is this a secondary cpu? */
|
||||
if ((cpu_init_detectedx) || (!boot_cpu())) {
|
||||
if (last_boot_normal_x) {
|
||||
goto normal_image;
|
||||
} else {
|
||||
goto fallback_image;
|
||||
}
|
||||
}
|
||||
|
||||
/* Nothing special needs to be done to find bus 0 */
|
||||
/* Allow the HT devices to be found */
|
||||
/* Nothing special needs to be done to find bus 0 */
|
||||
/* Allow the HT devices to be found */
|
||||
|
||||
enumerate_ht_chain();
|
||||
enumerate_ht_chain();
|
||||
|
||||
sio_setup();
|
||||
sio_setup();
|
||||
|
||||
/* Setup the ck804 */
|
||||
ck804_enable_rom();
|
||||
/* Setup the ck804 */
|
||||
ck804_enable_rom();
|
||||
|
||||
/* Is this a deliberate reset by the bios */
|
||||
// post_code(0x22);
|
||||
if (bios_reset_detected() && last_boot_normal_x) {
|
||||
goto normal_image;
|
||||
}
|
||||
/* This is the primary cpu how should I boot? */
|
||||
else if (do_normal_boot()) {
|
||||
goto normal_image;
|
||||
}
|
||||
else {
|
||||
goto fallback_image;
|
||||
}
|
||||
/* Is this a deliberate reset by the bios */
|
||||
// post_code(0x22);
|
||||
if (bios_reset_detected() && last_boot_normal_x) {
|
||||
goto normal_image;
|
||||
}
|
||||
/* This is the primary cpu how should I boot? */
|
||||
else if (do_normal_boot()) {
|
||||
goto normal_image;
|
||||
}
|
||||
else {
|
||||
goto fallback_image;
|
||||
}
|
||||
normal_image:
|
||||
// post_code(0x23);
|
||||
__asm__ volatile ("jmp __normal_image"
|
||||
: /* outputs */
|
||||
: "a" (bist) , "b" (cpu_init_detectedx)/* inputs */
|
||||
);
|
||||
// post_code(0x23);
|
||||
__asm__ volatile ("jmp __normal_image"
|
||||
: /* outputs */
|
||||
: "a" (bist), "b"(cpu_init_detectedx) /* inputs */
|
||||
);
|
||||
|
||||
fallback_image:
|
||||
// post_code(0x25);
|
||||
// post_code(0x25);
|
||||
;
|
||||
}
|
||||
#endif
|
||||
|
@ -182,71 +168,71 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
|||
{
|
||||
|
||||
#if USE_FALLBACK_IMAGE == 1
|
||||
failover_process(bist, cpu_init_detectedx);
|
||||
failover_process(bist, cpu_init_detectedx);
|
||||
#endif
|
||||
real_main(bist, cpu_init_detectedx);
|
||||
real_main(bist, cpu_init_detectedx);
|
||||
|
||||
}
|
||||
|
||||
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
{
|
||||
static const uint16_t spd_addr [] = {
|
||||
(0xa<<3)|0, (0xa<<3)|2, 0, 0,
|
||||
(0xa<<3)|1, (0xa<<3)|3, 0, 0,
|
||||
(0xa<<3)|0, (0xa<<3)|2, 0, 0,
|
||||
(0xa<<3)|1, (0xa<<3)|3, 0, 0,
|
||||
#if CONFIG_MAX_PHYSICAL_CPUS > 1
|
||||
(0xa<<3)|4, (0xa<<3)|6, 0, 0,
|
||||
(0xa<<3)|5, (0xa<<3)|7, 0, 0,
|
||||
(0xa<<3)|4, (0xa<<3)|6, 0, 0,
|
||||
(0xa<<3)|5, (0xa<<3)|7, 0, 0,
|
||||
#endif
|
||||
};
|
||||
|
||||
int needs_reset;
|
||||
unsigned bsp_apicid = 0;
|
||||
int needs_reset;
|
||||
unsigned bsp_apicid = 0;
|
||||
|
||||
struct mem_controller ctrl[8];
|
||||
unsigned nodes;
|
||||
struct mem_controller ctrl[8];
|
||||
unsigned nodes;
|
||||
|
||||
if (bist == 0) {
|
||||
bsp_apicid = init_cpus(cpu_init_detectedx);
|
||||
}
|
||||
if (bist == 0) {
|
||||
bsp_apicid = init_cpus(cpu_init_detectedx);
|
||||
}
|
||||
|
||||
// post_code(0x32);
|
||||
|
||||
|
||||
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
|
||||
uart_init();
|
||||
console_init();
|
||||
|
||||
uart_init();
|
||||
console_init();
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
report_bist_failure(bist);
|
||||
|
||||
setup_s2891_resource_map();
|
||||
setup_s2891_resource_map();
|
||||
#if 0
|
||||
dump_pci_device(PCI_DEV(0, 0x18, 0));
|
||||
dump_pci_device(PCI_DEV(0, 0x18, 0));
|
||||
dump_pci_device(PCI_DEV(0, 0x19, 0));
|
||||
#endif
|
||||
|
||||
needs_reset = setup_coherent_ht_domain();
|
||||
|
||||
wait_all_core0_started();
|
||||
wait_all_core0_started();
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
// It is said that we should start core1 after all core0 launched
|
||||
start_other_cores();
|
||||
wait_all_other_cores_started(bsp_apicid);
|
||||
// It is said that we should start core1 after all core0 launched
|
||||
start_other_cores();
|
||||
wait_all_other_cores_started(bsp_apicid);
|
||||
#endif
|
||||
|
||||
needs_reset |= ht_setup_chains_x();
|
||||
needs_reset |= ht_setup_chains_x();
|
||||
|
||||
needs_reset |= ck804_early_setup_x();
|
||||
needs_reset |= ck804_early_setup_x();
|
||||
|
||||
if (needs_reset) {
|
||||
print_info("ht reset -\r\n");
|
||||
// soft_reset();
|
||||
}
|
||||
if (needs_reset) {
|
||||
print_info("ht reset -\r\n");
|
||||
// soft_reset();
|
||||
}
|
||||
|
||||
allow_all_aps_stop(bsp_apicid);
|
||||
allow_all_aps_stop(bsp_apicid);
|
||||
|
||||
nodes = get_nodes();
|
||||
//It's the time to set ctrl now;
|
||||
fill_mem_ctrl(nodes, ctrl, spd_addr);
|
||||
nodes = get_nodes();
|
||||
//It's the time to set ctrl now;
|
||||
fill_mem_ctrl(nodes, ctrl, spd_addr);
|
||||
|
||||
enable_smbus();
|
||||
#if 0
|
||||
|
@ -260,7 +246,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
|||
sdram_initialize(nodes, ctrl);
|
||||
|
||||
#if 0
|
||||
print_pci_devices();
|
||||
print_pci_devices();
|
||||
#endif
|
||||
|
||||
#if 0
|
||||
|
|
|
@ -91,7 +91,6 @@ static unsigned long main(unsigned long bist)
|
|||
: "a" (bist) /* inputs */
|
||||
: /* clobbers */
|
||||
);
|
||||
|
||||
fallback_image:
|
||||
return bist;
|
||||
}
|
||||
|
|
|
@ -25,9 +25,9 @@
|
|||
unsigned apicid_ck804;
|
||||
unsigned apicid_8131_1;
|
||||
unsigned apicid_8131_2;
|
||||
|
||||
|
||||
unsigned pci1234x[] =
|
||||
|
||||
unsigned pci1234x[] =
|
||||
{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not
|
||||
//You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
|
||||
0x0000000,
|
||||
|
@ -39,7 +39,7 @@ unsigned pci1234x[] =
|
|||
// 0x0000ff0,
|
||||
// 0x0000ff0
|
||||
};
|
||||
unsigned hcdnx[] =
|
||||
unsigned hcdnx[] =
|
||||
{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
|
||||
0x20202020,
|
||||
0x20202020,
|
||||
|
@ -62,9 +62,9 @@ void get_bus_conf(void)
|
|||
{
|
||||
|
||||
unsigned apicid_base;
|
||||
unsigned sbdn;
|
||||
|
||||
device_t dev;
|
||||
unsigned sbdn;
|
||||
int i;
|
||||
|
||||
if(get_bus_conf_done==1) return; //do it only once
|
||||
|
@ -78,7 +78,7 @@ void get_bus_conf(void)
|
|||
}
|
||||
|
||||
get_sblk_pci1234();
|
||||
|
||||
|
||||
sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
|
||||
sbdn = sysconf.sbdn;
|
||||
|
||||
|
@ -91,51 +91,15 @@ void get_bus_conf(void)
|
|||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x09,0));
|
||||
if (dev) {
|
||||
bus_ck804_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
#if 0
|
||||
bus_ck804_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_2++;
|
||||
#else
|
||||
bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_4++;
|
||||
#endif
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x09);
|
||||
|
||||
bus_ck804_1 = 2;
|
||||
#if 0
|
||||
bus_ck804_2 = 3;
|
||||
#else
|
||||
bus_ck804_4 = 3;
|
||||
#endif
|
||||
|
||||
}
|
||||
#if 0
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0b,0));
|
||||
if (dev) {
|
||||
bus_ck804_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_ck804_3 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_3++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x0b);
|
||||
|
||||
bus_ck804_3 = bus_ck804_2+1;
|
||||
}
|
||||
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0c,0));
|
||||
if (dev) {
|
||||
bus_ck804_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_4++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x0c);
|
||||
|
||||
bus_ck804_4 = bus_ck804_3+1;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0d,0));
|
||||
if (dev) {
|
||||
|
@ -160,7 +124,6 @@ void get_bus_conf(void)
|
|||
}
|
||||
|
||||
bus_8131_0 = (sysconf.pci1234[1] >> 16) & 0xff;
|
||||
|
||||
/* 8131-1 */
|
||||
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,0));
|
||||
if (dev) {
|
||||
|
@ -192,13 +155,13 @@ void get_bus_conf(void)
|
|||
bus_coproc_0 = (sysconf.pci1234[2] >> 16) & 0xff;
|
||||
coprocdn = (sysconf.hcdn[2] & 0xff);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*I/O APICs: APIC ID Version State Address*/
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
apicid_base = get_apicid_base(3);
|
||||
#else
|
||||
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
|
||||
#else
|
||||
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
|
||||
#endif
|
||||
apicid_ck804 = apicid_base+0;
|
||||
apicid_8131_1 = apicid_base+1;
|
||||
|
|
|
@ -1,4 +1,4 @@
|
|||
/* This file was generated by getpir.c, do not modify!
|
||||
/* This file was generated by getpir.c, do not modify!
|
||||
(but if you do, please run checkpir on it to verify)
|
||||
Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
|
||||
|
||||
|
@ -12,22 +12,22 @@
|
|||
|
||||
#include <cpu/amd/amdk8_sysconf.h>
|
||||
|
||||
static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0,
|
||||
static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0,
|
||||
uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
|
||||
uint8_t slot, uint8_t rfu)
|
||||
{
|
||||
pirq_info->bus = bus;
|
||||
pirq_info->devfn = devfn;
|
||||
pirq_info->irq[0].link = link0;
|
||||
pirq_info->irq[0].bitmap = bitmap0;
|
||||
pirq_info->irq[1].link = link1;
|
||||
pirq_info->irq[1].bitmap = bitmap1;
|
||||
pirq_info->irq[2].link = link2;
|
||||
pirq_info->irq[2].bitmap = bitmap2;
|
||||
pirq_info->irq[3].link = link3;
|
||||
pirq_info->irq[3].bitmap = bitmap3;
|
||||
pirq_info->slot = slot;
|
||||
pirq_info->rfu = rfu;
|
||||
pirq_info->bus = bus;
|
||||
pirq_info->devfn = devfn;
|
||||
pirq_info->irq[0].link = link0;
|
||||
pirq_info->irq[0].bitmap = bitmap0;
|
||||
pirq_info->irq[1].link = link1;
|
||||
pirq_info->irq[1].bitmap = bitmap1;
|
||||
pirq_info->irq[2].link = link2;
|
||||
pirq_info->irq[2].bitmap = bitmap2;
|
||||
pirq_info->irq[3].link = link3;
|
||||
pirq_info->irq[3].bitmap = bitmap3;
|
||||
pirq_info->slot = slot;
|
||||
pirq_info->rfu = rfu;
|
||||
}
|
||||
|
||||
extern unsigned char bus_isa;
|
||||
|
@ -37,13 +37,13 @@ extern unsigned char bus_ck804_2; //3
|
|||
extern unsigned char bus_ck804_3; //4
|
||||
extern unsigned char bus_ck804_4; //5
|
||||
extern unsigned char bus_ck804_5; //6
|
||||
extern unsigned char bus_8131_0;//7
|
||||
extern unsigned char bus_8131_1;//8
|
||||
extern unsigned char bus_8131_2;//9
|
||||
extern unsigned char bus_8131_0; //7
|
||||
extern unsigned char bus_8131_1; //8
|
||||
extern unsigned char bus_8131_2; //9
|
||||
extern unsigned char bus_coproc_0;
|
||||
|
||||
extern unsigned sbdn3;
|
||||
extern unsigned coprocdn;
|
||||
extern unsigned coprocdn;
|
||||
|
||||
extern void get_bus_conf(void);
|
||||
|
||||
|
@ -54,32 +54,32 @@ unsigned long write_pirq_routing_table(unsigned long addr)
|
|||
struct irq_info *pirq_info;
|
||||
unsigned slot_num;
|
||||
uint8_t *v;
|
||||
|
||||
uint8_t sum=0;
|
||||
int i;
|
||||
unsigned sbdn;
|
||||
|
||||
get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
|
||||
uint8_t sum=0;
|
||||
int i;
|
||||
|
||||
get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
|
||||
sbdn = sysconf.sbdn;
|
||||
|
||||
/* Align the table to be 16 byte aligned. */
|
||||
addr += 15;
|
||||
addr &= ~15;
|
||||
/* Align the table to be 16 byte aligned. */
|
||||
addr += 15;
|
||||
addr &= ~15;
|
||||
|
||||
/* This table must be betweeen 0xf0000 & 0x100000 */
|
||||
printk_info("Writing IRQ routing tables to 0x%x...", addr);
|
||||
/* This table must be betweeen 0xf0000 & 0x100000 */
|
||||
printk_info("Writing IRQ routing tables to 0x%x...", addr);
|
||||
|
||||
pirq = (void *)(addr);
|
||||
v = (uint8_t *)(addr);
|
||||
|
||||
|
||||
pirq->signature = PIRQ_SIGNATURE;
|
||||
pirq->version = PIRQ_VERSION;
|
||||
|
||||
|
||||
pirq->rtr_bus = bus_ck804_0;
|
||||
pirq->rtr_devfn = ((sbdn+9)<<3)|0;
|
||||
|
||||
pirq->exclusive_irqs = 0;
|
||||
|
||||
|
||||
pirq->rtr_vendor = 0x10de;
|
||||
pirq->rtr_device = 0x005c;
|
||||
|
||||
|
@ -93,74 +93,74 @@ unsigned long write_pirq_routing_table(unsigned long addr)
|
|||
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+9)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
//pcix bridge
|
||||
write_pirq_info(pirq_info, bus_8131_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
write_pirq_info(pirq_info, bus_8131_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
//co processor
|
||||
if(sysconf.pci1234[2] & 1) {
|
||||
write_pirq_info(pirq_info, bus_coproc_0, (coprocdn<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
if(sysconf.pci1234[2] & 1) {
|
||||
write_pirq_info(pirq_info, bus_coproc_0, (coprocdn<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
}
|
||||
|
||||
|
||||
#if 0
|
||||
//smbus
|
||||
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+1)<<3)|0, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
pirq_info++; slot_num++;
|
||||
|
||||
//usb
|
||||
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+2)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
pirq_info++; slot_num++;
|
||||
|
||||
//audio
|
||||
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+4)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
pirq_info++; slot_num++;
|
||||
//sata
|
||||
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+7)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
pirq_info++; slot_num++;
|
||||
//sata
|
||||
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+8)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+8)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
//nic
|
||||
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+0xa)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+0xa)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
|
||||
//Slot1 PCIE x16
|
||||
write_pirq_info(pirq_info, bus_ck804_5, (0<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 1, 0);
|
||||
pirq_info++; slot_num++;
|
||||
write_pirq_info(pirq_info, bus_ck804_5, (0<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 1, 0);
|
||||
pirq_info++; slot_num++;
|
||||
|
||||
//firewire
|
||||
write_pirq_info(pirq_info, bus_ck804_1, (0x5<<3)|0, 0x3, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
write_pirq_info(pirq_info, bus_ck804_1, (0x5<<3)|0, 0x3, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
|
||||
//Slot2 pci
|
||||
write_pirq_info(pirq_info, bus_ck804_1, (0x4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 2, 0);
|
||||
pirq_info++; slot_num++;
|
||||
//Slot3 PCIE x16
|
||||
write_pirq_info(pirq_info, bus_ck804b_5, (0<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 3, 0);
|
||||
pirq_info++; slot_num++;
|
||||
write_pirq_info(pirq_info, bus_ck804_1, (0x4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 2, 0);
|
||||
pirq_info++; slot_num++;
|
||||
//Slot3 PCIE x16
|
||||
write_pirq_info(pirq_info, bus_ck804b_5, (0<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 3, 0);
|
||||
pirq_info++; slot_num++;
|
||||
|
||||
//Slot4 PCIX
|
||||
write_pirq_info(pirq_info, bus_8131_2, (4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 4, 0);
|
||||
pirq_info++; slot_num++;
|
||||
write_pirq_info(pirq_info, bus_8131_2, (4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 4, 0);
|
||||
pirq_info++; slot_num++;
|
||||
|
||||
//Slot5 PCIX
|
||||
write_pirq_info(pirq_info, bus_8131_2, (9<<3)|0, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 5, 0);
|
||||
pirq_info++; slot_num++;
|
||||
write_pirq_info(pirq_info, bus_8131_2, (9<<3)|0, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 5, 0);
|
||||
pirq_info++; slot_num++;
|
||||
|
||||
//Slot6 PCIX
|
||||
write_pirq_info(pirq_info, bus_8131_1, (4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 6, 0);
|
||||
pirq_info++; slot_num++;
|
||||
write_pirq_info(pirq_info, bus_8131_1, (4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 6, 0);
|
||||
pirq_info++; slot_num++;
|
||||
#endif
|
||||
|
||||
pirq->size = 32 + 16 * slot_num;
|
||||
|
||||
for (i = 0; i < pirq->size; i++)
|
||||
sum += v[i];
|
||||
pirq->size = 32 + 16 * slot_num;
|
||||
|
||||
for (i = 0; i < pirq->size; i++)
|
||||
sum += v[i];
|
||||
|
||||
sum = pirq->checksum - sum;
|
||||
|
||||
if (sum != pirq->checksum) {
|
||||
pirq->checksum = sum;
|
||||
}
|
||||
if (sum != pirq->checksum) {
|
||||
pirq->checksum = sum;
|
||||
}
|
||||
|
||||
printk_info("done.\n");
|
||||
|
||||
|
|
|
@ -13,9 +13,9 @@ extern unsigned char bus_ck804_2; //3
|
|||
extern unsigned char bus_ck804_3; //4
|
||||
extern unsigned char bus_ck804_4; //5
|
||||
extern unsigned char bus_ck804_5; //6
|
||||
extern unsigned char bus_8131_0;//7
|
||||
extern unsigned char bus_8131_1;//8
|
||||
extern unsigned char bus_8131_2;//9
|
||||
extern unsigned char bus_8131_0; //7
|
||||
extern unsigned char bus_8131_1; //8
|
||||
extern unsigned char bus_8131_2; //9
|
||||
extern unsigned apicid_ck804;
|
||||
extern unsigned apicid_8131_1;
|
||||
extern unsigned apicid_8131_2;
|
||||
|
@ -26,52 +26,52 @@ extern void get_bus_conf(void);
|
|||
|
||||
void *smp_write_config_table(void *v)
|
||||
{
|
||||
static const char sig[4] = "PCMP";
|
||||
static const char oem[8] = "TYAN ";
|
||||
static const char productid[12] = "S2891 ";
|
||||
struct mp_config_table *mc;
|
||||
static const char sig[4] = "PCMP";
|
||||
static const char oem[8] = "TYAN ";
|
||||
static const char productid[12] = "S2891 ";
|
||||
struct mp_config_table *mc;
|
||||
unsigned sbdn;
|
||||
|
||||
unsigned char bus_num;
|
||||
unsigned char bus_num;
|
||||
int i;
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
memset(mc, 0, sizeof(*mc));
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
memset(mc, 0, sizeof(*mc));
|
||||
|
||||
memcpy(mc->mpc_signature, sig, sizeof(sig));
|
||||
mc->mpc_length = sizeof(*mc); /* initially just the header */
|
||||
mc->mpc_spec = 0x04;
|
||||
mc->mpc_checksum = 0; /* not yet computed */
|
||||
memcpy(mc->mpc_oem, oem, sizeof(oem));
|
||||
memcpy(mc->mpc_productid, productid, sizeof(productid));
|
||||
mc->mpc_oemptr = 0;
|
||||
mc->mpc_oemsize = 0;
|
||||
mc->mpc_entry_count = 0; /* No entries yet... */
|
||||
mc->mpc_lapic = LAPIC_ADDR;
|
||||
mc->mpe_length = 0;
|
||||
mc->mpe_checksum = 0;
|
||||
mc->reserved = 0;
|
||||
memcpy(mc->mpc_signature, sig, sizeof(sig));
|
||||
mc->mpc_length = sizeof(*mc); /* initially just the header */
|
||||
mc->mpc_spec = 0x04;
|
||||
mc->mpc_checksum = 0; /* not yet computed */
|
||||
memcpy(mc->mpc_oem, oem, sizeof(oem));
|
||||
memcpy(mc->mpc_productid, productid, sizeof(productid));
|
||||
mc->mpc_oemptr = 0;
|
||||
mc->mpc_oemsize = 0;
|
||||
mc->mpc_entry_count = 0; /* No entries yet... */
|
||||
mc->mpc_lapic = LAPIC_ADDR;
|
||||
mc->mpe_length = 0;
|
||||
mc->mpe_checksum = 0;
|
||||
mc->reserved = 0;
|
||||
|
||||
smp_write_processors(mc);
|
||||
smp_write_processors(mc);
|
||||
|
||||
get_bus_conf();
|
||||
sbdn = sysconf.sbdn;
|
||||
|
||||
/*Bus: Bus ID Type*/
|
||||
/* define bus and isa numbers */
|
||||
for(bus_num = 0; bus_num < bus_isa; bus_num++) {
|
||||
smp_write_bus(mc, bus_num, "PCI ");
|
||||
}
|
||||
smp_write_bus(mc, bus_isa, "ISA ");
|
||||
for(bus_num = 0; bus_num < bus_isa; bus_num++) {
|
||||
smp_write_bus(mc, bus_num, "PCI ");
|
||||
}
|
||||
smp_write_bus(mc, bus_isa, "ISA ");
|
||||
|
||||
/*I/O APICs: APIC ID Version State Address*/
|
||||
{
|
||||
device_t dev;
|
||||
{
|
||||
device_t dev;
|
||||
struct resource *res;
|
||||
uint32_t dword;
|
||||
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x1,0));
|
||||
if (dev) {
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x1,0));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_1);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, apicid_ck804, 0x11, res->base);
|
||||
|
@ -80,33 +80,33 @@ void *smp_write_config_table(void *v)
|
|||
/* Initialize interrupt mapping*/
|
||||
|
||||
dword = 0x0120d218;
|
||||
pci_write_config32(dev, 0x7c, dword);
|
||||
pci_write_config32(dev, 0x7c, dword);
|
||||
|
||||
dword = 0x12008a00;
|
||||
pci_write_config32(dev, 0x80, dword);
|
||||
dword = 0x12008a00;
|
||||
pci_write_config32(dev, 0x80, dword);
|
||||
|
||||
dword = 0x0000007d;
|
||||
pci_write_config32(dev, 0x84, dword);
|
||||
dword = 0x0000007d;
|
||||
pci_write_config32(dev, 0x84, dword);
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1));
|
||||
if (dev) {
|
||||
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
|
||||
}
|
||||
}
|
||||
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
|
||||
if (dev) {
|
||||
}
|
||||
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#
|
||||
*/ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_ck804, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_ck804, 0x1);
|
||||
|
@ -122,53 +122,53 @@ void *smp_write_config_table(void *v)
|
|||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_ck804, 0xf);
|
||||
|
||||
// Onboard ck804 smbus
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+1)<<2)|1, apicid_ck804, 0xa);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+1)<<2)|1, apicid_ck804, 0xa);
|
||||
// 10
|
||||
|
||||
// Onboard ck804 USB 1.1
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|0, apicid_ck804, 0x15); // 21
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|0, apicid_ck804, 0x15); // 21
|
||||
|
||||
// Onboard ck804 USB 2
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|1, apicid_ck804, 0x14); // 20
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|1, apicid_ck804, 0x14); // 20
|
||||
|
||||
// Onboard ck804 SATA 0
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +7)<<2)|0, apicid_ck804, 0x17); // 23
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +7)<<2)|0, apicid_ck804, 0x17); // 23
|
||||
|
||||
// Onboard ck804 SATA 1
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +8)<<2)|0, apicid_ck804, 0x16); // 22
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +8)<<2)|0, apicid_ck804, 0x16); // 22
|
||||
|
||||
//Slot PCIE x16
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4);
|
||||
}
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4);
|
||||
}
|
||||
|
||||
//Slot PCIE x4
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|i, apicid_ck804, 0x10 + (1+i+4-sbdn%4)%4);
|
||||
}
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|i, apicid_ck804, 0x10 + (1+i+4-sbdn%4)%4);
|
||||
}
|
||||
|
||||
//Onboard ati
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (7<<2)|0, apicid_ck804, 0x13); // 19
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (7<<2)|0, apicid_ck804, 0x13); // 19
|
||||
|
||||
//Channel B of 8131
|
||||
|
||||
|
||||
//Onboard Broadcom NIC
|
||||
for(i=0;i<2;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|i, apicid_8131_2, (0+i)%4); //28
|
||||
}
|
||||
for(i=0;i<2;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|i, apicid_8131_2, (0+i)%4); //28
|
||||
}
|
||||
|
||||
//Channel A of 8131
|
||||
|
||||
//Slot 4 PCIX 133/100/66
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|i, apicid_8131_1, (0+i)%4); //24
|
||||
}
|
||||
//Slot 4 PCIX 133/100/66
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|i, apicid_8131_1, (0+i)%4); //24
|
||||
}
|
||||
|
||||
//Slot 3 PCIX 133/100/66 SoDIMM PCI
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0xa<<2)|i, apicid_8131_1, (2+i)%4); //26
|
||||
}
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0xa<<2)|i, apicid_8131_1, (2+i)%4); //26
|
||||
}
|
||||
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
|
||||
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
|
||||
|
|
|
@ -6,7 +6,6 @@
|
|||
static void setup_s2891_resource_map(void)
|
||||
{
|
||||
static const unsigned int register_values[] = {
|
||||
#if 1
|
||||
/* Careful set limit registers before base registers which contain the enables */
|
||||
/* DRAM Limit i Registers
|
||||
* F1:0x44 i = 0
|
||||
|
@ -80,8 +79,6 @@ static void setup_s2891_resource_map(void)
|
|||
PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
|
||||
#endif
|
||||
#if 1
|
||||
|
||||
/* Memory-Mapped I/O Limit i Registers
|
||||
* F1:0x84 i = 0
|
||||
|
@ -158,8 +155,6 @@ static void setup_s2891_resource_map(void)
|
|||
PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
|
||||
// PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
|
||||
#endif
|
||||
#if 1
|
||||
|
||||
/* PCI I/O Limit i Registers
|
||||
* F1:0xC4 i = 0
|
||||
|
@ -220,7 +215,7 @@ static void setup_s2891_resource_map(void)
|
|||
PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
|
||||
#endif
|
||||
|
||||
/* Config Base and Limit i Registers
|
||||
* F1:0xE0 i = 0
|
||||
* F1:0xE4 i = 1
|
||||
|
@ -257,12 +252,10 @@ static void setup_s2891_resource_map(void)
|
|||
* [31:24] Bus Number Limit i
|
||||
* This field defines the highest bus number in configuration region i
|
||||
*/
|
||||
#if 1
|
||||
// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000003, /* link 0 of cpu 0 --> Nvidia CK 804 Pro */
|
||||
// PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203, /* link 2 of cpu 0 --> AMD8131 */
|
||||
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
|
||||
#endif
|
||||
|
||||
};
|
||||
|
||||
|
|
|
@ -14,9 +14,9 @@ end
|
|||
## Compute the start location and size size of
|
||||
## The coreboot bootloader.
|
||||
##
|
||||
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
|
||||
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
|
||||
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
|
||||
default CONFIG_ROM_PAYLOAD = 1
|
||||
default CONFIG_ROM_PAYLOAD = 1
|
||||
|
||||
##
|
||||
## Compute where this copy of coreboot will start in the boot rom
|
||||
|
@ -33,7 +33,7 @@ default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
|
|||
default XIP_ROM_SIZE=65536
|
||||
default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
|
||||
|
||||
arch i386 end
|
||||
arch i386 end
|
||||
|
||||
|
||||
##
|
||||
|
@ -43,10 +43,10 @@ arch i386 end
|
|||
driver mainboard.o
|
||||
|
||||
#dir /drivers/ati/ragexl
|
||||
|
||||
#needed by irq_tables and mptable and acpi_tables
|
||||
object get_bus_conf.o
|
||||
|
||||
|
||||
if HAVE_MP_TABLE object mptable.o end
|
||||
if HAVE_PIRQ_TABLE object irq_tables.o end
|
||||
#object reset.o
|
||||
|
@ -54,46 +54,42 @@ if HAVE_PIRQ_TABLE object irq_tables.o end
|
|||
if USE_DCACHE_RAM
|
||||
|
||||
if CONFIG_USE_INIT
|
||||
|
||||
makerule ./auto.o
|
||||
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
|
||||
action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
|
||||
makerule ./auto.o
|
||||
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
|
||||
action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
|
||||
end
|
||||
else
|
||||
makerule ./auto.inc
|
||||
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
|
||||
action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
|
||||
action "perl -e 's/.rodata/.rom.data/g' -pi $@"
|
||||
action "perl -e 's/.text/.section .rom.text/g' -pi $@"
|
||||
end
|
||||
end
|
||||
|
||||
else
|
||||
##
|
||||
## Romcc output
|
||||
##
|
||||
makerule ./failover.E
|
||||
depends "$(MAINBOARD)/failover.c ../romcc"
|
||||
action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
|
||||
end
|
||||
|
||||
makerule ./auto.inc
|
||||
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
|
||||
action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
|
||||
action "perl -e 's/.rodata/.rom.data/g' -pi $@"
|
||||
action "perl -e 's/.text/.section .rom.text/g' -pi $@"
|
||||
end
|
||||
makerule ./failover.inc
|
||||
depends "$(MAINBOARD)/failover.c ../romcc"
|
||||
action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
|
||||
end
|
||||
|
||||
end
|
||||
else
|
||||
|
||||
##
|
||||
## Romcc output
|
||||
##
|
||||
makerule ./failover.E
|
||||
depends "$(MAINBOARD)/failover.c ../romcc"
|
||||
action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
|
||||
end
|
||||
|
||||
makerule ./failover.inc
|
||||
depends "$(MAINBOARD)/failover.c ../romcc"
|
||||
action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
|
||||
end
|
||||
|
||||
makerule ./auto.E
|
||||
depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
action "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
makerule ./auto.inc
|
||||
depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
action "../romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
makerule ./auto.E
|
||||
depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
action "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
|
||||
makerule ./auto.inc
|
||||
depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
action "../romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
|
@ -101,8 +97,8 @@ end
|
|||
## Build our 16 bit and 32 bit coreboot entry code
|
||||
##
|
||||
if USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
end
|
||||
|
||||
mainboardinit cpu/x86/32bit/entry32.inc
|
||||
|
@ -113,25 +109,25 @@ if USE_DCACHE_RAM
|
|||
end
|
||||
|
||||
if CONFIG_USE_INIT
|
||||
ldscript /cpu/amd/car/cache_as_ram.lds
|
||||
ldscript /cpu/amd/car/cache_as_ram.lds
|
||||
end
|
||||
end
|
||||
|
||||
##
|
||||
## Build our reset vector (This is where coreboot is entered)
|
||||
##
|
||||
if USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
if USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
else
|
||||
mainboardinit cpu/x86/32bit/reset32.inc
|
||||
ldscript /cpu/x86/32bit/reset32.lds
|
||||
mainboardinit cpu/x86/32bit/reset32.inc
|
||||
ldscript /cpu/x86/32bit/reset32.lds
|
||||
end
|
||||
|
||||
if USE_DCACHE_RAM
|
||||
else
|
||||
### Should this be in the northbridge code?
|
||||
mainboardinit arch/i386/lib/cpu_reset.inc
|
||||
### Should this be in the northbridge code?
|
||||
mainboardinit arch/i386/lib/cpu_reset.inc
|
||||
end
|
||||
|
||||
##
|
||||
|
@ -149,24 +145,24 @@ if USE_FALLBACK_IMAGE
|
|||
end
|
||||
|
||||
if USE_DCACHE_RAM
|
||||
##
|
||||
## Setup Cache-As-Ram
|
||||
##
|
||||
mainboardinit cpu/amd/car/cache_as_ram.inc
|
||||
##
|
||||
## Setup Cache-As-Ram
|
||||
##
|
||||
mainboardinit cpu/amd/car/cache_as_ram.inc
|
||||
end
|
||||
|
||||
###
|
||||
### This is the early phase of coreboot startup
|
||||
### This is the early phase of coreboot startup
|
||||
### Things are delicate and we test to see if we should
|
||||
### failover to another image.
|
||||
###
|
||||
if USE_FALLBACK_IMAGE
|
||||
if USE_DCACHE_RAM
|
||||
ldscript /arch/i386/lib/failover.lds
|
||||
else
|
||||
ldscript /arch/i386/lib/failover.lds
|
||||
mainboardinit ./failover.inc
|
||||
end
|
||||
if USE_DCACHE_RAM
|
||||
ldscript /arch/i386/lib/failover.lds
|
||||
else
|
||||
ldscript /arch/i386/lib/failover.lds
|
||||
mainboardinit ./failover.inc
|
||||
end
|
||||
end
|
||||
|
||||
###
|
||||
|
@ -178,187 +174,185 @@ end
|
|||
##
|
||||
if USE_DCACHE_RAM
|
||||
|
||||
if CONFIG_USE_INIT
|
||||
initobject auto.o
|
||||
else
|
||||
mainboardinit ./auto.inc
|
||||
end
|
||||
if CONFIG_USE_INIT
|
||||
initobject auto.o
|
||||
else
|
||||
mainboardinit ./auto.inc
|
||||
end
|
||||
|
||||
else
|
||||
# ROMCC
|
||||
mainboardinit cpu/x86/fpu/enable_fpu.inc
|
||||
mainboardinit cpu/x86/mmx/enable_mmx.inc
|
||||
mainboardinit cpu/x86/sse/enable_sse.inc
|
||||
mainboardinit ./auto.inc
|
||||
mainboardinit cpu/x86/sse/disable_sse.inc
|
||||
mainboardinit cpu/x86/mmx/disable_mmx.inc
|
||||
# ROMCC
|
||||
mainboardinit cpu/x86/fpu/enable_fpu.inc
|
||||
mainboardinit cpu/x86/mmx/enable_mmx.inc
|
||||
mainboardinit cpu/x86/sse/enable_sse.inc
|
||||
mainboardinit ./auto.inc
|
||||
mainboardinit cpu/x86/sse/disable_sse.inc
|
||||
mainboardinit cpu/x86/mmx/disable_mmx.inc
|
||||
|
||||
end
|
||||
|
||||
##
|
||||
## Include the secondary Configuration files
|
||||
## Include the secondary Configuration files
|
||||
##
|
||||
if CONFIG_CHIP_NAME
|
||||
config chip.h
|
||||
config chip.h
|
||||
end
|
||||
|
||||
|
||||
# sample config for tyan/s2892
|
||||
chip northbridge/amd/amdk8/root_complex
|
||||
device apic_cluster 0 on
|
||||
chip cpu/amd/socket_940
|
||||
device apic 0 on end
|
||||
end
|
||||
end
|
||||
|
||||
device apic_cluster 0 on
|
||||
chip cpu/amd/socket_940
|
||||
device apic 0 on end
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on
|
||||
chip northbridge/amd/amdk8 #mc0
|
||||
device pci 18.0 on # northbridge
|
||||
# devices on link 0, link 0 == LDT 0
|
||||
chip southbridge/nvidia/ck804
|
||||
device pci 18.0 on # northbridge
|
||||
# devices on link 0, link 0 == LDT 0
|
||||
chip southbridge/nvidia/ck804
|
||||
device pci 0.0 on end # HT
|
||||
device pci 1.0 on # LPC
|
||||
chip superio/winbond/w83627hf
|
||||
device pnp 2e.0 on # Floppy
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 2e.1 off # Parallel Port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 2e.2 on # Com1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.3 off # Com2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.5 on # Keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
irq 0x72 = 12
|
||||
end
|
||||
device pnp 2e.6 off # CIR
|
||||
io 0x60 = 0x100
|
||||
end
|
||||
device pnp 2e.7 off # GAME_MIDI_GIPO1
|
||||
io 0x60 = 0x220
|
||||
io 0x62 = 0x300
|
||||
irq 0x70 = 9
|
||||
end
|
||||
device pnp 2e.8 off end # GPIO2
|
||||
device pnp 2e.9 off end # GPIO3
|
||||
device pnp 2e.a off end # ACPI
|
||||
device pnp 2e.b on # HW Monitor
|
||||
io 0x60 = 0x290
|
||||
irq 0x70 = 5
|
||||
end
|
||||
end
|
||||
device pci 1.0 on # LPC
|
||||
chip superio/winbond/w83627hf
|
||||
device pnp 2e.0 on # Floppy
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 2e.1 off # Parallel Port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 2e.2 on # Com1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.3 off # Com2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.5 on # Keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
irq 0x72 = 12
|
||||
end
|
||||
device pnp 2e.6 off # CIR
|
||||
io 0x60 = 0x100
|
||||
end
|
||||
device pnp 2e.7 off # GAME_MIDI_GIPO1
|
||||
io 0x60 = 0x220
|
||||
io 0x62 = 0x300
|
||||
irq 0x70 = 9
|
||||
end
|
||||
device pnp 2e.8 off end # GPIO2
|
||||
device pnp 2e.9 off end # GPIO3
|
||||
device pnp 2e.a off end # ACPI
|
||||
device pnp 2e.b on # HW Monitor
|
||||
io 0x60 = 0x290
|
||||
irq 0x70 = 5
|
||||
end
|
||||
end
|
||||
end
|
||||
device pci 1.1 on # SM 0
|
||||
chip drivers/generic/generic #dimm 0-0-0
|
||||
device i2c 50 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-0-1
|
||||
device i2c 51 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-1-0
|
||||
device i2c 52 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-1-1
|
||||
device i2c 53 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-0-0
|
||||
device i2c 54 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-0-1
|
||||
device i2c 55 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-1-0
|
||||
device i2c 56 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-1-1
|
||||
device i2c 57 on end
|
||||
end
|
||||
end # SM
|
||||
device pci 1.1 on # SM 1
|
||||
device pci 1.1 on # SM 0
|
||||
chip drivers/generic/generic #dimm 0-0-0
|
||||
device i2c 50 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-0-1
|
||||
device i2c 51 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-1-0
|
||||
device i2c 52 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-1-1
|
||||
device i2c 53 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-0-0
|
||||
device i2c 54 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-0-1
|
||||
device i2c 55 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-1-0
|
||||
device i2c 56 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-1-1
|
||||
device i2c 57 on end
|
||||
end
|
||||
end # SM
|
||||
device pci 1.1 on # SM 1
|
||||
chip drivers/i2c/adm1027 # ADT7463A CPU0 temp, SYS FAN 2/3/4
|
||||
device i2c 2d on end
|
||||
end
|
||||
chip drivers/i2c/adm1027 # ADT7463A CPU1 temp, CPU0/1 FAN , SYS FAN 1/5
|
||||
device i2c 2e on end
|
||||
end
|
||||
chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 6/7, SB FAN
|
||||
device i2c 2a on end
|
||||
end
|
||||
chip drivers/generic/generic # Winbond HWM 0x92
|
||||
device i2c 49 on end
|
||||
end
|
||||
chip drivers/generic/generic # Winbond HWM 0x94
|
||||
device i2c 4a on end
|
||||
end
|
||||
device i2c 2d on end
|
||||
end
|
||||
chip drivers/i2c/adm1027 # ADT7463A CPU1 temp, CPU0/1 FAN , SYS FAN 1/5
|
||||
device i2c 2e on end
|
||||
end
|
||||
chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 6/7, SB FAN
|
||||
device i2c 2a on end
|
||||
end
|
||||
chip drivers/generic/generic # Winbond HWM 0x92
|
||||
device i2c 49 on end
|
||||
end
|
||||
chip drivers/generic/generic # Winbond HWM 0x94
|
||||
device i2c 4a on end
|
||||
end
|
||||
end #SM
|
||||
device pci 2.0 on end # USB 1.1
|
||||
device pci 2.1 on end # USB 2
|
||||
device pci 4.0 off end # ACI
|
||||
device pci 4.1 off end # MCI
|
||||
device pci 6.0 on end # IDE
|
||||
device pci 7.0 on end # SATA 1
|
||||
device pci 8.0 on end # SATA 0
|
||||
device pci 9.0 on # PCI
|
||||
device pci 2.0 on end # USB 1.1
|
||||
device pci 2.1 on end # USB 2
|
||||
device pci 4.0 off end # ACI
|
||||
device pci 4.1 off end # MCI
|
||||
device pci 6.0 on end # IDE
|
||||
device pci 7.0 on end # SATA 1
|
||||
device pci 8.0 on end # SATA 0
|
||||
device pci 9.0 on # PCI
|
||||
# chip drivers/ati/ragexl
|
||||
chip drivers/pci/onboard
|
||||
device pci 6.0 on end
|
||||
register "rom_address" = "0xfff80000"
|
||||
end
|
||||
chip drivers/pci/onboard
|
||||
device pci 8.0 on end
|
||||
end
|
||||
chip drivers/pci/onboard
|
||||
device pci 8.0 on end
|
||||
end
|
||||
end
|
||||
device pci a.0 off end # NIC
|
||||
device pci b.0 off end # PCI E 3
|
||||
device pci c.0 off end # PCI E 2
|
||||
device pci d.0 on end # PCI E 1
|
||||
device pci e.0 on end # PCI E 0
|
||||
register "ide0_enable" = "1"
|
||||
register "ide1_enable" = "1"
|
||||
register "sata0_enable" = "1"
|
||||
register "sata1_enable" = "1"
|
||||
device pci a.0 off end # NIC
|
||||
device pci b.0 off end # PCI E 3
|
||||
device pci c.0 off end # PCI E 2
|
||||
device pci d.0 on end # PCI E 1
|
||||
device pci e.0 on end # PCI E 0
|
||||
register "ide0_enable" = "1"
|
||||
register "ide1_enable" = "1"
|
||||
register "sata0_enable" = "1"
|
||||
register "sata1_enable" = "1"
|
||||
end
|
||||
end # device pci 18.0
|
||||
end # device pci 18.0
|
||||
device pci 18.0 on end # Link 1
|
||||
device pci 18.0 on
|
||||
# devices on link 2, link 2 == LDT 2
|
||||
chip southbridge/amd/amd8131
|
||||
# the on/off keyword is mandatory
|
||||
device pci 0.0 on end
|
||||
device pci 0.1 on end
|
||||
device pci 1.0 on
|
||||
chip drivers/pci/onboard
|
||||
device pci 9.0 on end # broadcom 5704
|
||||
# devices on link 2, link 2 == LDT 2
|
||||
chip southbridge/amd/amd8131
|
||||
# the on/off keyword is mandatory
|
||||
device pci 0.0 on end
|
||||
device pci 0.1 on end
|
||||
device pci 1.0 on
|
||||
chip drivers/pci/onboard
|
||||
device pci 9.0 on end # broadcom 5704
|
||||
device pci 9.1 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
device pci 1.1 on end
|
||||
end
|
||||
device pci 1.1 on end
|
||||
end
|
||||
end # device pci 18.0
|
||||
device pci 18.1 on end
|
||||
device pci 18.2 on end
|
||||
device pci 18.3 on end
|
||||
end #mc0
|
||||
|
||||
|
||||
end # pci_domain
|
||||
|
||||
# chip drivers/generic/debug
|
||||
# device pnp 0.0 off end
|
||||
# device pnp 0.1 off end
|
||||
# device pnp 0.2 off end
|
||||
# device pnp 0.3 off end
|
||||
# device pnp 0.4 off end
|
||||
|
||||
# chip drivers/generic/debug
|
||||
# device pnp 0.0 off end
|
||||
# device pnp 0.1 off end
|
||||
# device pnp 0.2 off end
|
||||
# device pnp 0.3 off end
|
||||
# device pnp 0.4 off end
|
||||
# device pnp 0.5 on end
|
||||
# end
|
||||
# end
|
||||
end # root_complex
|
||||
|
|
|
@ -30,9 +30,9 @@ uses USE_OPTION_TABLE
|
|||
uses LB_CKS_RANGE_START
|
||||
uses LB_CKS_RANGE_END
|
||||
uses LB_CKS_LOC
|
||||
uses MAINBOARD
|
||||
uses MAINBOARD_PART_NUMBER
|
||||
uses MAINBOARD_VENDOR
|
||||
uses MAINBOARD
|
||||
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
|
||||
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
|
||||
uses COREBOOT_EXTRA_VERSION
|
||||
|
@ -76,7 +76,6 @@ default ROM_SIZE=524288
|
|||
#1M bytes
|
||||
#default ROM_SIZE=1048576
|
||||
|
||||
|
||||
##
|
||||
## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
|
||||
##
|
||||
|
@ -131,6 +130,9 @@ default CONFIG_MAX_CPUS=4
|
|||
default CONFIG_MAX_PHYSICAL_CPUS=2
|
||||
default CONFIG_LOGICAL_CPUS=1
|
||||
|
||||
#1G memory hole
|
||||
default HW_MEM_HOLE_SIZEK=0x100000
|
||||
|
||||
##HT Unit ID offset, default is 1, the typical one
|
||||
default HT_CHAIN_UNITID_BASE=0x0
|
||||
|
||||
|
@ -143,9 +145,6 @@ default SB_HT_CHAIN_ON_BUS0=2
|
|||
##only offset for SB chain?, default is yes(1)
|
||||
default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
|
||||
|
||||
#1G memory hole
|
||||
default HW_MEM_HOLE_SIZEK=0x100000
|
||||
|
||||
#BTEXT Console
|
||||
#default CONFIG_CONSOLE_BTEXT=1
|
||||
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
#define ASSEMBLY 1
|
||||
|
||||
|
||||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <arch/io.h>
|
||||
|
@ -33,20 +33,20 @@
|
|||
|
||||
static void hard_reset(void)
|
||||
{
|
||||
set_bios_reset();
|
||||
set_bios_reset();
|
||||
|
||||
/* full reset */
|
||||
/* full reset */
|
||||
outb(0x0a, 0x0cf9);
|
||||
outb(0x0e, 0x0cf9);
|
||||
outb(0x0e, 0x0cf9);
|
||||
}
|
||||
|
||||
static void soft_reset(void)
|
||||
{
|
||||
set_bios_reset();
|
||||
set_bios_reset();
|
||||
#if 1
|
||||
/* link reset */
|
||||
/* link reset */
|
||||
outb(0x02, 0x0cf9);
|
||||
outb(0x06, 0x0cf9);
|
||||
outb(0x06, 0x0cf9);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
@ -73,10 +73,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
|
|||
#include "northbridge/amd/amdk8/coherent_ht.c"
|
||||
#include "sdram/generic_sdram.c"
|
||||
|
||||
/* tyan does not want the default */
|
||||
#include "resourcemap.c"
|
||||
/* tyan does not want the default */
|
||||
#include "resourcemap.c"
|
||||
|
||||
#define FIRST_CPU 1
|
||||
#define FIRST_CPU 1
|
||||
#define SECOND_CPU 1
|
||||
#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
|
||||
|
||||
|
@ -84,14 +84,13 @@ static inline int spd_read_byte(unsigned device, unsigned address)
|
|||
#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
|
||||
//set GPIO to input mode
|
||||
#define CK804_MB_SETUP \
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
|
||||
|
||||
#include "southbridge/nvidia/ck804/ck804_early_setup.c"
|
||||
|
||||
|
||||
static void main(unsigned long bist)
|
||||
{
|
||||
static const struct mem_controller cpu[] = {
|
||||
|
@ -119,32 +118,31 @@ static void main(unsigned long bist)
|
|||
#endif
|
||||
};
|
||||
|
||||
int needs_reset;
|
||||
int needs_reset;
|
||||
|
||||
if (bist == 0) {
|
||||
k8_init_and_stop_secondaries();
|
||||
}
|
||||
if (bist == 0) {
|
||||
k8_init_and_stop_secondaries();
|
||||
}
|
||||
|
||||
|
||||
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
|
||||
uart_init();
|
||||
console_init();
|
||||
|
||||
uart_init();
|
||||
console_init();
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
// report_bist_failure(bist);
|
||||
|
||||
setup_s2892_resource_map();
|
||||
setup_s2892_resource_map();
|
||||
|
||||
needs_reset = setup_coherent_ht_domain();
|
||||
|
||||
|
||||
needs_reset |= ht_setup_chains_x();
|
||||
|
||||
needs_reset |= ck804_early_setup_x();
|
||||
|
||||
if (needs_reset) {
|
||||
print_info("ht reset -\r\n");
|
||||
soft_reset();
|
||||
}
|
||||
if (needs_reset) {
|
||||
print_info("ht reset -\r\n");
|
||||
soft_reset();
|
||||
}
|
||||
|
||||
enable_smbus();
|
||||
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
#define ASSEMBLY 1
|
||||
#define __ROMCC__
|
||||
|
||||
|
||||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <arch/io.h>
|
||||
|
@ -13,18 +13,8 @@
|
|||
#include "arch/i386/lib/console.c"
|
||||
#include "ram/ramtest.c"
|
||||
|
||||
#if 0
|
||||
static void post_code(uint8_t value) {
|
||||
#if 1
|
||||
int i;
|
||||
for(i=0;i<0x80000;i++) {
|
||||
outb(value, 0x80);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
#include <cpu/amd/model_fxx_rev.h>
|
||||
|
||||
#include "northbridge/amd/amdk8/incoherent_ht.c"
|
||||
#include "southbridge/nvidia/ck804/ck804_early_smbus.c"
|
||||
#include "northbridge/amd/amdk8/raminit.h"
|
||||
|
@ -72,7 +62,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
|
|||
#include "sdram/generic_sdram.c"
|
||||
|
||||
/* tyan does not want the default */
|
||||
#include "resourcemap.c"
|
||||
#include "resourcemap.c"
|
||||
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
#define SET_NB_CFG_54 1
|
||||
|
@ -83,10 +73,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
|
|||
#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
|
||||
//set GPIO to input mode
|
||||
#define CK804_MB_SETUP \
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
|
||||
|
||||
#include "southbridge/nvidia/ck804/ck804_early_setup.c"
|
||||
|
||||
|
@ -96,7 +86,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
|
|||
|
||||
#include "cpu/amd/model_fxx/init_cpus.c"
|
||||
|
||||
|
||||
#if USE_FALLBACK_IMAGE == 1
|
||||
|
||||
#include "southbridge/nvidia/ck804/ck804_enable_rom.c"
|
||||
|
@ -105,63 +94,64 @@ static inline int spd_read_byte(unsigned device, unsigned address)
|
|||
static void sio_setup(void)
|
||||
{
|
||||
|
||||
unsigned value;
|
||||
uint32_t dword;
|
||||
uint8_t byte;
|
||||
unsigned value;
|
||||
uint32_t dword;
|
||||
uint8_t byte;
|
||||
|
||||
byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
|
||||
byte |= 0x20;
|
||||
pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
|
||||
byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
|
||||
byte |= 0x20;
|
||||
pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
|
||||
|
||||
dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
|
||||
dword |= (1<<0);
|
||||
pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
|
||||
dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
|
||||
dword |= (1<<0);
|
||||
pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
|
||||
|
||||
}
|
||||
|
||||
void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
{
|
||||
unsigned last_boot_normal_x = last_boot_normal();
|
||||
unsigned last_boot_normal_x = last_boot_normal();
|
||||
|
||||
/* Is this a cpu only reset? or Is this a secondary cpu? */
|
||||
if ((cpu_init_detectedx) || (!boot_cpu())) {
|
||||
if (last_boot_normal_x) {
|
||||
goto normal_image;
|
||||
} else {
|
||||
goto fallback_image;
|
||||
}
|
||||
}
|
||||
/* Is this a cpu only reset? or Is this a secondary cpu? */
|
||||
if ((cpu_init_detectedx) || (!boot_cpu())) {
|
||||
if (last_boot_normal_x) {
|
||||
goto normal_image;
|
||||
} else {
|
||||
goto fallback_image;
|
||||
}
|
||||
}
|
||||
|
||||
/* Nothing special needs to be done to find bus 0 */
|
||||
/* Allow the HT devices to be found */
|
||||
/* Nothing special needs to be done to find bus 0 */
|
||||
/* Allow the HT devices to be found */
|
||||
|
||||
enumerate_ht_chain();
|
||||
enumerate_ht_chain();
|
||||
|
||||
sio_setup();
|
||||
sio_setup();
|
||||
|
||||
/* Setup the ck804 */
|
||||
ck804_enable_rom();
|
||||
/* Setup the ck804 */
|
||||
ck804_enable_rom();
|
||||
|
||||
/* Is this a deliberate reset by the bios */
|
||||
// post_code(0x22);
|
||||
if (bios_reset_detected() && last_boot_normal_x) {
|
||||
goto normal_image;
|
||||
}
|
||||
/* This is the primary cpu how should I boot? */
|
||||
else if (do_normal_boot()) {
|
||||
goto normal_image;
|
||||
}
|
||||
else {
|
||||
goto fallback_image;
|
||||
}
|
||||
/* Is this a deliberate reset by the bios */
|
||||
// post_code(0x22);
|
||||
if (bios_reset_detected() && last_boot_normal_x) {
|
||||
goto normal_image;
|
||||
}
|
||||
/* This is the primary cpu how should I boot? */
|
||||
else if (do_normal_boot()) {
|
||||
goto normal_image;
|
||||
}
|
||||
else {
|
||||
goto fallback_image;
|
||||
}
|
||||
normal_image:
|
||||
// post_code(0x23);
|
||||
__asm__ volatile ("jmp __normal_image"
|
||||
: /* outputs */
|
||||
: "a" (bist), "b"(cpu_init_detectedx) /* inputs */
|
||||
);
|
||||
|
||||
// post_code(0x23);
|
||||
__asm__ volatile ("jmp __normal_image"
|
||||
: /* outputs */
|
||||
: "a" (bist), "b"(cpu_init_detectedx) /* inputs */
|
||||
);
|
||||
|
||||
fallback_image:
|
||||
// post_code(0x25);
|
||||
// post_code(0x25);
|
||||
;
|
||||
}
|
||||
#endif
|
||||
|
@ -172,91 +162,90 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
|||
{
|
||||
|
||||
#if USE_FALLBACK_IMAGE == 1
|
||||
failover_process(bist, cpu_init_detectedx);
|
||||
failover_process(bist, cpu_init_detectedx);
|
||||
#endif
|
||||
real_main(bist, cpu_init_detectedx);
|
||||
real_main(bist, cpu_init_detectedx);
|
||||
|
||||
}
|
||||
|
||||
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
{
|
||||
|
||||
static const uint16_t spd_addr [] = {
|
||||
(0xa<<3)|0, (0xa<<3)|2, 0, 0,
|
||||
(0xa<<3)|1, (0xa<<3)|3, 0, 0,
|
||||
static const uint16_t spd_addr [] = {
|
||||
(0xa<<3)|0, (0xa<<3)|2, 0, 0,
|
||||
(0xa<<3)|1, (0xa<<3)|3, 0, 0,
|
||||
#if CONFIG_MAX_PHYSICAL_CPUS > 1
|
||||
(0xa<<3)|4, (0xa<<3)|6, 0, 0,
|
||||
(0xa<<3)|5, (0xa<<3)|7, 0, 0,
|
||||
(0xa<<3)|4, (0xa<<3)|6, 0, 0,
|
||||
(0xa<<3)|5, (0xa<<3)|7, 0, 0,
|
||||
#endif
|
||||
};
|
||||
};
|
||||
|
||||
int needs_reset;
|
||||
unsigned bsp_apicid = 0;
|
||||
int needs_reset;
|
||||
unsigned bsp_apicid = 0;
|
||||
|
||||
struct mem_controller ctrl[8];
|
||||
unsigned nodes;
|
||||
struct mem_controller ctrl[8];
|
||||
unsigned nodes;
|
||||
|
||||
if (bist == 0) {
|
||||
if (bist == 0) {
|
||||
init_cpus(cpu_init_detectedx);
|
||||
}
|
||||
}
|
||||
|
||||
// post_code(0x32);
|
||||
|
||||
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
|
||||
uart_init();
|
||||
console_init();
|
||||
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
|
||||
uart_init();
|
||||
console_init();
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
report_bist_failure(bist);
|
||||
/* Halt if there was a built in self test failure */
|
||||
report_bist_failure(bist);
|
||||
|
||||
setup_s2892_resource_map();
|
||||
setup_s2892_resource_map();
|
||||
#if 0
|
||||
dump_pci_device(PCI_DEV(0, 0x18, 0));
|
||||
dump_pci_device(PCI_DEV(0, 0x19, 0));
|
||||
dump_pci_device(PCI_DEV(0, 0x18, 0));
|
||||
dump_pci_device(PCI_DEV(0, 0x19, 0));
|
||||
#endif
|
||||
|
||||
needs_reset = setup_coherent_ht_domain();
|
||||
needs_reset = setup_coherent_ht_domain();
|
||||
|
||||
wait_all_core0_started();
|
||||
wait_all_core0_started();
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
// It is said that we should start core1 after all core0 launched
|
||||
start_other_cores();
|
||||
wait_all_other_cores_started(bsp_apicid);
|
||||
// It is said that we should start core1 after all core0 launched
|
||||
start_other_cores();
|
||||
wait_all_other_cores_started(bsp_apicid);
|
||||
#endif
|
||||
|
||||
needs_reset |= ht_setup_chains_x();
|
||||
needs_reset |= ht_setup_chains_x();
|
||||
|
||||
needs_reset |= ck804_early_setup_x();
|
||||
needs_reset |= ck804_early_setup_x();
|
||||
|
||||
if (needs_reset) {
|
||||
print_info("ht reset -\r\n");
|
||||
soft_reset();
|
||||
}
|
||||
if (needs_reset) {
|
||||
print_info("ht reset -\r\n");
|
||||
soft_reset();
|
||||
}
|
||||
|
||||
allow_all_aps_stop(bsp_apicid);
|
||||
allow_all_aps_stop(bsp_apicid);
|
||||
|
||||
nodes = get_nodes();
|
||||
//It's the time to set ctrl now;
|
||||
fill_mem_ctrl(nodes, ctrl, spd_addr);
|
||||
nodes = get_nodes();
|
||||
//It's the time to set ctrl now;
|
||||
fill_mem_ctrl(nodes, ctrl, spd_addr);
|
||||
|
||||
enable_smbus();
|
||||
enable_smbus();
|
||||
#if 0
|
||||
dump_spd_registers(&cpu[0]);
|
||||
dump_spd_registers(&cpu[0]);
|
||||
#endif
|
||||
#if 0
|
||||
dump_smbus_registers();
|
||||
dump_smbus_registers();
|
||||
#endif
|
||||
|
||||
memreset_setup();
|
||||
sdram_initialize(nodes, ctrl);
|
||||
memreset_setup();
|
||||
sdram_initialize(nodes, ctrl);
|
||||
|
||||
#if 0
|
||||
print_pci_devices();
|
||||
print_pci_devices();
|
||||
#endif
|
||||
|
||||
#if 0
|
||||
dump_pci_devices();
|
||||
dump_pci_devices();
|
||||
#endif
|
||||
|
||||
post_cache_as_ram();
|
||||
post_cache_as_ram();
|
||||
}
|
||||
|
|
|
@ -25,7 +25,7 @@
|
|||
unsigned apicid_8131_1;
|
||||
unsigned apicid_8131_2;
|
||||
|
||||
unsigned pci1234x[] =
|
||||
unsigned pci1234x[] =
|
||||
{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not
|
||||
//You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
|
||||
0x0000ff0,
|
||||
|
@ -37,7 +37,7 @@ unsigned pci1234x[] =
|
|||
// 0x0000ff0,
|
||||
// 0x0000ff0
|
||||
};
|
||||
unsigned hcdnx[] =
|
||||
unsigned hcdnx[] =
|
||||
{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
|
||||
0x20202020,
|
||||
0x20202020,
|
||||
|
@ -75,7 +75,7 @@ void get_bus_conf(void)
|
|||
}
|
||||
|
||||
get_sblk_pci1234();
|
||||
|
||||
|
||||
sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
|
||||
sbdn = sysconf.sbdn;
|
||||
|
||||
|
@ -88,51 +88,15 @@ void get_bus_conf(void)
|
|||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x09,0));
|
||||
if (dev) {
|
||||
bus_ck804_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
#if 0
|
||||
bus_ck804_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_2++;
|
||||
#else
|
||||
bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_4++;
|
||||
#endif
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x09);
|
||||
|
||||
bus_ck804_1 = 2;
|
||||
#if 0
|
||||
bus_ck804_2 = 3;
|
||||
#else
|
||||
bus_ck804_4 = 3;
|
||||
#endif
|
||||
|
||||
}
|
||||
#if 0
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0b,0));
|
||||
if (dev) {
|
||||
bus_ck804_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_ck804_3 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_3++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x0b);
|
||||
|
||||
bus_ck804_3 = bus_ck804_2+1;
|
||||
}
|
||||
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0c,0));
|
||||
if (dev) {
|
||||
bus_ck804_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_4++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x0c);
|
||||
|
||||
bus_ck804_4 = bus_ck804_3+1;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0d,0));
|
||||
if (dev) {
|
||||
|
@ -157,7 +121,6 @@ void get_bus_conf(void)
|
|||
}
|
||||
|
||||
bus_8131_0 = (sysconf.pci1234[1] >> 16) & 0xff;
|
||||
|
||||
/* 8131-1 */
|
||||
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,0));
|
||||
if (dev) {
|
||||
|
@ -190,8 +153,8 @@ void get_bus_conf(void)
|
|||
/*I/O APICs: APIC ID Version State Address*/
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
apicid_base = get_apicid_base(3);
|
||||
#else
|
||||
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
|
||||
#else
|
||||
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
|
||||
#endif
|
||||
apicid_ck804 = apicid_base+0;
|
||||
apicid_8131_1 = apicid_base+1;
|
||||
|
|
|
@ -1,4 +1,4 @@
|
|||
/* This file was generated by getpir.c, do not modify!
|
||||
/* This file was generated by getpir.c, do not modify!
|
||||
(but if you do, please run checkpir on it to verify)
|
||||
Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
|
||||
|
||||
|
@ -12,22 +12,22 @@
|
|||
|
||||
#include <cpu/amd/amdk8_sysconf.h>
|
||||
|
||||
static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0,
|
||||
static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0,
|
||||
uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
|
||||
uint8_t slot, uint8_t rfu)
|
||||
{
|
||||
pirq_info->bus = bus;
|
||||
pirq_info->devfn = devfn;
|
||||
pirq_info->irq[0].link = link0;
|
||||
pirq_info->irq[0].bitmap = bitmap0;
|
||||
pirq_info->irq[1].link = link1;
|
||||
pirq_info->irq[1].bitmap = bitmap1;
|
||||
pirq_info->irq[2].link = link2;
|
||||
pirq_info->irq[2].bitmap = bitmap2;
|
||||
pirq_info->irq[3].link = link3;
|
||||
pirq_info->irq[3].bitmap = bitmap3;
|
||||
pirq_info->slot = slot;
|
||||
pirq_info->rfu = rfu;
|
||||
pirq_info->bus = bus;
|
||||
pirq_info->devfn = devfn;
|
||||
pirq_info->irq[0].link = link0;
|
||||
pirq_info->irq[0].bitmap = bitmap0;
|
||||
pirq_info->irq[1].link = link1;
|
||||
pirq_info->irq[1].bitmap = bitmap1;
|
||||
pirq_info->irq[2].link = link2;
|
||||
pirq_info->irq[2].bitmap = bitmap2;
|
||||
pirq_info->irq[3].link = link3;
|
||||
pirq_info->irq[3].bitmap = bitmap3;
|
||||
pirq_info->slot = slot;
|
||||
pirq_info->rfu = rfu;
|
||||
}
|
||||
|
||||
extern unsigned char bus_isa;
|
||||
|
@ -37,9 +37,9 @@ extern unsigned char bus_ck804_2; //3
|
|||
extern unsigned char bus_ck804_3; //4
|
||||
extern unsigned char bus_ck804_4; //5
|
||||
extern unsigned char bus_ck804_5; //6
|
||||
extern unsigned char bus_8131_0;//7
|
||||
extern unsigned char bus_8131_1;//8
|
||||
extern unsigned char bus_8131_2;//9
|
||||
extern unsigned char bus_8131_0; //7
|
||||
extern unsigned char bus_8131_1; //8
|
||||
extern unsigned char bus_8131_2; //9
|
||||
|
||||
extern unsigned sbdn3;
|
||||
|
||||
|
@ -54,30 +54,30 @@ unsigned long write_pirq_routing_table(unsigned long addr)
|
|||
uint8_t *v;
|
||||
unsigned sbdn;
|
||||
|
||||
uint8_t sum=0;
|
||||
int i;
|
||||
uint8_t sum=0;
|
||||
int i;
|
||||
|
||||
get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
|
||||
get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
|
||||
sbdn = sysconf.sbdn;
|
||||
|
||||
/* Align the table to be 16 byte aligned. */
|
||||
addr += 15;
|
||||
addr &= ~15;
|
||||
/* Align the table to be 16 byte aligned. */
|
||||
addr += 15;
|
||||
addr &= ~15;
|
||||
|
||||
/* This table must be betweeen 0xf0000 & 0x100000 */
|
||||
printk_info("Writing IRQ routing tables to 0x%x...", addr);
|
||||
/* This table must be betweeen 0xf0000 & 0x100000 */
|
||||
printk_info("Writing IRQ routing tables to 0x%x...", addr);
|
||||
|
||||
pirq = (void *)(addr);
|
||||
v = (uint8_t *)(addr);
|
||||
|
||||
|
||||
pirq->signature = PIRQ_SIGNATURE;
|
||||
pirq->version = PIRQ_VERSION;
|
||||
|
||||
|
||||
pirq->rtr_bus = bus_ck804_0;
|
||||
pirq->rtr_devfn = ((sbdn+9)<<3)|0;
|
||||
|
||||
pirq->exclusive_irqs = 0;
|
||||
|
||||
|
||||
pirq->rtr_vendor = 0x10de;
|
||||
pirq->rtr_device = 0x005c;
|
||||
|
||||
|
@ -91,69 +91,69 @@ unsigned long write_pirq_routing_table(unsigned long addr)
|
|||
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+9)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
//pcix bridge
|
||||
write_pirq_info(pirq_info, bus_8131_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
|
||||
write_pirq_info(pirq_info, bus_8131_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
|
||||
#if 0
|
||||
//smbus
|
||||
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+1)<<3)|0, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
pirq_info++; slot_num++;
|
||||
|
||||
//usb
|
||||
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+2)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
pirq_info++; slot_num++;
|
||||
|
||||
//audio
|
||||
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+4)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
pirq_info++; slot_num++;
|
||||
//sata
|
||||
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+7)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
pirq_info++; slot_num++;
|
||||
//sata
|
||||
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+8)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+8)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
//nic
|
||||
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+0xa)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+0xa)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
|
||||
//Slot1 PCIE x16
|
||||
write_pirq_info(pirq_info, bus_ck804_5, (0<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 1, 0);
|
||||
pirq_info++; slot_num++;
|
||||
write_pirq_info(pirq_info, bus_ck804_5, (0<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 1, 0);
|
||||
pirq_info++; slot_num++;
|
||||
|
||||
//firewire
|
||||
write_pirq_info(pirq_info, bus_ck804_1, (0x5<<3)|0, 0x3, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
write_pirq_info(pirq_info, bus_ck804_1, (0x5<<3)|0, 0x3, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
|
||||
//Slot2 pci
|
||||
write_pirq_info(pirq_info, bus_ck804_1, (0x4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 2, 0);
|
||||
pirq_info++; slot_num++;
|
||||
//Slot3 PCIE x16
|
||||
write_pirq_info(pirq_info, bus_ck804b_5, (0<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 3, 0);
|
||||
pirq_info++; slot_num++;
|
||||
write_pirq_info(pirq_info, bus_ck804_1, (0x4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 2, 0);
|
||||
pirq_info++; slot_num++;
|
||||
//Slot3 PCIE x16
|
||||
write_pirq_info(pirq_info, bus_ck804b_5, (0<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 3, 0);
|
||||
pirq_info++; slot_num++;
|
||||
|
||||
//Slot4 PCIX
|
||||
write_pirq_info(pirq_info, bus_8131_2, (4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 4, 0);
|
||||
pirq_info++; slot_num++;
|
||||
write_pirq_info(pirq_info, bus_8131_2, (4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 4, 0);
|
||||
pirq_info++; slot_num++;
|
||||
|
||||
//Slot5 PCIX
|
||||
write_pirq_info(pirq_info, bus_8131_2, (9<<3)|0, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 5, 0);
|
||||
pirq_info++; slot_num++;
|
||||
write_pirq_info(pirq_info, bus_8131_2, (9<<3)|0, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 5, 0);
|
||||
pirq_info++; slot_num++;
|
||||
|
||||
//Slot6 PCIX
|
||||
write_pirq_info(pirq_info, bus_8131_1, (4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 6, 0);
|
||||
pirq_info++; slot_num++;
|
||||
write_pirq_info(pirq_info, bus_8131_1, (4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 6, 0);
|
||||
pirq_info++; slot_num++;
|
||||
#endif
|
||||
|
||||
pirq->size = 32 + 16 * slot_num;
|
||||
|
||||
for (i = 0; i < pirq->size; i++)
|
||||
sum += v[i];
|
||||
pirq->size = 32 + 16 * slot_num;
|
||||
|
||||
for (i = 0; i < pirq->size; i++)
|
||||
sum += v[i];
|
||||
|
||||
sum = pirq->checksum - sum;
|
||||
|
||||
if (sum != pirq->checksum) {
|
||||
pirq->checksum = sum;
|
||||
}
|
||||
if (sum != pirq->checksum) {
|
||||
pirq->checksum = sum;
|
||||
}
|
||||
|
||||
printk_info("done.\n");
|
||||
|
||||
|
|
|
@ -13,64 +13,65 @@ extern unsigned char bus_ck804_2; //3
|
|||
extern unsigned char bus_ck804_3; //4
|
||||
extern unsigned char bus_ck804_4; //5
|
||||
extern unsigned char bus_ck804_5; //6
|
||||
extern unsigned char bus_8131_0;//7
|
||||
extern unsigned char bus_8131_1;//8
|
||||
extern unsigned char bus_8131_2;//9
|
||||
extern unsigned char bus_8131_0; //7
|
||||
extern unsigned char bus_8131_1; //8
|
||||
extern unsigned char bus_8131_2; //9
|
||||
extern unsigned apicid_ck804;
|
||||
extern unsigned apicid_8131_1;
|
||||
extern unsigned apicid_8131_2;
|
||||
|
||||
extern unsigned sbdn3;
|
||||
|
||||
extern void get_bus_conf(void);
|
||||
|
||||
void *smp_write_config_table(void *v)
|
||||
{
|
||||
static const char sig[4] = "PCMP";
|
||||
static const char oem[8] = "TYAN ";
|
||||
static const char productid[12] = "S2892 ";
|
||||
struct mp_config_table *mc;
|
||||
static const char sig[4] = "PCMP";
|
||||
static const char oem[8] = "TYAN ";
|
||||
static const char productid[12] = "S2892 ";
|
||||
struct mp_config_table *mc;
|
||||
unsigned sbdn;
|
||||
|
||||
unsigned char bus_num;
|
||||
unsigned char bus_num;
|
||||
int i;
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
memset(mc, 0, sizeof(*mc));
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
memset(mc, 0, sizeof(*mc));
|
||||
|
||||
memcpy(mc->mpc_signature, sig, sizeof(sig));
|
||||
mc->mpc_length = sizeof(*mc); /* initially just the header */
|
||||
mc->mpc_spec = 0x04;
|
||||
mc->mpc_checksum = 0; /* not yet computed */
|
||||
memcpy(mc->mpc_oem, oem, sizeof(oem));
|
||||
memcpy(mc->mpc_productid, productid, sizeof(productid));
|
||||
mc->mpc_oemptr = 0;
|
||||
mc->mpc_oemsize = 0;
|
||||
mc->mpc_entry_count = 0; /* No entries yet... */
|
||||
mc->mpc_lapic = LAPIC_ADDR;
|
||||
mc->mpe_length = 0;
|
||||
mc->mpe_checksum = 0;
|
||||
mc->reserved = 0;
|
||||
memcpy(mc->mpc_signature, sig, sizeof(sig));
|
||||
mc->mpc_length = sizeof(*mc); /* initially just the header */
|
||||
mc->mpc_spec = 0x04;
|
||||
mc->mpc_checksum = 0; /* not yet computed */
|
||||
memcpy(mc->mpc_oem, oem, sizeof(oem));
|
||||
memcpy(mc->mpc_productid, productid, sizeof(productid));
|
||||
mc->mpc_oemptr = 0;
|
||||
mc->mpc_oemsize = 0;
|
||||
mc->mpc_entry_count = 0; /* No entries yet... */
|
||||
mc->mpc_lapic = LAPIC_ADDR;
|
||||
mc->mpe_length = 0;
|
||||
mc->mpe_checksum = 0;
|
||||
mc->reserved = 0;
|
||||
|
||||
smp_write_processors(mc);
|
||||
smp_write_processors(mc);
|
||||
|
||||
get_bus_conf();
|
||||
sbdn = sysconf.sbdn;
|
||||
|
||||
/*Bus: Bus ID Type*/
|
||||
/* define bus and isa numbers */
|
||||
for(bus_num = 0; bus_num < bus_isa; bus_num++) {
|
||||
smp_write_bus(mc, bus_num, "PCI ");
|
||||
}
|
||||
smp_write_bus(mc, bus_isa, "ISA ");
|
||||
for(bus_num = 0; bus_num < bus_isa; bus_num++) {
|
||||
smp_write_bus(mc, bus_num, "PCI ");
|
||||
}
|
||||
smp_write_bus(mc, bus_isa, "ISA ");
|
||||
|
||||
/*I/O APICs: APIC ID Version State Address*/
|
||||
{
|
||||
device_t dev;
|
||||
{
|
||||
device_t dev;
|
||||
struct resource *res;
|
||||
uint32_t dword;
|
||||
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x1,0));
|
||||
if (dev) {
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x1,0));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_1);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, apicid_ck804, 0x11, res->base);
|
||||
|
@ -79,33 +80,33 @@ void *smp_write_config_table(void *v)
|
|||
/* Initialize interrupt mapping*/
|
||||
|
||||
dword = 0x0120d218;
|
||||
pci_write_config32(dev, 0x7c, dword);
|
||||
pci_write_config32(dev, 0x7c, dword);
|
||||
|
||||
dword = 0x12008a00;
|
||||
pci_write_config32(dev, 0x80, dword);
|
||||
dword = 0x12008a00;
|
||||
pci_write_config32(dev, 0x80, dword);
|
||||
|
||||
dword = 0x0000007d;
|
||||
pci_write_config32(dev, 0x84, dword);
|
||||
dword = 0x0000007d;
|
||||
pci_write_config32(dev, 0x84, dword);
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1));
|
||||
if (dev) {
|
||||
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
|
||||
}
|
||||
}
|
||||
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
|
||||
if (dev) {
|
||||
}
|
||||
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#
|
||||
*/ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_ck804, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_ck804, 0x1);
|
||||
|
@ -121,74 +122,74 @@ void *smp_write_config_table(void *v)
|
|||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_ck804, 0xf);
|
||||
|
||||
// Onboard ck804 smbus
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+1)<<2)|1, apicid_ck804, 0xa);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+1)<<2)|1, apicid_ck804, 0xa);
|
||||
// 10
|
||||
|
||||
// Onboard ck804 USB 1.1
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|0, apicid_ck804, 0x15); // 21
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|0, apicid_ck804, 0x15); // 21
|
||||
|
||||
// Onboard ck804 USB 2
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|1, apicid_ck804, 0x14); // 20
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|1, apicid_ck804, 0x14); // 20
|
||||
|
||||
// Onboard ck804 SATA 0
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +7)<<2)|0, apicid_ck804, 0x17); // 23
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +7)<<2)|0, apicid_ck804, 0x17); // 23
|
||||
|
||||
// Onboard ck804 SATA 1
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +8)<<2)|0, apicid_ck804, 0x16); // 22
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +8)<<2)|0, apicid_ck804, 0x16); // 22
|
||||
|
||||
//Slot PCIE x16
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4);
|
||||
}
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4);
|
||||
}
|
||||
|
||||
//Slot PCIE x4
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|i, apicid_ck804, 0x10 + (1+i+4-sbdn%4)%4);
|
||||
}
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|i, apicid_ck804, 0x10 + (1+i+4-sbdn%4)%4);
|
||||
}
|
||||
|
||||
|
||||
//Slot 2 PCI 32
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (4<<2)|i, apicid_ck804, 0x10+(0+i)%4); //16
|
||||
}
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (4<<2)|i, apicid_ck804, 0x10+(0+i)%4); //16
|
||||
}
|
||||
|
||||
|
||||
//Onboard ati
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (6<<2)|0, apicid_ck804, 0x12); // 18
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (6<<2)|0, apicid_ck804, 0x12); // 18
|
||||
//Onboard intel 10/100
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (8<<2)|0, apicid_ck804, 0x12); // 18
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (8<<2)|0, apicid_ck804, 0x12); // 18
|
||||
|
||||
//Channel B of 8131
|
||||
|
||||
|
||||
//Onboard Broadcom NIC
|
||||
for(i=0;i<2;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|i, apicid_8131_2, (0+i)%4); //28
|
||||
}
|
||||
for(i=0;i<2;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|i, apicid_8131_2, (0+i)%4); //28
|
||||
}
|
||||
|
||||
//SO DIMM PCI-X
|
||||
for(i=0;i<2;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (7<<2)|i, apicid_8131_2, (0+i)%4); //28
|
||||
}
|
||||
for(i=0;i<2;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (7<<2)|i, apicid_8131_2, (0+i)%4); //28
|
||||
}
|
||||
|
||||
//Slot 4 PCIX 133/100/66
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|i, apicid_8131_2, (2+i)%4); //30
|
||||
}
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|i, apicid_8131_2, (2+i)%4); //30
|
||||
}
|
||||
|
||||
|
||||
//Channel A of 8131
|
||||
|
||||
//Slot 5 PCIX 133/100/66
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|i, apicid_8131_1, (3+i)%4); //27
|
||||
}
|
||||
//Slot 5 PCIX 133/100/66
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|i, apicid_8131_1, (3+i)%4); //27
|
||||
}
|
||||
|
||||
|
||||
//Slot 6 PCIX 133/100/66
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|i, apicid_8131_1, (2+i)%4); //26
|
||||
}
|
||||
//Slot 6 PCIX 133/100/66
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|i, apicid_8131_1, (2+i)%4); //26
|
||||
}
|
||||
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
|
||||
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
|
||||
|
|
|
@ -6,7 +6,6 @@
|
|||
static void setup_s2892_resource_map(void)
|
||||
{
|
||||
static const unsigned int register_values[] = {
|
||||
#if 1
|
||||
/* Careful set limit registers before base registers which contain the enables */
|
||||
/* DRAM Limit i Registers
|
||||
* F1:0x44 i = 0
|
||||
|
@ -80,8 +79,6 @@ static void setup_s2892_resource_map(void)
|
|||
PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
|
||||
#endif
|
||||
#if 1
|
||||
|
||||
/* Memory-Mapped I/O Limit i Registers
|
||||
* F1:0x84 i = 0
|
||||
|
@ -158,8 +155,6 @@ static void setup_s2892_resource_map(void)
|
|||
PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
|
||||
// PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
|
||||
#endif
|
||||
#if 1
|
||||
|
||||
/* PCI I/O Limit i Registers
|
||||
* F1:0xC4 i = 0
|
||||
|
@ -220,7 +215,7 @@ static void setup_s2892_resource_map(void)
|
|||
PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
|
||||
#endif
|
||||
|
||||
/* Config Base and Limit i Registers
|
||||
* F1:0xE0 i = 0
|
||||
* F1:0xE4 i = 1
|
||||
|
@ -257,12 +252,10 @@ static void setup_s2892_resource_map(void)
|
|||
* [31:24] Bus Number Limit i
|
||||
* This field defines the highest bus number in configuration region i
|
||||
*/
|
||||
#if 1
|
||||
// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000003, /* link 0 of cpu 0 --> Nvidia CK 804 Pro */
|
||||
// PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203, /* link 2 of cpu 0 --> AMD8131 */
|
||||
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
|
||||
#endif
|
||||
|
||||
};
|
||||
|
||||
|
|
|
@ -19,7 +19,7 @@ end
|
|||
## Compute the start location and size size of
|
||||
## The coreboot bootloader.
|
||||
##
|
||||
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
|
||||
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
|
||||
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
|
||||
|
||||
##
|
||||
|
@ -39,14 +39,14 @@ default XIP_ROM_SIZE=65536
|
|||
if USE_FAILOVER_IMAGE
|
||||
default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
|
||||
else
|
||||
if USE_FALLBACK_IMAGE
|
||||
default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
|
||||
else
|
||||
default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
|
||||
end
|
||||
if USE_FALLBACK_IMAGE
|
||||
default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
|
||||
else
|
||||
default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
|
||||
end
|
||||
end
|
||||
|
||||
arch i386 end
|
||||
arch i386 end
|
||||
|
||||
##
|
||||
## Build the objects we have code for in this directory.
|
||||
|
@ -59,44 +59,45 @@ object get_bus_conf.o
|
|||
if HAVE_MP_TABLE object mptable.o end
|
||||
if HAVE_PIRQ_TABLE object irq_tables.o end
|
||||
#object reset.o
|
||||
|
||||
if USE_DCACHE_RAM
|
||||
|
||||
if CONFIG_USE_INIT
|
||||
makerule ./auto.o
|
||||
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
|
||||
action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
|
||||
end
|
||||
else
|
||||
makerule ./auto.inc
|
||||
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
|
||||
action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
|
||||
action "perl -e 's/.rodata/.rom.data/g' -pi $@"
|
||||
action "perl -e 's/.text/.section .rom.text/g' -pi $@"
|
||||
end
|
||||
if CONFIG_USE_INIT
|
||||
makerule ./auto.o
|
||||
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
|
||||
action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
|
||||
end
|
||||
else
|
||||
makerule ./auto.inc
|
||||
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
|
||||
action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
|
||||
action "perl -e 's/.rodata/.rom.data/g' -pi $@"
|
||||
action "perl -e 's/.text/.section .rom.text/g' -pi $@"
|
||||
end
|
||||
end
|
||||
|
||||
else
|
||||
##
|
||||
## Romcc output
|
||||
##
|
||||
makerule ./failover.E
|
||||
depends "$(MAINBOARD)/failover.c ../romcc"
|
||||
action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
|
||||
depends "$(MAINBOARD)/failover.c ../romcc"
|
||||
action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
|
||||
end
|
||||
|
||||
makerule ./failover.inc
|
||||
depends "$(MAINBOARD)/failover.c ../romcc"
|
||||
action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
|
||||
depends "$(MAINBOARD)/failover.c ../romcc"
|
||||
action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
|
||||
end
|
||||
|
||||
makerule ./auto.E
|
||||
depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
action "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
|
||||
depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
action "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
|
||||
makerule ./auto.inc
|
||||
depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
action "../romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
|
||||
depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
action "../romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
|
||||
end
|
||||
|
@ -105,48 +106,47 @@ end
|
|||
## Build our 16 bit and 32 bit coreboot entry code
|
||||
##
|
||||
if HAVE_FAILOVER_BOOT
|
||||
if USE_FAILOVER_IMAGE
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
end
|
||||
if USE_FAILOVER_IMAGE
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
end
|
||||
else
|
||||
if USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
end
|
||||
if USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
end
|
||||
end
|
||||
|
||||
mainboardinit cpu/x86/32bit/entry32.inc
|
||||
|
||||
if USE_DCACHE_RAM
|
||||
if CONFIG_USE_INIT
|
||||
ldscript /cpu/x86/32bit/entry32.lds
|
||||
end
|
||||
if CONFIG_USE_INIT
|
||||
ldscript /cpu/x86/32bit/entry32.lds
|
||||
end
|
||||
|
||||
if CONFIG_USE_INIT
|
||||
ldscript /cpu/amd/car/cache_as_ram.lds
|
||||
end
|
||||
if CONFIG_USE_INIT
|
||||
ldscript /cpu/amd/car/cache_as_ram.lds
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
##
|
||||
## Build our reset vector (This is where coreboot is entered)
|
||||
##
|
||||
if HAVE_FAILOVER_BOOT
|
||||
if USE_FAILOVER_IMAGE
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
if USE_FAILOVER_IMAGE
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
else
|
||||
mainboardinit cpu/x86/32bit/reset32.inc
|
||||
ldscript /cpu/x86/32bit/reset32.lds
|
||||
mainboardinit cpu/x86/32bit/reset32.inc
|
||||
ldscript /cpu/x86/32bit/reset32.lds
|
||||
end
|
||||
else
|
||||
if USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
if USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
else
|
||||
mainboardinit cpu/x86/32bit/reset32.inc
|
||||
ldscript /cpu/x86/32bit/reset32.lds
|
||||
mainboardinit cpu/x86/32bit/reset32.inc
|
||||
ldscript /cpu/x86/32bit/reset32.lds
|
||||
end
|
||||
end
|
||||
|
||||
|
@ -166,15 +166,15 @@ ldscript /southbridge/nvidia/ck804/id.lds
|
|||
## ROMSTRAP table for CK804
|
||||
##
|
||||
if HAVE_FAILOVER_BOOT
|
||||
if USE_FAILOVER_IMAGE
|
||||
mainboardinit southbridge/nvidia/ck804/romstrap.inc
|
||||
ldscript /southbridge/nvidia/ck804/romstrap.lds
|
||||
end
|
||||
if USE_FAILOVER_IMAGE
|
||||
mainboardinit southbridge/nvidia/ck804/romstrap.inc
|
||||
ldscript /southbridge/nvidia/ck804/romstrap.lds
|
||||
end
|
||||
else
|
||||
if USE_FALLBACK_IMAGE
|
||||
mainboardinit southbridge/nvidia/ck804/romstrap.inc
|
||||
ldscript /southbridge/nvidia/ck804/romstrap.lds
|
||||
end
|
||||
if USE_FALLBACK_IMAGE
|
||||
mainboardinit southbridge/nvidia/ck804/romstrap.inc
|
||||
ldscript /southbridge/nvidia/ck804/romstrap.lds
|
||||
end
|
||||
end
|
||||
|
||||
if USE_DCACHE_RAM
|
||||
|
@ -185,24 +185,24 @@ if USE_DCACHE_RAM
|
|||
end
|
||||
|
||||
###
|
||||
### This is the early phase of coreboot startup
|
||||
### This is the early phase of coreboot startup
|
||||
### Things are delicate and we test to see if we should
|
||||
### failover to another image.
|
||||
###
|
||||
if HAVE_FAILOVER_BOOT
|
||||
if USE_FAILOVER_IMAGE
|
||||
if USE_DCACHE_RAM
|
||||
ldscript /arch/i386/lib/failover_failover.lds
|
||||
if USE_FAILOVER_IMAGE
|
||||
if USE_DCACHE_RAM
|
||||
ldscript /arch/i386/lib/failover_failover.lds
|
||||
end
|
||||
end
|
||||
end
|
||||
else
|
||||
if USE_FALLBACK_IMAGE
|
||||
if USE_DCACHE_RAM
|
||||
ldscript /arch/i386/lib/failover.lds
|
||||
else
|
||||
mainboardinit ./failover.inc
|
||||
if USE_FALLBACK_IMAGE
|
||||
if USE_DCACHE_RAM
|
||||
ldscript /arch/i386/lib/failover.lds
|
||||
else
|
||||
mainboardinit ./failover.inc
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
##
|
||||
|
@ -228,7 +228,7 @@ else
|
|||
end
|
||||
|
||||
##
|
||||
## Include the secondary Configuration files
|
||||
## Include the secondary Configuration files
|
||||
##
|
||||
if CONFIG_CHIP_NAME
|
||||
config chip.h
|
||||
|
@ -236,177 +236,158 @@ end
|
|||
|
||||
# sample config for tyan/s2895
|
||||
chip northbridge/amd/amdk8/root_complex
|
||||
device apic_cluster 0 on
|
||||
chip cpu/amd/socket_940
|
||||
device apic 0 on end
|
||||
end
|
||||
end
|
||||
device apic_cluster 0 on
|
||||
chip cpu/amd/socket_940
|
||||
device apic 0 on end
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on
|
||||
chip northbridge/amd/amdk8 #mc0
|
||||
device pci 18.0 on
|
||||
# devices on link 0, link 0 == LDT 0
|
||||
chip southbridge/nvidia/ck804
|
||||
device pci 18.0 on # northbridge
|
||||
# devices on link 0, link 0 == LDT 0
|
||||
chip southbridge/nvidia/ck804
|
||||
device pci 0.0 on end # HT
|
||||
device pci 1.0 on # LPC
|
||||
chip superio/smsc/lpc47b397
|
||||
device pnp 2e.0 on # Floppy
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 2e.3 off # Parallel Port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 2e.4 on # Com1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.5 off # Com2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.7 on # Keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
irq 0x72 = 12
|
||||
end
|
||||
device pnp 2e.8 on # HW Monitor
|
||||
io 0x60 = 0x290
|
||||
chip drivers/generic/generic # LM95221 CPU temp
|
||||
device i2c 2b on end
|
||||
end
|
||||
chip drivers/generic/generic # EMCT03
|
||||
device i2c 54 on end
|
||||
end
|
||||
device pci 1.0 on # LPC
|
||||
chip superio/smsc/lpc47b397
|
||||
device pnp 2e.0 on # Floppy
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 2e.a on # RT
|
||||
io 0x60 = 0x400
|
||||
device pnp 2e.3 off # Parallel Port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
end
|
||||
device pnp 2e.4 on # Com1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.5 off # Com2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.7 on # Keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
irq 0x72 = 12
|
||||
end
|
||||
device pnp 2e.8 on # HW Monitor
|
||||
io 0x60 = 0x290
|
||||
chip drivers/generic/generic # LM95221 CPU temp
|
||||
device i2c 2b on end
|
||||
end
|
||||
chip drivers/generic/generic # EMCT03
|
||||
device i2c 54 on end
|
||||
end
|
||||
end
|
||||
device pnp 2e.a on # RT
|
||||
io 0x60 = 0x400
|
||||
end
|
||||
end
|
||||
end
|
||||
device pci 1.1 on # SM 0
|
||||
chip drivers/generic/generic #dimm 0-0-0
|
||||
device i2c 50 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-0-1
|
||||
device i2c 51 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-1-0
|
||||
device i2c 52 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-1-1
|
||||
device i2c 53 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-0-0
|
||||
device i2c 54 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-0-1
|
||||
device i2c 55 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-1-0
|
||||
device i2c 56 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-1-1
|
||||
device i2c 57 on end
|
||||
end
|
||||
device pci 1.1 on # SM 0
|
||||
chip drivers/generic/generic #dimm 0-0-0
|
||||
device i2c 50 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-0-1
|
||||
device i2c 51 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-1-0
|
||||
device i2c 52 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-1-1
|
||||
device i2c 53 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-0-0
|
||||
device i2c 54 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-0-1
|
||||
device i2c 55 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-1-0
|
||||
device i2c 56 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-1-1
|
||||
device i2c 57 on end
|
||||
end
|
||||
end # SM
|
||||
device pci 1.1 on # SM 1
|
||||
#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
|
||||
# chip drivers/generic/generic #PCIXA Slot1
|
||||
# device i2c 50 on end
|
||||
# end
|
||||
# chip drivers/generic/generic #PCIXB Slot1
|
||||
# device i2c 51 on end
|
||||
# end
|
||||
# chip drivers/generic/generic #PCIXB Slot2
|
||||
# device i2c 52 on end
|
||||
# end
|
||||
# chip drivers/generic/generic #PCI Slot1
|
||||
# device i2c 53 on end
|
||||
# end
|
||||
# chip drivers/generic/generic #Master CK804 PCI-E
|
||||
# device i2c 54 on end
|
||||
# end
|
||||
# chip drivers/generic/generic #Slave CK804 PCI-E
|
||||
# device i2c 55 on end
|
||||
# end
|
||||
chip drivers/generic/generic #MAC EEPROM
|
||||
device i2c 51 on end
|
||||
end
|
||||
device pci 1.1 on # SM 1
|
||||
chip drivers/generic/generic #MAC EEPROM
|
||||
device i2c 51 on end
|
||||
end
|
||||
|
||||
end # SM
|
||||
device pci 2.0 on end # USB 1.1
|
||||
device pci 2.1 on end # USB 2
|
||||
device pci 4.0 on end # ACI
|
||||
device pci 4.1 off end # MCI
|
||||
device pci 6.0 on end # IDE
|
||||
device pci 7.0 on end # SATA 1
|
||||
device pci 8.0 on end # SATA 0
|
||||
device pci 9.0 on end # PCI
|
||||
device pci a.0 on end # NIC
|
||||
device pci b.0 off end # PCI E 3
|
||||
device pci c.0 off end # PCI E 2
|
||||
device pci d.0 off end # PCI E 1
|
||||
device pci e.0 on end # PCI E 0
|
||||
register "ide0_enable" = "1"
|
||||
register "ide1_enable" = "1"
|
||||
register "sata0_enable" = "1"
|
||||
register "sata1_enable" = "1"
|
||||
end # SM
|
||||
device pci 2.0 on end # USB 1.1
|
||||
device pci 2.1 on end # USB 2
|
||||
device pci 4.0 on end # ACI
|
||||
device pci 4.1 off end # MCI
|
||||
device pci 6.0 on end # IDE
|
||||
device pci 7.0 on end # SATA 1
|
||||
device pci 8.0 on end # SATA 0
|
||||
device pci 9.0 on end # PCI
|
||||
device pci a.0 on end # NIC
|
||||
device pci b.0 off end # PCI E 3
|
||||
device pci c.0 off end # PCI E 2
|
||||
device pci d.0 off end # PCI E 1
|
||||
device pci e.0 on end # PCI E 0
|
||||
register "ide0_enable" = "1"
|
||||
register "ide1_enable" = "1"
|
||||
register "sata0_enable" = "1"
|
||||
register "sata1_enable" = "1"
|
||||
# register "nic_rom_address" = "0xfff80000" # 64k
|
||||
# register "raid_rom_address" = "0xfff90000"
|
||||
register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
|
||||
register "mac_eeprom_addr" = "0x51"
|
||||
end
|
||||
end # device pci 18.0
|
||||
end # device pci 18.0
|
||||
device pci 18.0 on end # Link 1
|
||||
device pci 18.0 on
|
||||
# devices on link 2, link 2 == LDT 2
|
||||
chip southbridge/amd/amd8131
|
||||
# the on/off keyword is mandatory
|
||||
device pci 0.0 on end
|
||||
device pci 0.1 on end
|
||||
device pci 1.0 on
|
||||
chip drivers/pci/onboard
|
||||
device pci 6.0 on end # lsi scsi
|
||||
device pci 6.1 on end
|
||||
end
|
||||
# devices on link 2, link 2 == LDT 2
|
||||
chip southbridge/amd/amd8131
|
||||
# the on/off keyword is mandatory
|
||||
device pci 0.0 on end
|
||||
device pci 0.1 on end
|
||||
device pci 1.0 on
|
||||
chip drivers/pci/onboard
|
||||
device pci 6.0 on end # lsi scsi
|
||||
device pci 6.1 on end
|
||||
end
|
||||
end
|
||||
device pci 1.1 on end
|
||||
end
|
||||
end
|
||||
end # device pci 18.0
|
||||
device pci 18.1 on end
|
||||
device pci 18.2 on end
|
||||
device pci 18.3 on end
|
||||
end # mc0
|
||||
|
||||
end #mc0
|
||||
|
||||
chip northbridge/amd/amdk8
|
||||
device pci 19.0 on # northbridge
|
||||
# devices on link 0, link 0 == LDT 0
|
||||
chip southbridge/nvidia/ck804
|
||||
device pci 0.0 on end # HT
|
||||
device pci 1.0 on end # LPC
|
||||
device pci 1.1 off end # SM
|
||||
device pci 2.0 off end # USB 1.1
|
||||
device pci 2.1 off end # USB 2
|
||||
device pci 4.0 off end # ACI
|
||||
device pci 4.1 off end # MCI
|
||||
device pci 6.0 off end # IDE
|
||||
device pci 7.0 off end # SATA 1
|
||||
device pci 8.0 off end # SATA 0
|
||||
device pci 9.0 off end # PCI
|
||||
device pci a.0 on end # NIC
|
||||
device pci b.0 off end # PCI E 3
|
||||
device pci c.0 off end # PCI E 2
|
||||
device pci d.0 off end # PCI E 1
|
||||
device pci e.0 on end # PCI E 0
|
||||
device pci 19.0 on # northbridge
|
||||
# devices on link 0, link 0 == LDT 0
|
||||
chip southbridge/nvidia/ck804
|
||||
device pci 0.0 on end # HT
|
||||
device pci 1.0 on end # LPC
|
||||
device pci 1.1 off end # SM
|
||||
device pci 2.0 off end # USB 1.1
|
||||
device pci 2.1 off end # USB 2
|
||||
device pci 4.0 off end # ACI
|
||||
device pci 4.1 off end # MCI
|
||||
device pci 6.0 off end # IDE
|
||||
device pci 7.0 off end # SATA 1
|
||||
device pci 8.0 off end # SATA 0
|
||||
device pci 9.0 off end # PCI
|
||||
device pci a.0 on end # NIC
|
||||
device pci b.0 off end # PCI E 3
|
||||
device pci c.0 off end # PCI E 2
|
||||
device pci d.0 off end # PCI E 1
|
||||
device pci e.0 on end # PCI E 0
|
||||
# register "nic_rom_address" = "0xfff80000" # 64k
|
||||
register "mac_eeprom_smbus" = "3"
|
||||
register "mac_eeprom_addr" = "0x51"
|
||||
end
|
||||
end # device pci 19.0
|
||||
|
||||
register "mac_eeprom_smbus" = "3"
|
||||
register "mac_eeprom_addr" = "0x51"
|
||||
end
|
||||
end # device pci 19.0
|
||||
|
||||
device pci 19.0 on end
|
||||
device pci 19.0 on end
|
||||
device pci 19.1 on end
|
||||
|
@ -414,15 +395,15 @@ chip northbridge/amd/amdk8/root_complex
|
|||
device pci 19.3 on end
|
||||
end
|
||||
end # PCI domain
|
||||
|
||||
# chip drivers/generic/debug
|
||||
# device pnp 0.0 off end # chip name
|
||||
# device pnp 0.1 off end # pci_regs_all
|
||||
# device pnp 0.2 off end # mem
|
||||
# device pnp 0.3 off end # cpuid
|
||||
# device pnp 0.4 on end # smbus_regs_all
|
||||
# device pnp 0.5 off end # dual core msr
|
||||
# device pnp 0.6 off end # cache size
|
||||
# device pnp 0.7 off end # tsc
|
||||
# end
|
||||
end #root_complex
|
||||
|
||||
# chip drivers/generic/debug
|
||||
# device pnp 0.0 off end # chip name
|
||||
# device pnp 0.1 off end # pci_regs_all
|
||||
# device pnp 0.2 off end # mem
|
||||
# device pnp 0.3 off end # cpuid
|
||||
# device pnp 0.4 on end # smbus_regs_all
|
||||
# device pnp 0.5 off end # dual core msr
|
||||
# device pnp 0.6 off end # cache size
|
||||
# device pnp 0.7 off end # tsc
|
||||
# end
|
||||
end # root_complex
|
||||
|
|
|
@ -37,7 +37,7 @@ uses MAINBOARD
|
|||
uses MAINBOARD_PART_NUMBER
|
||||
uses MAINBOARD_VENDOR
|
||||
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
|
||||
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
|
||||
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
|
||||
uses COREBOOT_EXTRA_VERSION
|
||||
uses _RAMBASE
|
||||
uses CONFIG_GDB_STUB
|
||||
|
@ -166,7 +166,7 @@ default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
|
|||
#Opteron K8 1G HT Support
|
||||
default K8_HT_FREQ_1G_SUPPORT=1
|
||||
|
||||
#VGA
|
||||
#VGA Console
|
||||
default CONFIG_CONSOLE_VGA=1
|
||||
default CONFIG_PCI_ROM_RUN=1
|
||||
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
#define ASSEMBLY 1
|
||||
|
||||
|
||||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <arch/io.h>
|
||||
|
@ -37,20 +37,20 @@
|
|||
|
||||
static void hard_reset(void)
|
||||
{
|
||||
set_bios_reset();
|
||||
set_bios_reset();
|
||||
|
||||
/* full reset */
|
||||
/* full reset */
|
||||
outb(0x0a, 0x0cf9);
|
||||
outb(0x0e, 0x0cf9);
|
||||
outb(0x0e, 0x0cf9);
|
||||
}
|
||||
|
||||
static void soft_reset(void)
|
||||
{
|
||||
set_bios_reset();
|
||||
set_bios_reset();
|
||||
#if 1
|
||||
/* link reset */
|
||||
/* link reset */
|
||||
outb(0x02, 0x0cf9);
|
||||
outb(0x06, 0x0cf9);
|
||||
outb(0x06, 0x0cf9);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
@ -63,7 +63,7 @@ static void memreset(int controllers, const struct mem_controller *ctrl)
|
|||
}
|
||||
|
||||
#define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
|
||||
|
||||
|
||||
#define SUPERIO_GPIO_IO_BASE 0x400
|
||||
|
||||
static void sio_gpio_setup(void){
|
||||
|
@ -71,13 +71,9 @@ static void sio_gpio_setup(void){
|
|||
unsigned value;
|
||||
|
||||
// lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE); // Already enable in failover.c
|
||||
|
||||
#if 1
|
||||
lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L
|
||||
value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
|
||||
lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1)));
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
static inline void activate_spd_rom(const struct mem_controller *ctrl)
|
||||
|
@ -91,23 +87,14 @@ static inline int spd_read_byte(unsigned device, unsigned address)
|
|||
}
|
||||
|
||||
#define QRANK_DIMM_SUPPORT 1
|
||||
|
||||
#include "northbridge/amd/amdk8/raminit.c"
|
||||
#if 0
|
||||
#define ENABLE_APIC_EXT_ID 1
|
||||
#define APIC_ID_OFFSET 0x10
|
||||
#define LIFT_BSP_APIC_ID 0
|
||||
#else
|
||||
#define ENABLE_APIC_EXT_ID 0
|
||||
#endif
|
||||
#include "northbridge/amd/amdk8/coherent_ht.c"
|
||||
#include "sdram/generic_sdram.c"
|
||||
|
||||
/* tyan does not want the default */
|
||||
#include "resourcemap.c"
|
||||
|
||||
|
||||
#define FIRST_CPU 1
|
||||
#define FIRST_CPU 1
|
||||
#define SECOND_CPU 1
|
||||
#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
|
||||
|
||||
|
@ -116,18 +103,16 @@ static inline int spd_read_byte(unsigned device, unsigned address)
|
|||
#define CK804_USE_NIC 1
|
||||
#define CK804_USE_ACI 1
|
||||
#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
|
||||
|
||||
//set GPIO to input mode
|
||||
#define CK804_MB_SETUP \
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/ \
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/ \
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
|
||||
|
||||
#include "southbridge/nvidia/ck804/ck804_early_setup.c"
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/ \
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/ \
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
|
||||
|
||||
#include "southbridge/nvidia/ck804/ck804_early_setup.c"
|
||||
|
||||
static void main(unsigned long bist)
|
||||
{
|
||||
|
@ -156,41 +141,37 @@ static void main(unsigned long bist)
|
|||
#endif
|
||||
};
|
||||
|
||||
int needs_reset;
|
||||
int needs_reset;
|
||||
|
||||
if (bist == 0) {
|
||||
k8_init_and_stop_secondaries();
|
||||
}
|
||||
if (bist == 0) {
|
||||
k8_init_and_stop_secondaries();
|
||||
}
|
||||
|
||||
// post_code(0x32);
|
||||
lpc47b397_enable_serial(SERIAL_DEV, TTYS0_BASE);
|
||||
uart_init();
|
||||
console_init();
|
||||
|
||||
lpc47b397_enable_serial(SERIAL_DEV, TTYS0_BASE);
|
||||
uart_init();
|
||||
console_init();
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
report_bist_failure(bist);
|
||||
|
||||
sio_gpio_setup();
|
||||
|
||||
setup_s2895_resource_map();
|
||||
setup_s2895_resource_map();
|
||||
|
||||
needs_reset = setup_coherent_ht_domain();
|
||||
|
||||
needs_reset |= ht_setup_chains_x();
|
||||
needs_reset |= ht_setup_chains_x();
|
||||
|
||||
needs_reset |= ck804_early_setup_x();
|
||||
|
||||
if (needs_reset) {
|
||||
print_info("ht reset -\r\n");
|
||||
soft_reset();
|
||||
}
|
||||
needs_reset |= ck804_early_setup_x();
|
||||
|
||||
if (needs_reset) {
|
||||
print_info("ht reset -\r\n");
|
||||
soft_reset();
|
||||
}
|
||||
|
||||
enable_smbus();
|
||||
|
||||
memreset_setup();
|
||||
sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
|
||||
|
||||
|
||||
}
|
||||
|
|
|
@ -1,18 +1,16 @@
|
|||
#define ASSEMBLY 1
|
||||
#define __ROMCC__
|
||||
|
||||
|
||||
#define K8_ALLOCATE_IO_RANGE 1
|
||||
//#define K8_SCAN_PCI_BUS 1
|
||||
|
||||
|
||||
//used by raminit
|
||||
#define QRANK_DIMM_SUPPORT 1
|
||||
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
#define SET_NB_CFG_54 1
|
||||
#endif
|
||||
|
||||
|
||||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <arch/io.h>
|
||||
|
@ -27,17 +25,6 @@
|
|||
#include "arch/i386/lib/console.c"
|
||||
#include "ram/ramtest.c"
|
||||
|
||||
#if 0
|
||||
static void post_code(uint8_t value) {
|
||||
#if 1
|
||||
int i;
|
||||
for(i=0;i<0x8000;i++) {
|
||||
outb(value, 0x80);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
#include <cpu/amd/model_fxx_rev.h>
|
||||
|
||||
#include "northbridge/amd/amdk8/incoherent_ht.c"
|
||||
|
@ -68,7 +55,6 @@ static void post_code(uint8_t value) {
|
|||
|
||||
#include "cpu/amd/mtrr/amd_earlymtrr.c"
|
||||
|
||||
|
||||
#include "northbridge/amd/amdk8/setup_resource_map.c"
|
||||
|
||||
#define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
|
||||
|
@ -81,15 +67,14 @@ static void memreset(int controllers, const struct mem_controller *ctrl)
|
|||
{
|
||||
}
|
||||
|
||||
|
||||
static void sio_gpio_setup(void){
|
||||
|
||||
unsigned value;
|
||||
unsigned value;
|
||||
|
||||
/*Enable onboard scsi*/
|
||||
lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L
|
||||
value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
|
||||
lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1)));
|
||||
/*Enable onboard scsi*/
|
||||
lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L
|
||||
value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
|
||||
lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1)));
|
||||
|
||||
}
|
||||
|
||||
|
@ -103,13 +88,12 @@ static inline int spd_read_byte(unsigned device, unsigned address)
|
|||
return smbus_read_byte(device, address);
|
||||
}
|
||||
|
||||
|
||||
#include "northbridge/amd/amdk8/raminit.c"
|
||||
#include "northbridge/amd/amdk8/coherent_ht.c"
|
||||
#include "sdram/generic_sdram.c"
|
||||
|
||||
/* tyan does not want the default */
|
||||
#include "resourcemap.c"
|
||||
#include "resourcemap.c"
|
||||
|
||||
#include "cpu/amd/dualcore/dualcore.c"
|
||||
|
||||
|
@ -122,12 +106,12 @@ static inline int spd_read_byte(unsigned device, unsigned address)
|
|||
|
||||
//set GPIO to input mode
|
||||
#define CK804_MB_SETUP \
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/ \
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/ \
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/ \
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/ \
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
|
||||
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
|
||||
|
||||
#include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
|
||||
|
||||
|
@ -144,105 +128,103 @@ static inline int spd_read_byte(unsigned device, unsigned address)
|
|||
#include "southbridge/nvidia/ck804/ck804_enable_rom.c"
|
||||
#include "northbridge/amd/amdk8/early_ht.c"
|
||||
|
||||
|
||||
static void sio_setup(void)
|
||||
{
|
||||
|
||||
unsigned value;
|
||||
uint32_t dword;
|
||||
uint8_t byte;
|
||||
unsigned value;
|
||||
uint32_t dword;
|
||||
uint8_t byte;
|
||||
|
||||
|
||||
pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);
|
||||
|
||||
byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
|
||||
byte |= 0x20;
|
||||
pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
|
||||
|
||||
dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
|
||||
dword |= (1<<29)|(1<<0);
|
||||
pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
|
||||
|
||||
dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xa4);
|
||||
dword |= (1<<16);
|
||||
pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword);
|
||||
pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);
|
||||
|
||||
lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE);
|
||||
value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77);
|
||||
value &= 0xbf;
|
||||
lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value);
|
||||
byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
|
||||
byte |= 0x20;
|
||||
pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
|
||||
|
||||
dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
|
||||
dword |= (1<<29)|(1<<0);
|
||||
pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
|
||||
|
||||
dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xa4);
|
||||
dword |= (1<<16);
|
||||
pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword);
|
||||
|
||||
lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE);
|
||||
value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77);
|
||||
value &= 0xbf;
|
||||
lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value);
|
||||
|
||||
}
|
||||
|
||||
void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
{
|
||||
unsigned last_boot_normal_x = last_boot_normal();
|
||||
unsigned last_boot_normal_x = last_boot_normal();
|
||||
|
||||
/* Is this a cpu only reset? or Is this a secondary cpu? */
|
||||
if ((cpu_init_detectedx) || (!boot_cpu())) {
|
||||
if (last_boot_normal_x) {
|
||||
goto normal_image;
|
||||
} else {
|
||||
goto fallback_image;
|
||||
}
|
||||
}
|
||||
/* Is this a cpu only reset? or Is this a secondary cpu? */
|
||||
if ((cpu_init_detectedx) || (!boot_cpu())) {
|
||||
if (last_boot_normal_x) {
|
||||
goto normal_image;
|
||||
} else {
|
||||
goto fallback_image;
|
||||
}
|
||||
}
|
||||
|
||||
/* Nothing special needs to be done to find bus 0 */
|
||||
/* Allow the HT devices to be found */
|
||||
/* Nothing special needs to be done to find bus 0 */
|
||||
/* Allow the HT devices to be found */
|
||||
|
||||
enumerate_ht_chain();
|
||||
enumerate_ht_chain();
|
||||
|
||||
sio_setup();
|
||||
sio_setup();
|
||||
|
||||
/* Setup the ck804 */
|
||||
ck804_enable_rom();
|
||||
/* Setup the ck804 */
|
||||
ck804_enable_rom();
|
||||
|
||||
/* Is this a deliberate reset by the bios */
|
||||
// post_code(0x22);
|
||||
if (bios_reset_detected() && last_boot_normal_x) {
|
||||
goto normal_image;
|
||||
}
|
||||
/* This is the primary cpu how should I boot? */
|
||||
else if (do_normal_boot()) {
|
||||
goto normal_image;
|
||||
}
|
||||
else {
|
||||
goto fallback_image;
|
||||
}
|
||||
/* Is this a deliberate reset by the bios */
|
||||
// post_code(0x22);
|
||||
if (bios_reset_detected() && last_boot_normal_x) {
|
||||
goto normal_image;
|
||||
}
|
||||
/* This is the primary cpu how should I boot? */
|
||||
else if (do_normal_boot()) {
|
||||
goto normal_image;
|
||||
}
|
||||
else {
|
||||
goto fallback_image;
|
||||
}
|
||||
normal_image:
|
||||
// post_code(0x23);
|
||||
__asm__ volatile ("jmp __normal_image"
|
||||
: /* outputs */
|
||||
: "a" (bist), "b" (cpu_init_detectedx) /* inputs */
|
||||
);
|
||||
// post_code(0x23);
|
||||
__asm__ volatile ("jmp __normal_image"
|
||||
: /* outputs */
|
||||
: "a" (bist), "b"(cpu_init_detectedx) /* inputs */
|
||||
);
|
||||
|
||||
fallback_image:
|
||||
// post_code(0x25);
|
||||
// post_code(0x25);
|
||||
#if HAVE_FAILOVER_BOOT==1
|
||||
__asm__ volatile ("jmp __fallback_image"
|
||||
: /* outputs */
|
||||
: "a" (bist), "b" (cpu_init_detectedx) /* inputs */
|
||||
)
|
||||
__asm__ volatile ("jmp __fallback_image"
|
||||
: /* outputs */
|
||||
: "a" (bist), "b" (cpu_init_detectedx) /* inputs */
|
||||
)
|
||||
#endif
|
||||
;
|
||||
}
|
||||
#endif
|
||||
|
||||
void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
|
||||
|
||||
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
{
|
||||
#if HAVE_FAILOVER_BOOT==1
|
||||
#if USE_FAILOVER_IMAGE==1
|
||||
failover_process(bist, cpu_init_detectedx);
|
||||
#else
|
||||
real_main(bist, cpu_init_detectedx);
|
||||
#endif
|
||||
#if HAVE_FAILOVER_BOOT==1
|
||||
#if USE_FAILOVER_IMAGE==1
|
||||
failover_process(bist, cpu_init_detectedx);
|
||||
#endif
|
||||
#else
|
||||
#if USE_FALLBACK_IMAGE == 1
|
||||
failover_process(bist, cpu_init_detectedx);
|
||||
#endif
|
||||
real_main(bist, cpu_init_detectedx);
|
||||
#if USE_FALLBACK_IMAGE == 1
|
||||
failover_process(bist, cpu_init_detectedx);
|
||||
#endif
|
||||
#endif
|
||||
real_main(bist, cpu_init_detectedx);
|
||||
|
||||
}
|
||||
|
||||
#if USE_FAILOVER_IMAGE==0
|
||||
|
@ -250,38 +232,38 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
|||
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
{
|
||||
static const uint16_t spd_addr [] = {
|
||||
(0xa<<3)|0, (0xa<<3)|2, 0, 0,
|
||||
(0xa<<3)|1, (0xa<<3)|3, 0, 0,
|
||||
(0xa<<3)|0, (0xa<<3)|2, 0, 0,
|
||||
(0xa<<3)|1, (0xa<<3)|3, 0, 0,
|
||||
#if CONFIG_MAX_PHYSICAL_CPUS > 1
|
||||
(0xa<<3)|4, (0xa<<3)|6, 0, 0,
|
||||
(0xa<<3)|5, (0xa<<3)|7, 0, 0,
|
||||
(0xa<<3)|4, (0xa<<3)|6, 0, 0,
|
||||
(0xa<<3)|5, (0xa<<3)|7, 0, 0,
|
||||
#endif
|
||||
};
|
||||
|
||||
int needs_reset;
|
||||
unsigned bsp_apicid = 0;
|
||||
int needs_reset;
|
||||
unsigned bsp_apicid = 0;
|
||||
|
||||
struct mem_controller ctrl[8];
|
||||
unsigned nodes;
|
||||
struct mem_controller ctrl[8];
|
||||
unsigned nodes;
|
||||
|
||||
if (bist == 0) {
|
||||
bsp_apicid = init_cpus(cpu_init_detectedx);
|
||||
}
|
||||
if (bist == 0) {
|
||||
bsp_apicid = init_cpus(cpu_init_detectedx);
|
||||
}
|
||||
|
||||
// post_code(0x32);
|
||||
|
||||
lpc47b397_enable_serial(SERIAL_DEV, TTYS0_BASE);
|
||||
uart_init();
|
||||
console_init();
|
||||
|
||||
uart_init();
|
||||
console_init();
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
report_bist_failure(bist);
|
||||
|
||||
sio_gpio_setup();
|
||||
|
||||
setup_mb_resource_map();
|
||||
setup_mb_resource_map();
|
||||
#if 0
|
||||
dump_pci_device(PCI_DEV(0, 0x18, 0));
|
||||
dump_pci_device(PCI_DEV(0, 0x18, 0));
|
||||
dump_pci_device(PCI_DEV(0, 0x19, 0));
|
||||
#endif
|
||||
|
||||
|
@ -289,25 +271,25 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
|||
|
||||
wait_all_core0_started();
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
// It is said that we should start core1 after all core0 launched
|
||||
start_other_cores();
|
||||
// It is said that we should start core1 after all core0 launched
|
||||
start_other_cores();
|
||||
wait_all_other_cores_started(bsp_apicid);
|
||||
#endif
|
||||
|
||||
needs_reset |= ht_setup_chains_x();
|
||||
needs_reset |= ht_setup_chains_x();
|
||||
|
||||
needs_reset |= ck804_early_setup_x();
|
||||
needs_reset |= ck804_early_setup_x();
|
||||
|
||||
if (needs_reset) {
|
||||
print_info("ht reset -\r\n");
|
||||
// soft_reset();
|
||||
}
|
||||
if (needs_reset) {
|
||||
print_info("ht reset -\r\n");
|
||||
// soft_reset();
|
||||
}
|
||||
|
||||
allow_all_aps_stop(bsp_apicid);
|
||||
allow_all_aps_stop(bsp_apicid);
|
||||
|
||||
nodes = get_nodes();
|
||||
//It's the time to set ctrl now;
|
||||
fill_mem_ctrl(nodes, ctrl, spd_addr);
|
||||
nodes = get_nodes();
|
||||
//It's the time to set ctrl now;
|
||||
fill_mem_ctrl(nodes, ctrl, spd_addr);
|
||||
|
||||
enable_smbus();
|
||||
#if 0
|
||||
|
|
|
@ -50,14 +50,12 @@ static void sio_setup(void)
|
|||
|
||||
}
|
||||
|
||||
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
#include "cpu/amd/dualcore/dualcore_id.c"
|
||||
#else
|
||||
#include "cpu/amd/model_fxx/node_id.c"
|
||||
#endif
|
||||
|
||||
|
||||
static unsigned long main(unsigned long bist)
|
||||
{
|
||||
/* Is this a cpu only reset? */
|
||||
|
|
|
@ -9,7 +9,6 @@
|
|||
|
||||
#include <cpu/amd/amdk8_sysconf.h>
|
||||
|
||||
|
||||
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
|
||||
//busnum is default
|
||||
unsigned char bus_isa;
|
||||
|
@ -33,7 +32,7 @@
|
|||
unsigned apicid_8131_2;
|
||||
unsigned apicid_ck804b;
|
||||
|
||||
unsigned pci1234x[] =
|
||||
unsigned pci1234x[] =
|
||||
{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not
|
||||
//You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
|
||||
0x0000ff0,
|
||||
|
@ -45,7 +44,7 @@ unsigned pci1234x[] =
|
|||
// 0x0000ff0,
|
||||
// 0x0000ff0
|
||||
};
|
||||
unsigned hcdnx[] =
|
||||
unsigned hcdnx[] =
|
||||
{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
|
||||
0x20202020,
|
||||
0x20202020,
|
||||
|
@ -56,6 +55,7 @@ unsigned hcdnx[] =
|
|||
// 0x20202020,
|
||||
// 0x20202020,
|
||||
};
|
||||
|
||||
unsigned sbdn3;
|
||||
unsigned sbdnb;
|
||||
|
||||
|
@ -97,63 +97,15 @@ void get_bus_conf(void)
|
|||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x09,0));
|
||||
if (dev) {
|
||||
bus_ck804_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
#if 0
|
||||
bus_ck804_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_2++;
|
||||
#else
|
||||
bus_ck804_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_5++;
|
||||
#endif
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x09);
|
||||
|
||||
bus_ck804_1 = 2;
|
||||
#if 0
|
||||
bus_ck804_2 = 3;
|
||||
#else
|
||||
bus_ck804_5 = 3;
|
||||
#endif
|
||||
|
||||
}
|
||||
#if 0
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0b,0));
|
||||
if (dev) {
|
||||
bus_ck804_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_ck804_3 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_3++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x0b);
|
||||
|
||||
bus_ck804_3 = bus_ck804_2+1;
|
||||
}
|
||||
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0c,0));
|
||||
if (dev) {
|
||||
bus_ck804_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_4++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x0c);
|
||||
|
||||
bus_ck804_4 = bus_ck804_3+1;
|
||||
}
|
||||
|
||||
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0d,0));
|
||||
if (dev) {
|
||||
bus_ck804_4 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_ck804_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804_5++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n",sbdn + 0x0d);
|
||||
|
||||
bus_ck804_5 = bus_ck804_4+1;
|
||||
}
|
||||
#endif
|
||||
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x0e,0));
|
||||
if (dev) {
|
||||
|
@ -194,56 +146,6 @@ void get_bus_conf(void)
|
|||
|
||||
if(sysconf.pci1234[2] & 0x0f) { //if the second cpu is installed
|
||||
bus_ck804b_0 = (sysconf.pci1234[2]>>16) & 0xff;
|
||||
#if 0
|
||||
dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x09,0));
|
||||
if (dev) {
|
||||
bus_ck804b_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_ck804b_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804b_2++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,sbdnb+0x09);
|
||||
|
||||
bus_ck804b_1 = bus_ck804b_0+1;
|
||||
bus_ck804b_2 = bus_ck804b_0+2;
|
||||
}
|
||||
|
||||
dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x0b,0));
|
||||
if (dev) {
|
||||
bus_ck804b_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_ck804b_3 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804b_3++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,sbdnb+0x0b);
|
||||
|
||||
bus_ck804b_2 = bus_ck804b_0+1;
|
||||
bus_ck804b_3 = bus_ck804b_0+2;
|
||||
}
|
||||
|
||||
dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x0c,0));
|
||||
if (dev) {
|
||||
bus_ck804b_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_ck804b_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804b_4++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,sbdnb+0x0c);
|
||||
|
||||
bus_ck804b_4 = bus_ck804b_3+1;
|
||||
}
|
||||
dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x0d,0));
|
||||
if (dev) {
|
||||
bus_ck804b_4 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_ck804b_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_ck804b_5++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,sbdnb+0x0d);
|
||||
|
||||
bus_ck804b_5 = bus_ck804b_4+1;
|
||||
}
|
||||
#endif
|
||||
|
||||
dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x0e,0));
|
||||
if (dev) {
|
||||
|
@ -253,10 +155,7 @@ void get_bus_conf(void)
|
|||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,sbdnb+0x0e);
|
||||
#if 1
|
||||
bus_ck804b_5 = bus_ck804b_4+1;
|
||||
#endif
|
||||
|
||||
bus_isa = bus_ck804b_5+1;
|
||||
}
|
||||
}
|
||||
|
@ -265,12 +164,11 @@ void get_bus_conf(void)
|
|||
/*I/O APICs: APIC ID Version State Address*/
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
apicid_base = get_apicid_base(4);
|
||||
#else
|
||||
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
|
||||
#else
|
||||
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
|
||||
#endif
|
||||
apicid_ck804 = apicid_base+0;
|
||||
apicid_8131_1 = apicid_base+1;
|
||||
apicid_8131_2 = apicid_base+2;
|
||||
apicid_ck804b = apicid_base+3;
|
||||
|
||||
}
|
||||
|
|
|
@ -1,4 +1,4 @@
|
|||
/* This file was generated by getpir.c, do not modify!
|
||||
/* This file was generated by getpir.c, do not modify!
|
||||
(but if you do, please run checkpir on it to verify)
|
||||
Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
|
||||
|
||||
|
@ -12,22 +12,22 @@
|
|||
|
||||
#include <cpu/amd/amdk8_sysconf.h>
|
||||
|
||||
static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0,
|
||||
static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0,
|
||||
uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
|
||||
uint8_t slot, uint8_t rfu)
|
||||
{
|
||||
pirq_info->bus = bus;
|
||||
pirq_info->devfn = devfn;
|
||||
pirq_info->irq[0].link = link0;
|
||||
pirq_info->irq[0].bitmap = bitmap0;
|
||||
pirq_info->irq[1].link = link1;
|
||||
pirq_info->irq[1].bitmap = bitmap1;
|
||||
pirq_info->irq[2].link = link2;
|
||||
pirq_info->irq[2].bitmap = bitmap2;
|
||||
pirq_info->irq[3].link = link3;
|
||||
pirq_info->irq[3].bitmap = bitmap3;
|
||||
pirq_info->slot = slot;
|
||||
pirq_info->rfu = rfu;
|
||||
pirq_info->bus = bus;
|
||||
pirq_info->devfn = devfn;
|
||||
pirq_info->irq[0].link = link0;
|
||||
pirq_info->irq[0].bitmap = bitmap0;
|
||||
pirq_info->irq[1].link = link1;
|
||||
pirq_info->irq[1].bitmap = bitmap1;
|
||||
pirq_info->irq[2].link = link2;
|
||||
pirq_info->irq[2].bitmap = bitmap2;
|
||||
pirq_info->irq[3].link = link3;
|
||||
pirq_info->irq[3].bitmap = bitmap3;
|
||||
pirq_info->slot = slot;
|
||||
pirq_info->rfu = rfu;
|
||||
}
|
||||
|
||||
extern unsigned char bus_ck804_0; //1
|
||||
|
@ -50,6 +50,8 @@ extern unsigned char bus_ck804b_5;//f
|
|||
extern unsigned sbdn3;
|
||||
extern unsigned sbdnb;
|
||||
|
||||
extern void get_bus_conf(void);
|
||||
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
|
||||
|
@ -59,30 +61,30 @@ unsigned long write_pirq_routing_table(unsigned long addr)
|
|||
uint8_t *v;
|
||||
unsigned sbdn;
|
||||
|
||||
uint8_t sum=0;
|
||||
int i;
|
||||
uint8_t sum=0;
|
||||
int i;
|
||||
|
||||
get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
|
||||
get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
|
||||
sbdn = sysconf.sbdn;
|
||||
|
||||
/* Align the table to be 16 byte aligned. */
|
||||
addr += 15;
|
||||
addr &= ~15;
|
||||
/* Align the table to be 16 byte aligned. */
|
||||
addr += 15;
|
||||
addr &= ~15;
|
||||
|
||||
/* This table must be betweeen 0xf0000 & 0x100000 */
|
||||
printk_info("Writing IRQ routing tables to 0x%x...", addr);
|
||||
/* This table must be betweeen 0xf0000 & 0x100000 */
|
||||
printk_info("Writing IRQ routing tables to 0x%x...", addr);
|
||||
|
||||
pirq = (void *)(addr);
|
||||
v = (uint8_t *)(addr);
|
||||
|
||||
|
||||
pirq->signature = PIRQ_SIGNATURE;
|
||||
pirq->version = PIRQ_VERSION;
|
||||
|
||||
|
||||
pirq->rtr_bus = bus_ck804_0;
|
||||
pirq->rtr_devfn = ((sbdn+9)<<3)|0;
|
||||
|
||||
pirq->exclusive_irqs = 0;
|
||||
|
||||
|
||||
pirq->rtr_vendor = 0x10de;
|
||||
pirq->rtr_device = 0x005c;
|
||||
|
||||
|
@ -96,81 +98,81 @@ unsigned long write_pirq_routing_table(unsigned long addr)
|
|||
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+9)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
//pcix bridge
|
||||
write_pirq_info(pirq_info, bus_8131_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
|
||||
if(sysconf.pci1234[2] & 0xf) {
|
||||
//second pci beidge
|
||||
write_pirq_info(pirq_info, bus_ck804b_0, ((sbdnb+9)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
write_pirq_info(pirq_info, bus_8131_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
|
||||
if(sysconf.pci1234[2] & 0xf) {
|
||||
//second pci beidge
|
||||
write_pirq_info(pirq_info, bus_ck804b_0, ((sbdnb+9)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
}
|
||||
#if 0
|
||||
//smbus
|
||||
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+1)<<3)|0, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
pirq_info++; slot_num++;
|
||||
|
||||
//usb
|
||||
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+2)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
pirq_info++; slot_num++;
|
||||
|
||||
//audio
|
||||
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+4)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
pirq_info++; slot_num++;
|
||||
//sata
|
||||
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+7)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
pirq_info++; slot_num++;
|
||||
//sata
|
||||
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+8)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+8)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
//nic
|
||||
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+0xa)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+0xa)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
|
||||
//Slot1 PCIE x16
|
||||
write_pirq_info(pirq_info, bus_ck804_5, (0<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 1, 0);
|
||||
pirq_info++; slot_num++;
|
||||
write_pirq_info(pirq_info, bus_ck804_5, (0<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 1, 0);
|
||||
pirq_info++; slot_num++;
|
||||
|
||||
//firewire
|
||||
write_pirq_info(pirq_info, bus_ck804_1, (0x5<<3)|0, 0x3, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
write_pirq_info(pirq_info, bus_ck804_1, (0x5<<3)|0, 0x3, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
|
||||
//Slot2 pci
|
||||
write_pirq_info(pirq_info, bus_ck804_1, (0x4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 2, 0);
|
||||
pirq_info++; slot_num++;
|
||||
//nic
|
||||
write_pirq_info(pirq_info, bus_ck804b_0, ((sbdnb+0xa)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
//Slot3 PCIE x16
|
||||
write_pirq_info(pirq_info, bus_ck804b_5, (0<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 3, 0);
|
||||
pirq_info++; slot_num++;
|
||||
write_pirq_info(pirq_info, bus_ck804_1, (0x4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 2, 0);
|
||||
pirq_info++; slot_num++;
|
||||
//nic
|
||||
write_pirq_info(pirq_info, bus_ck804b_0, ((sbdnb+0xa)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
//Slot3 PCIE x16
|
||||
write_pirq_info(pirq_info, bus_ck804b_5, (0<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 3, 0);
|
||||
pirq_info++; slot_num++;
|
||||
|
||||
//Slot4 PCIX
|
||||
write_pirq_info(pirq_info, bus_8131_2, (4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 4, 0);
|
||||
pirq_info++; slot_num++;
|
||||
write_pirq_info(pirq_info, bus_8131_2, (4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 4, 0);
|
||||
pirq_info++; slot_num++;
|
||||
|
||||
//Slot5 PCIX
|
||||
write_pirq_info(pirq_info, bus_8131_2, (9<<3)|0, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 5, 0);
|
||||
pirq_info++; slot_num++;
|
||||
write_pirq_info(pirq_info, bus_8131_2, (9<<3)|0, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 5, 0);
|
||||
pirq_info++; slot_num++;
|
||||
|
||||
//onboard scsi
|
||||
write_pirq_info(pirq_info, bus_8131_2, (6<<3)|0, 0x2, 0xdef8, 0x3, 0xdef8, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
write_pirq_info(pirq_info, bus_8131_2, (6<<3)|0, 0x2, 0xdef8, 0x3, 0xdef8, 0, 0, 0, 0, 0, 0);
|
||||
pirq_info++; slot_num++;
|
||||
|
||||
//Slot6 PCIX
|
||||
write_pirq_info(pirq_info, bus_8131_1, (4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 6, 0);
|
||||
pirq_info++; slot_num++;
|
||||
write_pirq_info(pirq_info, bus_8131_1, (4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 6, 0);
|
||||
pirq_info++; slot_num++;
|
||||
#endif
|
||||
|
||||
pirq->size = 32 + 16 * slot_num;
|
||||
|
||||
for (i = 0; i < pirq->size; i++)
|
||||
sum += v[i];
|
||||
pirq->size = 32 + 16 * slot_num;
|
||||
|
||||
for (i = 0; i < pirq->size; i++)
|
||||
sum += v[i];
|
||||
|
||||
sum = pirq->checksum - sum;
|
||||
|
||||
if (sum != pirq->checksum) {
|
||||
pirq->checksum = sum;
|
||||
}
|
||||
if (sum != pirq->checksum) {
|
||||
pirq->checksum = sum;
|
||||
}
|
||||
|
||||
printk_info("done.\n");
|
||||
|
||||
|
|
|
@ -30,54 +30,56 @@ extern unsigned apicid_ck804b;
|
|||
extern unsigned sbdn3;
|
||||
extern unsigned sbdnb;
|
||||
|
||||
extern void get_bus_conf(void);
|
||||
|
||||
void *smp_write_config_table(void *v)
|
||||
{
|
||||
static const char sig[4] = "PCMP";
|
||||
static const char oem[8] = "TYAN ";
|
||||
static const char productid[12] = "S2895 ";
|
||||
struct mp_config_table *mc;
|
||||
static const char sig[4] = "PCMP";
|
||||
static const char oem[8] = "TYAN ";
|
||||
static const char productid[12] = "S2895 ";
|
||||
struct mp_config_table *mc;
|
||||
unsigned sbdn;
|
||||
|
||||
unsigned char bus_num;
|
||||
unsigned char bus_num;
|
||||
int i;
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
memset(mc, 0, sizeof(*mc));
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
memset(mc, 0, sizeof(*mc));
|
||||
|
||||
memcpy(mc->mpc_signature, sig, sizeof(sig));
|
||||
mc->mpc_length = sizeof(*mc); /* initially just the header */
|
||||
mc->mpc_spec = 0x04;
|
||||
mc->mpc_checksum = 0; /* not yet computed */
|
||||
memcpy(mc->mpc_oem, oem, sizeof(oem));
|
||||
memcpy(mc->mpc_productid, productid, sizeof(productid));
|
||||
mc->mpc_oemptr = 0;
|
||||
mc->mpc_oemsize = 0;
|
||||
mc->mpc_entry_count = 0; /* No entries yet... */
|
||||
mc->mpc_lapic = LAPIC_ADDR;
|
||||
mc->mpe_length = 0;
|
||||
mc->mpe_checksum = 0;
|
||||
mc->reserved = 0;
|
||||
memcpy(mc->mpc_signature, sig, sizeof(sig));
|
||||
mc->mpc_length = sizeof(*mc); /* initially just the header */
|
||||
mc->mpc_spec = 0x04;
|
||||
mc->mpc_checksum = 0; /* not yet computed */
|
||||
memcpy(mc->mpc_oem, oem, sizeof(oem));
|
||||
memcpy(mc->mpc_productid, productid, sizeof(productid));
|
||||
mc->mpc_oemptr = 0;
|
||||
mc->mpc_oemsize = 0;
|
||||
mc->mpc_entry_count = 0; /* No entries yet... */
|
||||
mc->mpc_lapic = LAPIC_ADDR;
|
||||
mc->mpe_length = 0;
|
||||
mc->mpe_checksum = 0;
|
||||
mc->reserved = 0;
|
||||
|
||||
smp_write_processors(mc);
|
||||
smp_write_processors(mc);
|
||||
|
||||
get_bus_conf();
|
||||
sbdn = sysconf.sbdn;
|
||||
|
||||
/*Bus: Bus ID Type*/
|
||||
/* define bus and isa numbers */
|
||||
for(bus_num = 0; bus_num < bus_isa; bus_num++) {
|
||||
smp_write_bus(mc, bus_num, "PCI ");
|
||||
}
|
||||
smp_write_bus(mc, bus_isa, "ISA ");
|
||||
for(bus_num = 0; bus_num < bus_isa; bus_num++) {
|
||||
smp_write_bus(mc, bus_num, "PCI ");
|
||||
}
|
||||
smp_write_bus(mc, bus_isa, "ISA ");
|
||||
|
||||
/*I/O APICs: APIC ID Version State Address*/
|
||||
{
|
||||
device_t dev;
|
||||
{
|
||||
device_t dev;
|
||||
struct resource *res;
|
||||
uint32_t dword;
|
||||
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x1,0));
|
||||
if (dev) {
|
||||
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x1,0));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_1);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, apicid_ck804, 0x11, res->base);
|
||||
|
@ -86,53 +88,53 @@ void *smp_write_config_table(void *v)
|
|||
/* Initialize interrupt mapping*/
|
||||
|
||||
dword = 0x0120d218;
|
||||
pci_write_config32(dev, 0x7c, dword);
|
||||
pci_write_config32(dev, 0x7c, dword);
|
||||
|
||||
dword = 0x12008a00;
|
||||
pci_write_config32(dev, 0x80, dword);
|
||||
dword = 0x12008a00;
|
||||
pci_write_config32(dev, 0x80, dword);
|
||||
|
||||
dword = 0x00080d7d;
|
||||
pci_write_config32(dev, 0x84, dword);
|
||||
dword = 0x00080d7d;
|
||||
pci_write_config32(dev, 0x84, dword);
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1));
|
||||
if (dev) {
|
||||
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
|
||||
}
|
||||
}
|
||||
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
|
||||
if (dev) {
|
||||
}
|
||||
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if(sysconf.pci1234[2] & 0xf) {
|
||||
dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x1,0));
|
||||
if (dev) {
|
||||
dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x1,0));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_1);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, apicid_ck804b, 0x11, res->base);
|
||||
}
|
||||
|
||||
dword = 0x0000d218;
|
||||
pci_write_config32(dev, 0x7c, dword);
|
||||
pci_write_config32(dev, 0x7c, dword);
|
||||
|
||||
dword = 0x00000000;
|
||||
pci_write_config32(dev, 0x80, dword);
|
||||
dword = 0x00000000;
|
||||
pci_write_config32(dev, 0x80, dword);
|
||||
|
||||
dword = 0x00000d00;
|
||||
pci_write_config32(dev, 0x84, dword);
|
||||
dword = 0x00000d00;
|
||||
pci_write_config32(dev, 0x84, dword);
|
||||
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#
|
||||
*/ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_ck804, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_ck804, 0x1);
|
||||
|
@ -148,73 +150,73 @@ void *smp_write_config_table(void *v)
|
|||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_ck804, 0xf);
|
||||
|
||||
// Onboard ck804 smbus
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+1)<<2)|1, apicid_ck804, 0xa);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+1)<<2)|1, apicid_ck804, 0xa);
|
||||
// 10
|
||||
|
||||
// Onboard ck804 USB 1.1
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|0, apicid_ck804, 0x15); // 21
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|0, apicid_ck804, 0x15); // 21
|
||||
|
||||
// Onboard ck804 USB 2
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|1, apicid_ck804, 0x14); // 20
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|1, apicid_ck804, 0x14); // 20
|
||||
|
||||
// Onboard ck804 Audio
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+4)<<2)|0, apicid_ck804, 0x14); // 20
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+4)<<2)|0, apicid_ck804, 0x14); // 20
|
||||
|
||||
// Onboard ck804 SATA 0
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +7)<<2)|0, apicid_ck804, 0x17); // 23
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +7)<<2)|0, apicid_ck804, 0x17); // 23
|
||||
|
||||
// Onboard ck804 SATA 1
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +8)<<2)|0, apicid_ck804, 0x16); // 22
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +8)<<2)|0, apicid_ck804, 0x16); // 22
|
||||
|
||||
// Onboard ck804 NIC
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +0x0a)<<2)|0, apicid_ck804, 0x15); // 21
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +0x0a)<<2)|0, apicid_ck804, 0x15); // 21
|
||||
|
||||
//Slot 1 PCIE x16
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4);
|
||||
}
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4);
|
||||
}
|
||||
|
||||
//Onboard Firewire
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x05<<2)|0, apicid_ck804, 0x13); // 19
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x05<<2)|0, apicid_ck804, 0x13); // 19
|
||||
|
||||
//Slot 2 PCI 32
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|i, apicid_ck804, 0x10 + (0+i)%4);
|
||||
}
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|i, apicid_ck804, 0x10 + (0+i)%4);
|
||||
}
|
||||
|
||||
if(sysconf.pci1234[2] & 0xf) {
|
||||
//Onboard ck804b NIC
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_0, ((sbdnb+0x0a)<<2)|0, apicid_ck804b, 0x15);//24+4+4+21=53
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_0, ((sbdnb+0x0a)<<2)|0, apicid_ck804b, 0x15);//24+4+4+21=53
|
||||
|
||||
//Slot 3 PCIE x16
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|i, apicid_ck804b, 0x10 + (2+i+4-sbdnb%4)%4);
|
||||
}
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|i, apicid_ck804b, 0x10 + (2+i+4-sbdnb%4)%4);
|
||||
}
|
||||
}
|
||||
|
||||
//Channel B of 8131
|
||||
|
||||
//Slot 4 PCI-X 100/66
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4<<2)|i, apicid_8131_2, (0+i)%4);
|
||||
}
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4<<2)|i, apicid_8131_2, (0+i)%4);
|
||||
}
|
||||
|
||||
//Slot 5 PCIX 100/66
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|i, apicid_8131_2, (1+i)%4); // 29
|
||||
}
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|i, apicid_8131_2, (1+i)%4); // 29
|
||||
}
|
||||
|
||||
//OnBoard LSI SCSI
|
||||
for(i=0;i<2;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|i, apicid_8131_2, (2+i)%4); //30
|
||||
}
|
||||
for(i=0;i<2;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|i, apicid_8131_2, (2+i)%4); //30
|
||||
}
|
||||
|
||||
//Channel A of 8131
|
||||
|
||||
//Slot 6 PCIX 133/100/66
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|i, apicid_8131_1, (0+i)%4); //24
|
||||
}
|
||||
//Slot 6 PCIX 133/100/66
|
||||
for(i=0;i<4;i++) {
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|i, apicid_8131_1, (0+i)%4); //24
|
||||
}
|
||||
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
|
||||
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
|
||||
|
|
Loading…
Reference in New Issue