zero warnings days...

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5477 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/mainboard/asus/m2v-mx_se/romstage.c

@@ -57,7 +57,6 @@ unsigned int get_sbdn(unsigned bus);
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include "northbridge/amd/amdk8/early_ht.c"
@@ -83,10 +82,11 @@ static void activate_spd_rom(const struct mem_controller *ctrl)
 {
 }
 
-#define K8_4RANK_DIMM_SUPPORT 1
+// defines S3_NVRAM_EARLY:
-
 #include "southbridge/via/k8t890/k8t890_early_car.c"
 
+#define K8_4RANK_DIMM_SUPPORT 1
+
 #include "northbridge/amd/amdk8/amdk8.h"
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
@@ -164,7 +164,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	console_init();
 	enable_rom_decode();
 
-	print_info("now booting... real_main\n");
+	printk(BIOS_INFO, "now booting... \n");
 
 	if (bist == 0)
 		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
@@ -175,7 +175,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	setup_coherent_ht_domain();
 	wait_all_core0_started();
 
-	print_info("now booting... Core0 started\n");
+	printk(BIOS_INFO, "now booting... All core 0 started\n");
 
 #if CONFIG_LOGICAL_CPUS==1
 	/* It is said that we should start core1 after all core0 launched. */
@@ -196,12 +196,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	vt8237_early_spi_init();
 
 	if (needs_reset) {
-		print_debug_hex8(needs_reset);
+		printk(BIOS_DEBUG, "ht reset -\n");
-
-		print_debug("Xht reset -\n");
 		soft_reset();
-		print_debug("NO reset\n");
+		printk(BIOS_DEBUG, "FAILED!\n");
-
 	}
 
 	/* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */

src/mainboard/bcom/winnetp680/romstage.c

@@ -34,7 +34,6 @@
 #include "cpu/x86/bist.h"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
 #include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
 #include "superio/winbond/w83697hf/w83697hf_early_serial.c"
 #define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1)

src/mainboard/jetway/j7f24/romstage.c

@@ -34,7 +34,6 @@
 #include "cpu/x86/bist.h"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
 #include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
 #include "superio/fintek/f71805f/f71805f_early_serial.c"
 

src/mainboard/via/epia-cn/romstage.c

@@ -34,7 +34,6 @@
 #include "cpu/x86/bist.h"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
 #include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
 #include "southbridge/via/vt8235/vt8235_early_serial.c"
 

src/mainboard/via/pc2500e/romstage.c

@@ -35,7 +35,6 @@
 #include "cpu/x86/bist.h"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
 #include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
 #include "superio/ite/it8716f/it8716f_early_serial.c"
 

src/northbridge/amd/amdk8/raminit_f_dqs.c

@@ -1823,8 +1823,11 @@ static void set_sysinfo_in_ram(unsigned val)
 }
 
 #ifdef S3_NVRAM_EARLY
-int s3_save_nvram_early(u32 dword, int size, int  nvram_pos);
+// Don't define these prototypes as the real functions are already included
-int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
+// at this point.
+//
+//int s3_save_nvram_early(u32 dword, int size, int  nvram_pos);
+//int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
 #else
 static int s3_save_nvram_early(u32 dword, int size, int  nvram_pos)
 {

src/southbridge/via/k8t890/k8t890.h

@@ -38,14 +38,17 @@
 /* the FB size in MB (min is 8MB max is 512MB) */
 #define K8M890_FBSIZEMB		64
 
+#ifdef __PRE_RAM__
+u8 k8t890_early_setup_ht(void);
+#else
 #include <device/device.h>
-
 #if 0
 extern void writeback(struct device *dev, u16 where, u8 what);
 extern void dump_south(device_t dev);
 #endif
-#include <southbridge/via/vt8237r/vt8237r.h>
+#endif
 
+#include <southbridge/via/vt8237r/vt8237r.h>
 
 int k8m890_host_fb_size_get(void);
 //void k8m890_host_fb_direct_set(uint32_t fb_address);

src/southbridge/via/k8t890/k8t890_early_car.c

@@ -23,12 +23,12 @@
  */
 
 #include <stdlib.h>
-//include "k8t890.h"
+#include "k8t890.h"
-#warning hack the right header here
 
 /* The 256 bytes of NVRAM for S3 storage, 256B aligned */
 #define K8T890_NVRAM_IO_BASE	0xf00
 #define K8T890_MULTIPLE_FN_EN	0x4f
+
 /* we provide S3 NVRAM to system */
 #define S3_NVRAM_EARLY	1
 
@@ -113,7 +113,7 @@ u8 k8t890_early_setup_ht(void)
 	return 1;
 }
 
-int s3_save_nvram_early(u32 dword, int size, int  nvram_pos)
+static int s3_save_nvram_early(u32 dword, int size, int  nvram_pos)
 {
 	
 	printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos);
@@ -134,7 +134,7 @@ int s3_save_nvram_early(u32 dword, int size, int  nvram_pos)
 	return nvram_pos;
 }
 
-int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
+static int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
 {
 	switch (size) {
 	case 1:

src/southbridge/via/vt8237r/vt8237r.h

@@ -103,7 +103,18 @@ __attribute__ ((packed))
 #endif
 ;
 
-#ifndef __PRE_RAM__
+#ifdef __PRE_RAM__
+#ifndef __ROMCC__
+u8 smbus_read_byte(u8 dimm, u8 offset);
+void enable_smbus(void);
+void smbus_fixup(const struct mem_controller *ctrl);
+// these are in vt8237_early_smbus.c - do they really belong there?
+void vt8237_sb_enable_fid_vid(void);
+void enable_rom_decode(void);
+void vt8237_early_spi_init(void);
+int vt8237_early_network_init(struct vt8237_network_rom *rom);
+#endif
+#else
 #include <device/device.h>
 void writeback(struct device *dev, u16 where, u8 what);
 void dump_south(device_t dev);