remove more code
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2285 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Li-Ta Lo
parent
c1a4b2b0e5
commit
64f07fb21c
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@ -19,8 +19,6 @@
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* FIXME -- make this configurable
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*/
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#define RAMADJUSTMB 9
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/*
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*/
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/* todo: add a resource record. We don't do this here because this may be called when
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* very little of the platform is actually working.
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@ -52,191 +50,12 @@ sizeram(void)
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return sizem;
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}
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/* here is programming for the various MSRs.*/
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#define IM_QWAIT 0x100000
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#define DMCF_WRITE_SERIALIZE_REQUEST (2<<12) /* 2 outstanding */ /* in high */
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#define DMCF_SERIAL_LOAD_MISSES (2) /* enabled */
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/* these are the 8-bit attributes for controlling RCONF registers */
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#define CACHE_DISABLE (1<<0)
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#define WRITE_ALLOCATE (1<<1)
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#define WRITE_PROTECT (1<<2)
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#define WRITE_THROUGH (1<<3)
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#define WRITE_COMBINE (1<<4)
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#define WRITE_SERIALIZE (1<<5)
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/* ram has none of this stuff */
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#define RAM_PROPERTIES (0)
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#define DEVICE_PROPERTIES (WRITE_SERIALIZE|CACHE_DISABLE)
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#define ROM_PROPERTIES (WRITE_SERIALIZE|WRITE_THROUGH|CACHE_DISABLE)
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#define MSR_WS_CD_DEFAULT (0x21212121)
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/* 1810-1817 give you 8 registers with which to program protection regions */
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/* the are region configuration range registers, or RRCF */
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/* in msr terms, the are a straight base, top address assign, since they are 4k aligned. */
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/* so no left-shift needed for top or base */
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#define RRCF_LOW(base,properties) (base|(1<<8)|properties)
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#define RRCF_LOW_CD(base) RRCF_LOW(base, CACHE_DISABLE)
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/* build initializer for P2D MSR */
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#define P2D_BM(msr, pdid1, bizarro, pbase, pmask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(pbase>>24), .lo=(pbase<<8)|pmask}}
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#define P2D_BMO(msr, pdid1, bizarro, poffset, pbase, pmask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(poffset<<8)|(pbase>>24), .lo=(pbase<<8)|pmask}}
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#define P2D_R(msr, pdid1, bizarro, pmax, pmin) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(pmax>>12), .lo=(pmax<<20)|pmin}}
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#define P2D_RO(msr, pdid1, bizarro, poffset, pmax, pmin) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(poffset<<8)|(pmax>>12), .lo=(pmax<<20)|pmin}}
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#define P2D_SC(msr, pdid1, bizarro, wen, ren,pscbase) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(wen), .lo=(ren<<16)|(pscbase>>18)}}
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#define IOD_BM(msr, pdid1, bizarro, ibase, imask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(ibase>>12), .lo=(ibase<<20)|imask}}
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#define IOD_SC(msr, pdid1, bizarro, en, wen, ren, ibase) {msr, {.hi=(pdid1<<29)|(bizarro<<28), .lo=(en<<24)|(wen<<21)|(ren<<20)|(ibase<<3)}}
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struct msr_defaults {
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int msr_no;
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msr_t msr;
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} msr_defaults [] = {
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{0x1700, {.hi = 0, .lo = IM_QWAIT}},
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{0x1800, {.hi = DMCF_WRITE_SERIALIZE_REQUEST, .lo = DMCF_SERIAL_LOAD_MISSES}},
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/* 1808 will be done down below, so we have to do 180a->1817 (well, 1813 really) */
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/* for 180a, for now, we assume VSM will configure it */
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/* 180b is left at reset value,a0000-bffff is non-cacheable */
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/* 180c, c0000-dffff is set to write serialize and non-cachable */
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/* oops, 180c will be set by cpu bug handling in cpubug.c */
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//{0x180c, {.hi = MSR_WS_CD_DEFAULT, .lo = MSR_WS_CD_DEFAULT}},
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/* 180d is left at default, e0000-fffff is non-cached */
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/* we will assume 180e, the ssm region configuration, is left at default or set by VSM */
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/* we will not set 0x180f, the DMM,yet */
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//{0x1810, {.hi=0xee7ff000, .lo=RRCF_LOW(0xee000000, WRITE_COMBINE|CACHE_DISABLE)}},
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//{0x1811, {.hi = 0xefffb000, .lo = RRCF_LOW_CD(0xefff8000)}},
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//{0x1812, {.hi = 0xefff7000, .lo = RRCF_LOW_CD(0xefff4000)}},
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//{0x1813, {.hi = 0xefff3000, .lo = RRCF_LOW_CD(0xefff0000)}},
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/* now for GLPCI routing */
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/* GLIU0 */
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P2D_BM(0x10000020, 0x1, 0x0, 0x0, 0xfff80),
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P2D_BM(0x10000021, 0x1, 0x0, 0x80000, 0xfffe0),
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P2D_SC(0x1000002c, 0x1, 0x0, 0x0, 0xff03, 0x3),
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/* GLIU1 */
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P2D_BM(0x40000020, 0x1, 0x0, 0x0, 0xfff80),
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P2D_BM(0x40000021, 0x1, 0x0, 0x80000, 0xfffe0),
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P2D_SC(0x4000002d, 0x1, 0x0, 0x0, 0xff03, 0x3),
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{0}
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};
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static int
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setup_gx2_cache(void)
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{
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msr_t msr;
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unsigned long long val;
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int sizembytes, sizereg;
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sizembytes = sizeram();
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#ifdef NO
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printk_debug("enable_cache: enable for %dm bytes\n", sizembytes);
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/* build up the rconf word. */
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/* the SYSTOP bits 27:8 are actually the top bits from 31:12. Book fails to say that */
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/* set romrp */
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val = ((unsigned long long) ROM_PROPERTIES) << 56;
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/* make rom base useful for 1M roms */
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/* Flash base address -- sized for 1/2M for now*/
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val |= ((unsigned long long) 0xfff800)<<36;
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/* set the devrp properties */
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val |= ((unsigned long long) DEVICE_PROPERTIES) << 28;
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/* sigh. Take our TOM, RIGHT shift 12, since it page-aligned, then LEFT-shift 8 for reg. */
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/* yank off 8M for frame buffer and 1M for VSA */
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sizembytes -= RAMADJUSTMB;
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sizereg = sizembytes;
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sizereg *= 0x100000;
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sizereg >>= 12;
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sizereg <<= 8;
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val |= sizereg;
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val |= RAM_PROPERTIES;
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msr.lo = val;
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msr.hi = (val >> 32);
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printk_debug("msr will be set to %x:%x\n", msr.hi, msr.lo);
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wrmsr(CPU_RCONF_DEFAULT, msr);
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#endif
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enable_cache();
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wbinvd();
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return sizembytes;
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}
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#define SMM_OFFSET 0x40400000
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#define SMM_SIZE 256
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/* we have to do this here. We have not found a nicer way to do it */
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void
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setup_gx2(void)
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{
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int i;
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unsigned long tmp, tmp2, tmp3;
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msr_t msr;
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unsigned long sizem, membytes;
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sizem = setup_gx2_cache();
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membytes = sizem * 1048576;
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#if 0
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/* we need to set 0x10000028 and 0x40000029 */
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printk_debug("sizem 0x%x, membytes 0x%x\n", sizem, membytes);
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msr.hi = 0x20000000 | membytes>>24;
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msr.lo = 0x100 | ( ((membytes >>12) & 0xfff) << 20);
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wrmsr(0x10000028, msr);
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msr.hi = 0x20000000 | membytes>>24;
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msr.lo = 0x100 | ( ((membytes >>12) & 0xfff) << 20);
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wrmsr(0x40000029, msr);
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msr = rdmsr(0x10000028);
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printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000028, msr.hi,msr.lo);
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msr = rdmsr(0x40000029);
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printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x40000029, msr.hi,msr.lo);
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/* fixme: SMM MSR 0x10000026 and 0x400000023 */
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/* calculate the OFFSET field */
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tmp = membytes - SMM_OFFSET;
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tmp >>= 12;
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tmp <<= 8;
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tmp |= 0x20000000;
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tmp |= (SMM_OFFSET >> 24);
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/* calculate the PBASE and PMASK fields */
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tmp2 = (SMM_OFFSET << 8) & 0xFFF00000; /* shift right 12 then left 20 == left 8 */
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tmp2 |= (((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff);
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printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000026, tmp, tmp2);
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msr.hi = tmp;
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msr.lo = tmp2;
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wrmsr(0x10000026, msr);
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#else
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msr.hi = 0x2000000f;
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msr.lo = 0xfbf00100;
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wrmsr(0x10000028, msr);
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msr = rdmsr(0x10000028);
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printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000028, msr.hi, msr.lo);
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wrmsr(0x40000029, msr);
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msr = rdmsr(0x40000029);
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printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x40000029, msr.hi, msr.lo);
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msr.hi = 0x2cfbc040;
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msr.lo = 0x400fffc0;
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wrmsr(0x10000026, msr);
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msr = rdmsr(0x10000026);
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printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000026, msr.hi, msr.lo);
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msr.hi = 0x22fffc02;
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msr.lo = 0x10ffbf00;
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wrmsr(0x1808, msr);
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msr = rdmsr(0x1808);
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printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x1808, msr.hi, msr.lo);
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#endif
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/* now do the default MSR values */
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for(i = 0; msr_defaults[i].msr_no; i++) {
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msr_t msr;
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wrmsr(msr_defaults[i].msr_no, msr_defaults[i].msr);
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msr = rdmsr(msr_defaults[i].msr_no);
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printk_debug("MSR 0x%x is now 0x%x:0x%x\n", msr_defaults[i].msr_no, msr.hi,msr.lo);
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}
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}
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static void enable_shadow(device_t dev)
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{
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@ -418,7 +237,6 @@ static void enable_dev(struct device *dev)
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northbridgeinit();
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cpubug();
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chipsetinit();
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//setup_gx2();
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setup_gx2_cache();
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/* do this here for now -- this chip really breaks our device model */
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setup_realmode_idt();
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@ -22,27 +22,39 @@ struct gliutable {
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};
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struct gliutable gliu0table[] = {
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{.desc_name=MSR_GLIU0_BASE1, .desc_type= BM,.hi= MSR_MC + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC*/
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{.desc_name=MSR_GLIU0_BASE2, .desc_type= BM,.hi= MSR_MC + 0x0,.lo=(0x80 << 20) + 0x0FFFE0}, /* 80000-9ffff to Mc*/
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{.desc_name=MSR_GLIU0_SHADOW,.desc_type= SC_SHADOW,.hi= MSR_MC + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) A0000-Bffff handled by SoftVideo*/
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{.desc_name=MSR_GLIU0_SYSMEM,.desc_type= R_SYSMEM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly.*/
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{.desc_name=MSR_GLIU0_DMM, .desc_type= BMO_DMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly.*/
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{.desc_name=MSR_GLIU0_SMM, .desc_type= BMO_SMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly.*/
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{.desc_name=GLIU0_GLD_MSR_COH,.desc_type= OTHER,.hi= 0x0,.lo= GL0_CPU},
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{.desc_name=GL_END, .desc_type= GL_END,.hi= 0x0,.lo= 0x0},
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/* 0x00000-0x7FFFF to MC */
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{.desc_name = MSR_GLIU0_BASE1, .desc_type = BM, .hi = MSR_MC + 0x0,.lo = 0xFFF80},
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/* 0x80000-0x9ffff to Mc */
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{.desc_name = MSR_GLIU0_BASE2, .desc_type = BM, .hi = MSR_MC + 0x0,.lo = (0x80 << 20) + 0xFFFE0},
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/* 0xc0000-0xfffff split to MC and PCI (sub decode) A0000-Bffff handled by SoftVideo */
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{.desc_name = MSR_GLIU0_SHADOW, .desc_type = SC_SHADOW,.hi = MSR_MC + 0x0,.lo= 0x03},
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/* Catch and fix dynamicly.*/
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{.desc_name = MSR_GLIU0_SYSMEM, .desc_type = R_SYSMEM, .hi = MSR_MC, .lo= 0x0},
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/* Catch and fix dynamicly.*/
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{.desc_name = MSR_GLIU0_DMM, .desc_type = BMO_DMM, .hi = MSR_MC,.lo = 0x0},
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/* Catch and fix dynamicly.*/
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{.desc_name = MSR_GLIU0_SMM, .desc_type = BMO_SMM, .hi = MSR_MC,.lo = 0x0},
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{.desc_name = GLIU0_GLD_MSR_COH,.desc_type = OTHER, .hi = 0x0, .lo = GL0_CPU},
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{.desc_name = GL_END, .desc_type = GL_END, .hi = 0x0, .lo = 0x0},
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};
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struct gliutable gliu1table[] = {
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{.desc_name=MSR_GLIU1_BASE1,.desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC*/
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{.desc_name=MSR_GLIU1_BASE2,.desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= (0x80 << 20) +0x0FFFE0}, /* 80000-9ffff to Mc*/
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{.desc_name=MSR_GLIU1_SHADOW,.desc_type= SC_SHADOW,.hi= MSR_GL0 + 0x0,.lo= 0x03},/* C0000-Fffff split to MC and PCI (sub decode)*/
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{.desc_name=MSR_GLIU1_SYSMEM,.desc_type= R_SYSMEM,.hi= MSR_GL0,.lo= 0x0}, /* Cat0xc and fix dynamicly.*/
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{.desc_name=MSR_GLIU1_DMM,.desc_type= BM_DMM,.hi= MSR_GL0,.lo= 0x0}, /* Cat0xc and fix dynamicly.*/
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{.desc_name=MSR_GLIU1_SMM,.desc_type= BM_SMM,.hi= MSR_GL0,.lo= 0x0}, /* Cat0xc and fix dynamicly.*/
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{.desc_name=GLIU1_GLD_MSR_COH,.desc_type= OTHER,.hi= 0x0,.lo= GL1_GLIU0},
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{.desc_name=MSR_GLIU1_FPU_TRAP,.desc_type= SCIO,.hi= (GL1_GLCP << 29) + 0x0,.lo= 0x033000F0}, /* FooGlue FPU 0xF0*/
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{.desc_name=GL_END,.desc_type= GL_END,.hi= 0x0,.lo= 0x0},
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/* 0x00000-0x7FFFF to GLIU0 */
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{.desc_name = MSR_GLIU1_BASE1, .desc_type = BM, .hi = MSR_GL0 + 0x0,.lo= 0x0FFF80},
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/* 0x80000-0x9ffff to GLIU0 */
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{.desc_name = MSR_GLIU1_BASE2, .desc_type = BM, .hi = MSR_GL0 + 0x0,.lo= (0x80 << 20) +0x0FFFE0},
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/* 0xc0000-0xfffff split to MC and PCI (sub decode) A0000-Bffff handled by SoftVideo */
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{.desc_name = MSR_GLIU1_SHADOW,.desc_type= SC_SHADOW,.hi= MSR_GL0 + 0x0,.lo= 0x03},
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/* Cat0xc and fix dynamicly.*/
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{.desc_name = MSR_GLIU1_SYSMEM,. desc_type = R_SYSMEM,.hi= MSR_GL0,.lo= 0x0},
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/* Cat0xc and fix dynamicly.*/
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{.desc_name = MSR_GLIU1_DMM,.desc_type= BM_DMM,.hi= MSR_GL0,.lo= 0x0},
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/* Cat0xc and fix dynamicly.*/
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{.desc_name = MSR_GLIU1_SMM,.desc_type= BM_SMM,.hi= MSR_GL0,.lo= 0x0},
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{.desc_name = GLIU1_GLD_MSR_COH,.desc_type= OTHER,.hi= 0x0,.lo= GL1_GLIU0},
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/* FooGlue FPU 0xF0*/
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{.desc_name = MSR_GLIU1_FPU_TRAP,.desc_type= SCIO,.hi= (GL1_GLCP << 29) + 0x0,.lo= 0x033000F0},
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{.desc_name = GL_END,.desc_type= GL_END,.hi= 0x0,.lo= 0x0},
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};
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struct gliutable *gliutables[] = {gliu0table, gliu1table, 0};
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@ -258,8 +270,8 @@ SMMGL1Init(struct gliutable *gl) {
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}
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static void
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GLIUInit(struct gliutable *gl){
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GLIUInit(struct gliutable *gl)
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{
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while (gl->desc_type != GL_END){
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switch(gl->desc_type){
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default:
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@ -51,6 +51,8 @@ struct msr_defaults {
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int msr_no;
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unsigned long hi, lo;
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};
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const struct msr_defaults msr_defaults [] = {
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{0x1700, .hi = 0, .lo = IM_QWAIT},
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{0x1800, .hi = DMCF_WRITE_SERIALIZE_REQUEST, .lo = DMCF_SERIAL_LOAD_MISSES},
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@ -95,10 +97,7 @@ const struct msr_defaults msr_defaults [] = {
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#define SMM_OFFSET 0x40400000
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#define SMM_SIZE 256
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/*
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* FixME: MSR 0x10000028, 0x40000029 are reprogrammed by SysmemInit()
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* 0x10000026 and 0x400000023 are reprogrammed by SMMGL0Init() and SMMGL1Init()
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*/
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void
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setup_gx2(void)
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{
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@ -165,12 +164,12 @@ setup_gx2(void)
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wrmsr(msr_defaults[0].msr_no, msr);
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for(i = 0; msr_defaults[i].msr_no; i++) {
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// msr_t msr;
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//msr_t msr;
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msr.lo = msr_defaults[i].lo;
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msr.hi = msr_defaults[i].hi;
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wrmsr(msr_defaults[i].msr_no, msr);
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//msr = rdmsr(msr_defaults[i].msr_no);
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// print_debug("MSR 0x%x is now 0x%x:0x%x\n", msr_defaults[i].msr_no, msr.hi,msr.lo);
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//print_debug("MSR 0x%x is now 0x%x:0x%x\n", msr_defaults[i].msr_no, msr.hi,msr.lo);
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}
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}
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