code cleanup, comments added
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2284 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Li-Ta Lo
parent
b947b14734
commit
c1a4b2b0e5
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@ -9,7 +9,8 @@
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/* **/
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/* ***************************************************************************/
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static void
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BIST(void){
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BIST(void)
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{
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int msrnum;
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msr_t msr;
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@ -24,8 +25,8 @@ BIST(void){
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msrnum = CPU_DM_BIST;
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wrmsr(msrnum, msr);
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outb(POST_CPU_DM_BIST_FAILURE , 0x80); /* 0x29*/
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msr = rdmsr(msrnum); /* read back for pass fail*/
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outb(POST_CPU_DM_BIST_FAILURE, 0x80); /* 0x29*/
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msr = rdmsr(msrnum); /* read back for pass fail*/
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msr.lo &= 0x0F3FF0000;
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if (msr.lo != 0xfeff0000)
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goto BISTFail;
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@ -41,108 +42,115 @@ BIST(void){
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msrnum = CPU_FP_UROM_BIST;
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wrmsr(msrnum, msr);
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outb(POST_CPU_FPU_BIST_FAILURE, 0x80); /* 0x89*/
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inb(0x80); /* IO delay*/
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msr = rdmsr(msrnum); /* read back for pass fail*/
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outb(POST_CPU_FPU_BIST_FAILURE, 0x80); /* 0x89*/
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inb(0x80); /* IO delay*/
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msr = rdmsr(msrnum); /* read back for pass fail*/
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while ((msr.lo&0x884) != 0x884)
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msr = rdmsr(msrnum); /* Endless loop if BIST is broken*/
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msr = rdmsr(msrnum); /* Endless loop if BIST is broken*/
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if ((msr.lo&0x642) != 0x642)
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goto BISTFail;
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msr.lo = msr.hi = 0; /* clear FPU BIST bits*/
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msr.lo = msr.hi = 0; /* clear FPU BIST bits*/
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msrnum = CPU_FP_UROM_BIST;
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wrmsr(msrnum, msr);
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/* BTB*/
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msr.lo = 0x000000303;
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msr.hi = 0x000000000;
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msrnum = CPU_PF_BTBRMA_BIST;
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wrmsr(msrnum, msr);
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outb(POST_CPU_BTB_BIST_FAILURE , 0x80); /* 0x8A*/
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msr = rdmsr(msrnum); /* read back for pass fail*/
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outb(POST_CPU_BTB_BIST_FAILURE, 0x80); /* 0x8A*/
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msr = rdmsr(msrnum); /* read back for pass fail*/
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if ((msr.lo & 0x3030) != 0x3030)
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goto BISTFail;
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return;
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BISTFail:
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print_err("BIST failed!\n");
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while(1);
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}
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void BTM_enable(void)
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{
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int msrnum;
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msr_t msr;
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/* Set Diagnostic Mode */
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msrnum = CPU_GLD_MSR_DIAG;
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msr.hi = 0;
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msr.lo = DIAG_SEL1_SET | DIAG_SET0_SET;
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wrmsr(msrnum, msr);
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/* Set up GLCP to grab BTM data.*/
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msrnum = 0x04C00000C; /* GLCP_DBGOUT MSR*/
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msr.hi = 0x0;
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msr.lo = 0x08; /* reset value (SCOPE_SEL = 0) causes FIFO toshift out,*/
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wrmsr(msrnum, msr); /* exchange it to anything else to prevent this*/
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/* ;Turn off debug clock*/
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msrnum = 0x04C000016; /* DBG_CLK_CTL*/
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msr.lo = 0x00; /* No clock*/
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msr.hi = 0x00;
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wrmsr(msrnum, msr);
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/* ;Set debug clock to CPU*/
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msrnum = 0x04C000016; /* DBG_CLK_CTL*/
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msr.lo = 0x01; /* CPU CLOCK*/
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msr.hi = 0x00;
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wrmsr(msrnum, msr);
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/* ;Set fifo ctl to BTM bits wide*/
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msrnum = 0x04C00005E; /* FIFO_CTL*/
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msr.lo = 0x003880000; /* Bit [25:24] are size (11=BTM, 10 = 64 bit,
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* 01= 32 bit, 00 = 16bit),
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* Bit [23:21] are position (100 = CPU downto0)*/
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wrmsr(msrnum, msr); /* */
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/* Bit [19] sets it up in slow data mode.*/
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/* ;enable fifo loading - BTM sizing will constrain*/
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/* ; only valid BTM packets to load - this action should always be on*/
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msrnum = 0x04C00006F; /* GLCP ACTION7 - load fifo*/
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msr.lo = 0x00000F000; /* Any nibble all 1's will always trigger*/
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msr.hi = 0x000000000; /* */
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wrmsr(msrnum, msr);
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/* ;start storing diag data in the fifo*/
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msrnum = 0x04C00005F; /* DIAG CTL*/
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msr.lo = 0x080000000; /* enable actions*/
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msr.hi = 0x000000000;
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wrmsr(msrnum, msr);
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/* Set up delay on data lines, so that the hold time*/
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/* is 1 ns.*/
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msrnum = 0x04C00000D ; /* GLCP IO DELAY CONTROLS*/
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msr.lo = 0x082b5ad68;
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msr.hi = 0x080ad6b57; /* RGB delay = 0x07*/
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wrmsr(msrnum, msr);
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/* Set up DF to output diag information on DF pins.*/
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msrnum = DF_GLD_MSR_MASTER_CONF;
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msr.lo = 0x0220;
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msr.hi = 0;
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wrmsr(msrnum, msr);
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msrnum = 0x04C00000C ; /* GLCP_DBGOUT MSR*/
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msr.hi = 0x0;
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msr.lo = 0x0; /* reset value (SCOPE_SEL = 0) causes FIFO to shift out,*/
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wrmsr(msrnum, msr);
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/* end of code for BTM */
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}
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/* ***************************************************************************/
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/* * cpuRegInit*/
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/* ***************************************************************************/
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void
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cpuRegInit (void){
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cpuRegInit (void)
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{
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int msrnum;
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msr_t msr;
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/* Turn on BTM for early debug based on setup. */
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/*if (getnvram( TOKEN_BTM_DIAG_MODE) & 3) {*/
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{
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/* Set Diagnostic Mode */
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msrnum = CPU_GLD_MSR_DIAG;
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msr.hi = 0;
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msr.lo = DIAG_SEL1_SET | DIAG_SET0_SET;
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wrmsr(msrnum, msr);
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/* Set up GLCP to grab BTM data.*/
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msrnum = 0x04C00000C; /* GLCP_DBGOUT MSR*/
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msr.hi = 0x0;
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msr.lo = 0x08; /* reset value (SCOPE_SEL = 0) causes FIFO toshift out,*/
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wrmsr(msrnum, msr); /* exchange it to anything else to prevent this*/
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/* ;Turn off debug clock*/
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msrnum = 0x04C000016; /* DBG_CLK_CTL*/
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msr.lo = 0x00; /* No clock*/
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msr.hi = 0x00;
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wrmsr(msrnum, msr);
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/* ;Set debug clock to CPU*/
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msrnum = 0x04C000016; /* DBG_CLK_CTL*/
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msr.lo = 0x01; /* CPU CLOCK*/
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msr.hi = 0x00;
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wrmsr(msrnum, msr);
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/* ;Set fifo ctl to BTM bits wide*/
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msrnum = 0x04C00005E; /* FIFO_CTL*/
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msr.lo = 0x003880000; /* Bit [25:24] are size (11=BTM, 10 = 64 bit, 01= 32 bit, 00 = 16bit)*/
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wrmsr(msrnum, msr); /* Bit [23:21] are position (100 = CPU downto0)*/
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/* Bit [19] sets it up in slow data mode.*/
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/* ;enable fifo loading - BTM sizing will constrain*/
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/* ; only valid BTM packets to load - this action should always be on*/
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msrnum = 0x04C00006F; /* GLCP ACTION7 - load fifo*/
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msr.lo = 0x00000F000; /* Any nibble all 1's will always trigger*/
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msr.hi = 0x000000000; /* */
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wrmsr(msrnum, msr);
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/* ;start storing diag data in the fifo*/
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msrnum = 0x04C00005F; /* DIAG CTL*/
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msr.lo = 0x080000000; /* enable actions*/
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msr.hi = 0x000000000;
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wrmsr(msrnum, msr);
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/* Set up delay on data lines, so that the hold time*/
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/* is 1 ns.*/
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msrnum = 0x04C00000D ; /* GLCP IO DELAY CONTROLS*/
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msr.lo = 0x082b5ad68;
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msr.hi = 0x080ad6b57; /* RGB delay = 0x07*/
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wrmsr(msrnum, msr);
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/* Set up DF to output diag information on DF pins.*/
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msrnum = DF_GLD_MSR_MASTER_CONF;
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msr.lo = 0x0220;
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msr.hi = 0;
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wrmsr(msrnum, msr);
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msrnum = 0x04C00000C ; /* GLCP_DBGOUT MSR*/
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msr.hi = 0x0;
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msr.lo = 0x0; /* reset value (SCOPE_SEL = 0) causes FIFO to shift out,*/
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wrmsr(msrnum, msr);
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/* end of code for BTM */
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BTM_enable();
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}
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/* Enable Suspend on Halt*/
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@ -164,49 +172,32 @@ cpuRegInit (void){
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msr.lo = 0x00000603C;
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wrmsr(msrnum, msr);
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/* Only do this if we are building for 5535*/
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/* */
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/* FooGlue Setup*/
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/* */
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#if 1
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/* Enable CIS mode B in FooGlue*/
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/* Enable CIS mode C */
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msrnum = MSR_FG + 0x10;
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msr = rdmsr(msrnum);
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msr.lo &= ~3;
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msr.lo |= 2; /* ModeB*/
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msr.lo |= 2;
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wrmsr(msrnum, msr);
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#endif
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/* */
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/* Disable DOT PLL. Graphics init will enable it if needed.*/
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/* */
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/* Disable DOT PLL. Graphics init will enable it if needed.*/
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msrnum = GLCP_DOTPLL;
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msr = rdmsr(msrnum);
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msr.lo |= DOTPPL_LOWER_PD_SET;
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wrmsr(msrnum, msr);
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/* */
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/* Enable RSDC*/
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/* */
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/* Enable RSDC and other SMM instructions */
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msrnum = 0x1301 ;
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msr = rdmsr(msrnum);
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msr.lo |= 0x08;
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wrmsr(msrnum, msr);
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/* */
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/* BIST*/
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/* */
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/* BIST*/
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/*if (getnvram( TOKEN_BIST_ENABLE) & == TVALUE_DISABLE) {*/
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{
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// BIST();
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//BIST();
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}
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/* */
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/* Enable BTB*/
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/* */
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/* Enable BTB*/
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/* I hate to put this check here but it doesn't really work in cpubug.asm*/
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msrnum = MSR_GLCP+0x17;
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msr = rdmsr(msrnum);
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@ -217,9 +208,7 @@ cpuRegInit (void){
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wrmsr(msrnum, msr);
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}
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/* */
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/* FPU impercise exceptions bit*/
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/* */
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/* FPU impercise exceptions bit*/
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/*if (getnvram( TOKEN_FPU_IE_ENABLE) != TVALUE_DISABLE) {*/
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{
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msrnum = CPU_FPU_MSR_MODE;
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@ -228,9 +217,7 @@ cpuRegInit (void){
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wrmsr(msrnum, msr);
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}
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/* */
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/* Cache Overides*/
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/* */
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/* Cache Overides*/
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/* Allow NVRam to override DM Setup*/
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/*if (getnvram( TOKEN_CACHE_DM_MODE) != 1) {*/
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{
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@ -250,9 +237,6 @@ cpuRegInit (void){
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}
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}
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/* ***************************************************************************/
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/* **/
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/* * MTestPinCheckBX*/
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@ -262,7 +246,8 @@ cpuRegInit (void){
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/* **/
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/* ***************************************************************************/
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static void
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MTestPinCheckBX (void){
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MTestPinCheckBX (void)
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{
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int msrnum;
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msr_t msr;
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@ -12,6 +12,7 @@ static void vsm_end_post_smi(void)
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__asm__ volatile (
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"push %ax\n"
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"mov $0x5000, %ax\n"
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/* smint */
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".byte 0x0f, 0x38\n"
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"pop %ax\n"
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);
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@ -24,9 +25,7 @@ static void model_gx2_init(device_t dev)
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/* Turn on caching if we haven't already */
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x86_enable_cache();
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/* Enable the local cpu apics */
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//setup_lapic();
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/* send SYS_END_OF_POST to VSM */
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vsm_end_post_smi();
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printk_debug("model_gx2_init DONE\n");
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@ -1,20 +1,13 @@
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/* ***************************************************************************/
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/* **/
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/* * StartTimer1*/
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/* **/
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/* * Entry: none*/
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/* * Exit: Starts Timer 1 for port 61 use*/
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/* * Destroys: Al,*/
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/* **/
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/* ***************************************************************************/
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void
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StartTimer1(void){
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StartTimer1(void)
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{
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outb(0x56, 0x43);
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outb(0x12, 0x41);
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}
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void
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SystemPreInit(void){
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SystemPreInit(void)
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{
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/* they want a jump ... */
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__asm__("jmp .+2\ninvd\njmp.+2\n");
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@ -469,18 +469,18 @@
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/* This is chip specific!*/
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#define MSR_GLIU0_BASE1 (MSR_GLIU0 + 0x20) /* BM*/
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#define MSR_GLIU0_BASE2 (MSR_GLIU0 + 0x21) /* BM*/
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#define MSR_GLIU0_SHADOW (MSR_GLIU0 + 0x2C) /* SCO should only be SC*/
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#define MSR_GLIU0_SYSMEM (MSR_GLIU0 + 0x28) /* RO should only be R*/
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#define MSR_GLIU0_SHADOW (MSR_GLIU0 + 0x2C) /* SCO should only be SC*/
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#define MSR_GLIU0_SYSMEM (MSR_GLIU0 + 0x28) /* RO should only be R*/
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#define MSR_GLIU0_SMM (MSR_GLIU0 + 0x26) /* BMO*/
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#define MSR_GLIU0_DMM (MSR_GLIU0 + 0x27) /* BMO*/
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#define MSR_GLIU1_BASE1 (MSR_GLIU1 + 0x20) /* BM*/
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#define MSR_GLIU1_BASE2 (MSR_GLIU1 + 0x21) /* BM*/
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#define MSR_GLIU1_SHADOW (MSR_GLIU1 + 0x2D) /* SCO should only be SC*/
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#define MSR_GLIU1_SYSMEM (MSR_GLIU1 + 0x29) /* RO should only be R*/
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#define MSR_GLIU1_SHADOW (MSR_GLIU1 + 0x2D) /* SCO should only be SC*/
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#define MSR_GLIU1_SYSMEM (MSR_GLIU1 + 0x29) /* RO should only be R*/
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#define MSR_GLIU1_SMM (MSR_GLIU1 + 0x23) /* BM*/
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#define MSR_GLIU1_DMM (MSR_GLIU1 + 0x24) /* BM*/
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#define MSR_GLIU1_FPU_TRAP (MSR_GLIU1 + 0x0E3) /* FooGlue F0 for FPU*/
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#define MSR_GLIU1_FPU_TRAP (MSR_GLIU1 + 0x0E3) /* FooGlue F0 for FPU*/
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/* definitions that are "once you are mostly up, start VSA" type things */
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#define SMM_OFFSET 0x40400000
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@ -239,8 +239,7 @@ setup_gx2(void)
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}
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static void enable_shadow(device_t dev)
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{
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{
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}
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static void northbridge_init(device_t dev)
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@ -263,11 +263,10 @@ GLIUInit(struct gliutable *gl){
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while (gl->desc_type != GL_END){
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switch(gl->desc_type){
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default:
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printk_err("%s: name %x, type %x, hi %x, lo %x: unsupported type: ", __FUNCTION__,
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gl->desc_name, gl->desc_type, gl->hi, gl->hi);
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printk_err("Must be %x, %x, %x, %x, %x, or %x\n", SC_SHADOW,R_SYSMEM,BMO_DMM,
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BM_DMM, BMO_SMM,BM_SMM);
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printk_err("%s: name %x, type %x, hi %x, lo %x: unsupported type: ",
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__FUNCTION__, gl->desc_name, gl->desc_type, gl->hi, gl->hi);
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printk_err("Must be %x, %x, %x, %x, %x, or %x\n",
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SC_SHADOW,R_SYSMEM,BMO_DMM, BM_DMM, BMO_SMM,BM_SMM);
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case SC_SHADOW: /* Check for a Shadow entry*/
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ShadowInit(gl);
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break;
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@ -276,7 +275,7 @@ GLIUInit(struct gliutable *gl){
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SysmemInit(gl);
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break;
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case BMO_DMM: /* check for a DMM entry*/
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case BMO_DMM: /* check for a DMM entry*/
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DMMGL0Init(gl);
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break;
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@ -32,15 +32,20 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
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#define RRCF_LOW_CD(base) RRCF_LOW(base, CACHE_DISABLE)
|
||||
|
||||
/* build initializer for P2D MSR */
|
||||
#define P2D_BM(msr, pdid1, bizarro, pbase, pmask) {msr, .hi=(pdid1<<29)|(bizarro<<28)|(pbase>>24), .lo=(pbase<<8)|pmask}
|
||||
#define P2D_BMO(msr, pdid1, bizarro, poffset, pbase, pmask) {msr, .hi=(pdid1<<29)|(bizarro<<28)|(poffset<<8)|(pbase>>24), .lo=(pbase<<8)|pmask}
|
||||
#define P2D_R(msr, pdid1, bizarro, pmax, pmin) {msr, .hi=(pdid1<<29)|(bizarro<<28)|(pmax>>12), .lo=(pmax<<20)|pmin}
|
||||
#define P2D_RO(msr, pdid1, bizarro, poffset, pmax, pmin) {msr, .hi=(pdid1<<29)|(bizarro<<28)|(poffset<<8)|(pmax>>12), .lo=(pmax<<20)|pmin}
|
||||
#define P2D_SC(msr, pdid1, bizarro, wen, ren,pscbase) {msr, .hi=(pdid1<<29)|(bizarro<<28)|(wen), .lo=(ren<<16)|(pscbase>>18)}
|
||||
#define IOD_BM(msr, pdid1, bizarro, ibase, imask) {msr, .hi=(pdid1<<29)|(bizarro<<28)|(ibase>>12), .lo=(ibase<<20)|imask}
|
||||
#define IOD_SC(msr, pdid1, bizarro, en, wen, ren, ibase) {msr, .hi=(pdid1<<29)|(bizarro<<28), .lo=(en<<24)|(wen<<21)|(ren<<20)|(ibase<<3)}
|
||||
|
||||
|
||||
#define P2D_BM(msr, pdid1, bizarro, pbase, pmask) \
|
||||
{msr, .hi=(pdid1<<29)|(bizarro<<28)|(pbase>>24), .lo=(pbase<<8)|pmask}
|
||||
#define P2D_BMO(msr, pdid1, bizarro, poffset, pbase, pmask) \
|
||||
{msr, .hi=(pdid1<<29)|(bizarro<<28)|(poffset<<8)|(pbase>>24), .lo=(pbase<<8)|pmask}
|
||||
#define P2D_R(msr, pdid1, bizarro, pmax, pmin) \
|
||||
{msr, .hi=(pdid1<<29)|(bizarro<<28)|(pmax>>12), .lo=(pmax<<20)|pmin}
|
||||
#define P2D_RO(msr, pdid1, bizarro, poffset, pmax, pmin) \
|
||||
{msr, .hi=(pdid1<<29)|(bizarro<<28)|(poffset<<8)|(pmax>>12), .lo=(pmax<<20)|pmin}
|
||||
#define P2D_SC(msr, pdid1, bizarro, wen, ren,pscbase) \
|
||||
{msr, .hi=(pdid1<<29)|(bizarro<<28)|(wen), .lo=(ren<<16)|(pscbase>>18)}
|
||||
#define IOD_BM(msr, pdid1, bizarro, ibase, imask) \
|
||||
{msr, .hi=(pdid1<<29)|(bizarro<<28)|(ibase>>12), .lo=(ibase<<20)|imask}
|
||||
#define IOD_SC(msr, pdid1, bizarro, en, wen, ren, ibase) \
|
||||
{msr, .hi=(pdid1<<29)|(bizarro<<28), .lo=(en<<24)|(wen<<21)|(ren<<20)|(ibase<<3)}
|
||||
|
||||
struct msr_defaults {
|
||||
int msr_no;
|
||||
|
|
@ -63,22 +68,37 @@ const struct msr_defaults msr_defaults [] = {
|
|||
//{0x1811, .hi = 0xefffb000, .lo = RRCF_LOW_CD(0xefff8000)},
|
||||
//{0x1812, .hi = 0xefff7000, .lo = RRCF_LOW_CD(0xefff4000)},
|
||||
//{0x1813, .hi = 0xefff3000, .lo = RRCF_LOW_CD(0xefff0000)},
|
||||
/* now for GLPCI routing */
|
||||
|
||||
/* GeodeLink Routing */
|
||||
/* GLIU0 */
|
||||
P2D_BM(0x10000020, 0x1, 0x0, 0x0, 0xfff80),
|
||||
/* Traditional Memory 0kB-512kB goes to GLIU port 1, Memory Controller */
|
||||
P2D_BM(0x10000020, 0x1, 0x0, 0x00000, 0xfff80),
|
||||
/* Traditional Memory 512kB-1MB goes to GLIU port 1, Memory Controller */
|
||||
P2D_BM(0x10000021, 0x1, 0x0, 0x80000, 0xfffe0),
|
||||
P2D_SC(0x1000002c, 0x1, 0x0, 0x0, 0xff03, 0x3),
|
||||
/* Extended Memory, 0xC0000-0x100000, disable write,
|
||||
* enable read 0xC0000 - 0xC8000, 0xE0000-0xFFFFF ,
|
||||
* goest to GLIU Port 1, Memory Controller */
|
||||
P2D_SC(0x1000002c, 0x1, 0x0, 0x0000, 0xff03, 0x3),
|
||||
/* GLIU1 */
|
||||
P2D_BM(0x40000020, 0x1, 0x0, 0x0, 0xfff80),
|
||||
/* Traditional Memory 0kB-512kB goes to GLIU port 1, link to GLIU0 */
|
||||
P2D_BM(0x40000020, 0x1, 0x0, 0x00000, 0xfff80),
|
||||
/* Traditional Memory 512kB-1MB goes to GLIU port 1, link to GLIU0 */
|
||||
P2D_BM(0x40000021, 0x1, 0x0, 0x80000, 0xfffe0),
|
||||
P2D_SC(0x4000002d, 0x1, 0x0, 0x0, 0xff03, 0x3),
|
||||
/* Extended Memory, 0xC0000-0x100000, disable write,
|
||||
* enable read 0xC0000 - 0xC8000, 0xE0000-0xFFFFF ,
|
||||
* goest to GLIU Port 1, Memory Controller */
|
||||
P2D_SC(0x4000002d, 0x1, 0x0, 0x0000, 0xff03, 0x3),
|
||||
/* end of table */
|
||||
{0}
|
||||
};
|
||||
|
||||
#define SMM_OFFSET 0x40400000
|
||||
#define SMM_SIZE 256
|
||||
|
||||
/* we have to do this here. We have not found a nicer way to do it */
|
||||
/*
|
||||
* FixME: MSR 0x10000028, 0x40000029 are reprogrammed by SysmemInit()
|
||||
* 0x10000026 and 0x400000023 are reprogrammed by SMMGL0Init() and SMMGL1Init()
|
||||
*/
|
||||
void
|
||||
setup_gx2(void)
|
||||
{
|
||||
|
|
@ -92,7 +112,7 @@ setup_gx2(void)
|
|||
membytes = sizem * 1048576;
|
||||
|
||||
/* we need to set 0x10000028 and 0x40000029 */
|
||||
// print_debug("sizem 0x%x, membytes 0x%x\n", sizem, membytes);
|
||||
//print_debug("sizem 0x%x, membytes 0x%x\n", sizem, membytes);
|
||||
msr.hi = 0x20000000 | membytes>>24;
|
||||
msr.lo = 0x100 | ( ((membytes >>12) & 0xfff) << 20);
|
||||
wrmsr(0x10000028, msr);
|
||||
|
|
@ -100,10 +120,9 @@ setup_gx2(void)
|
|||
msr.lo = 0x100 | ( ((membytes >>12) & 0xfff) << 20);
|
||||
wrmsr(0x40000029, msr);
|
||||
msr = rdmsr(0x10000028);
|
||||
// print_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000028, msr.hi,msr.lo);
|
||||
//print_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000028, msr.hi,msr.lo);
|
||||
msr = rdmsr(0x40000029);
|
||||
// print_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x40000029, msr.hi,msr.lo);
|
||||
|
||||
//print_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x40000029, msr.hi,msr.lo);
|
||||
|
||||
/* fixme: SMM MSR 0x10000026 and 0x400000023 */
|
||||
/* calculate the OFFSET field */
|
||||
|
|
@ -116,7 +135,7 @@ setup_gx2(void)
|
|||
/* calculate the PBASE and PMASK fields */
|
||||
tmp2 = (SMM_OFFSET << 8) & 0xFFF00000; /* shift right 12 then left 20 == left 8 */
|
||||
tmp2 |= (((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff);
|
||||
// print_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000026, tmp, tmp2);
|
||||
//print_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000026, tmp, tmp2);
|
||||
msr.hi = tmp;
|
||||
msr.lo = tmp2;
|
||||
wrmsr(0x10000026, msr);
|
||||
|
|
@ -125,22 +144,22 @@ setup_gx2(void)
|
|||
msr.lo = 0xfbf00100;
|
||||
wrmsr(0x10000028, msr);
|
||||
msr = rdmsr(0x10000028);
|
||||
// print_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000028, msr.hi, msr.lo);
|
||||
//print_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000028, msr.hi, msr.lo);
|
||||
wrmsr(0x40000029, msr);
|
||||
msr = rdmsr(0x40000029);
|
||||
// print_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x40000029, msr.hi, msr.lo);
|
||||
//print_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x40000029, msr.hi, msr.lo);
|
||||
|
||||
msr.hi = 0x2cfbc040;
|
||||
msr.lo = 0x400fffc0;
|
||||
wrmsr(0x10000026, msr);
|
||||
msr = rdmsr(0x10000026);
|
||||
// print_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000026, msr.hi, msr.lo);
|
||||
//print_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000026, msr.hi, msr.lo);
|
||||
|
||||
msr.hi = 0x22fffc02;
|
||||
msr.lo = 0x10ffbf00;
|
||||
wrmsr(0x1808, msr);
|
||||
msr = rdmsr(0x1808);
|
||||
// print_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x1808, msr.hi, msr.lo);
|
||||
//print_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x1808, msr.hi, msr.lo);
|
||||
#endif
|
||||
/* now do the default MSR values */
|
||||
|
||||
|
|
|
|||
|
|
@ -165,7 +165,7 @@ static int cs5536_setup_onchipuart(void)
|
|||
* MSR 0x51400014 bit 18:16
|
||||
* 3. Enable UART controller
|
||||
* MSR 0x5140003A bit 0, 1
|
||||
* 4. IRQ routing on IRQ Mapper
|
||||
* 4. IRQ routing on IRQ Mapper (before loading OS)
|
||||
* MSR 0x51400021 bit [27:24]
|
||||
*/
|
||||
msr_t msr;
|
||||
|
|
|
|||
Loading…
Reference in New Issue