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more code removal and removal of incorrect register settings. 

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2283 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich 2006-04-27 17:46:27 +00:00
parent 94571a4767
commit b947b14734
1 changed files with 3 additions and 1 deletions
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4
src/northbridge/amd/gx2/northbridge.c
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@ -132,6 +132,7 @@ setup_gx2_cache(void)
int sizembytes, sizereg;
sizembytes = sizeram();
#ifdef NO
printk_debug("enable_cache: enable for %dm bytes\n", sizembytes);
/* build up the rconf word. */
/* the SYSTOP bits 27:8 are actually the top bits from 31:12. Book fails to say that */
@ -155,7 +156,7 @@ setup_gx2_cache(void)
msr.hi = (val >> 32);
printk_debug("msr will be set to %x:%x\n", msr.hi, msr.lo);
wrmsr(CPU_RCONF_DEFAULT, msr);
#endif
enable_cache();
wbinvd();
return sizembytes;
@ -419,6 +420,7 @@ static void enable_dev(struct device *dev)
cpubug();
chipsetinit();
//setup_gx2();
setup_gx2_cache();
/* do this here for now -- this chip really breaks our device model */
setup_realmode_idt();
do_vsmbios();