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Final set of changes to make Alix1c work. 

Fix IRQ tables (Thanks to Marc Jones)

Fix IRQ SLOT #

Comment out ram test in early startup. 

make the debug print in lx/raminit.c a debug print, not emerg print

Set the default console log level to 3, but leave in the possibility of 
running with more info (leave maximum at 11)

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Marc Jones <marc.jones@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2952 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich 2007-11-07 23:13:43 +00:00
parent cce5040153
commit 6503cd9d00
5 changed files with 125 additions and 87 deletions
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2
src/mainboard/pcengines/alix1c/Options.lb
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@ -103,7 +103,7 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
## Build code to export a programmable irq routing table ## Build code to export a programmable irq routing table
## ##
default HAVE_PIRQ_TABLE=1 default HAVE_PIRQ_TABLE=1
default IRQ_SLOT_COUNT=9 default IRQ_SLOT_COUNT=5
#object irq_tables.o #object irq_tables.o
## ##

3
src/mainboard/pcengines/alix1c/cache_as_ram_auto.c
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@ -169,7 +169,8 @@ void cache_as_ram_main(void)
sdram_initialize(1, memctrl); sdram_initialize(1, memctrl);
/* Check memory */ /* Check memory */
ram_check(0x00000000, 640 * 1024); /* enable this only if you are having questions */
/* ram_check(0x00000000, 640 * 1024);*/
/* Switch from Cache as RAM to real RAM /* Switch from Cache as RAM to real RAM
* There are two ways we could think about this. * There are two ways we could think about this.

103
src/mainboard/pcengines/alix1c/irq_tables.c
View File

@ -25,9 +25,9 @@
/* Platform IRQs */ /* Platform IRQs */
#define PIRQA 11 #define PIRQA 11
#define PIRQB 5 #define PIRQB 10
#define PIRQC 10 #define PIRQC 11
#define PIRQD 10 #define PIRQD 9
/* Map */ /* Map */
#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */ #define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
@ -41,67 +41,104 @@
#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */ #define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */ #define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
/* ALIX 1c interrupt wiring. Devices are:
* 00:01.0 Host bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] Host Bridge (rev 31)
* 00:01.2 Entertainment encryption device: Advanced Micro Devices [AMD] Geode LX AES Security Block
* 00:0d.0 Ethernet controller: VIA Technologies, Inc. VT6105M [Rhine-III] (rev 96)
* 00:0e.0 Network controller: Intersil Corporation Prism 2.5 Wavelan chipset (rev 01)
* 00:0f.0 ISA bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA (rev 03)
* 00:0f.2 IDE interface: Advanced Micro Devices [AMD] CS5536 [Geode companion] IDE (rev 01)
* 00:0f.3 Multimedia audio controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] Audio (rev 01)
* 00:0f.4 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] OHC (rev 02)
* 00:0f.5 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC (rev 02)
* The only devices that interrupt are:
* What device IRQ PIN PIN WIRED TO
* AES 00:01.2 0a 01 A A
* 3VPCI 00:0c.0 0a 01 A A
* eth0 00:0d.0 0b 01 A B
* mpci 00:0e.0 0a 01 A A
* usb 00:0f.3 0b 02 B B
* usb 00:0f.4 0b 04 D D
* usb 00:0f.5 0b 04 D D
*
* The only swizzled interrupt is eth0, where INTA is wired to interrupt controller line B
*/
const struct irq_routing_table intel_irq_routing_table = { const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */ PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */ PIRQ_VERSION, /* u16 version */
32+16*IRQ_SLOT_COUNT, /* There can be total IRQ_SLOT_COUNT devices on the bus */ 32 + 16 * IRQ_SLOT_COUNT,
0x00, /* Where the interrupt router lies (bus) */ 0x00, /* Where the interrupt router lies (bus) */
(0x0f<<3)|0x0, /* Where the interrupt router lies (dev) */ (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
0, /* IRQs devoted exclusively to PCI usage */ 0x00, /* IRQs devoted exclusively to PCI usage */
0x100b, /* Vendor */ 0x100B, /* Vendor */
0x2b, /* Device */ 0x002B, /* Device */
0, /* Crap (miniport) */ 0, /* Crap (miniport) */
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
0xe, /* u8 checksum. This has to be set to some 0x00, /* u8 checksum , this has to set to
value that would give 0 after the sum of all * some value that would give 0
bytes for this structure (including checksum) */ * after the sum of all bytes
* for this structure
* (including checksum)
*/
{ {
/* If you change the number of entries,
* change the IRQ_SLOT_COUNT above!
*/
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00,(0x01<<3)|0x0, {{0x01, 0x0400}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */
{0x00,(0x0f<<3)|0x0, {{0x01, 0x0400}, {0x02, 0x0800}, {0x03, 0x0400}, {0x04, 0x00800}}, 0x0, 0x0}, /* PCI SLOT */
{0x00,(0x13<<3)|0x0, {{0x01, 0x0400}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, {0x00, (0x0C << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x4, 0x0}, /* slot1 */
{0x00,(0x12<<3)|0x0, {{0x03, 0x0400}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* ONBOARD ETHER */
{0x00,(0x11<<3)|0x0, {{0x01, 0x0400}, {0x02, 0x0800}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, {0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet */
{0x00,(0x0a<<3)|0x0, {{0x01, 0x0400}, {0x02, 0x0800}, {0x03, 0x0400}, {0x04, 0x00800}}, 0x1, 0x0}, /* MINI PCI */
{0x00,(0x0b<<3)|0x0, {{0x02, 0x0800}, {0x03, 0x0400}, {0x04, 0x0800}, {0x01, 0x00400}}, 0x2, 0x0}, {0x00, (0x0E << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x1, 0x0}, /* mini slot2 */
{0x00,(0x0c<<3)|0x0, {{0x03, 0x0400}, {0x04, 0x0800}, {0x01, 0x0400}, {0x02, 0x00800}}, 0x3, 0x0}, /* Chipset slots -- f.3 wires to B, and f.4 and f.5 wires to D */
{0x00,(0x0d<<3)|0x0, {{0x04, 0x0800}, {0x01, 0x0400}, {0x02, 0x0800}, {0x03, 0x00400}}, 0x4, 0x0}, {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */
} }
}; };
unsigned long write_pirq_routing_table(unsigned long addr)
unsigned long write_pirq_routing_table(unsigned long addr){ {
int i, j, k, num_entries; int i, j, k, num_entries;
unsigned int pirq[4]; unsigned char pirq[4];
uint16_t chipset_irq_map; uint16_t chipset_irq_map;
uint32_t pciAddr, pirtable_end; uint32_t pciAddr, pirtable_end;
struct irq_routing_table *pirq_tbl; struct irq_routing_table *pirq_tbl;
pirtable_end = copy_pirq_routing_table(addr); pirtable_end = copy_pirq_routing_table(addr);
/* Set up chipset IRQ steering */ /* Set up chipset IRQ steering. */
pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C; pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
chipset_irq_map = (11 << 12 | 10 << 8 | 11 << 4 | 10); chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA);
printk_debug("%s(%08X, %04X)\n", __FUNCTION__, pciAddr, chipset_irq_map); printk_debug("%s(%08X, %04X)\n", __FUNCTION__, pciAddr,
chipset_irq_map);
outl(pciAddr & ~3, 0xCF8); outl(pciAddr & ~3, 0xCF8);
outl(chipset_irq_map, 0xCFC); outl(chipset_irq_map, 0xCFC);
pirq_tbl = (struct irq_routing_table *) (addr); pirq_tbl = (struct irq_routing_table *) (addr);
num_entries = (pirq_tbl->size - 32) / 16; num_entries = (pirq_tbl->size - 32) / 16;
/* Set PCI IRQs */ /* Set PCI IRQs. */
for (i = 0; i < num_entries; i++) { for (i = 0; i < num_entries; i++) {
printk_debug("PIR Entry %d Dev/Fn: %X Slot: %d\n", i, pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot); printk_debug("PIR Entry %d Dev/Fn: %X Slot: %d\n", i,
pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot);
for (j = 0; j < 4; j++) { for (j = 0; j < 4; j++) {
printk_debug("INT: %c bitmap: %x ", 'A'+j, pirq_tbl->slots[i].irq[j].bitmap); printk_debug("INT: %c bitmap: %x ", 'A' + j,
for (k = 0; (!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1)) && (pirq_tbl->slots[i].irq[j].bitmap != 0); k++); /* finds lsb in bitmap to IRQ# */ pirq_tbl->slots[i].irq[j].bitmap);
/* Finds lsb in bitmap to IRQ#. */
for (k = 0;
(!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1))
&& (pirq_tbl->slots[i].irq[j].bitmap != 0);
k++);
pirq[j] = k; pirq[j] = k;
printk_debug("PIRQ: %d\n", k); printk_debug("PIRQ: %d\n", k);
} }
pci_assign_irqs(pirq_tbl->slots[i].bus, pirq_tbl->slots[i].devfn, pirq); /* bus, device, slots IRQs for {A,B,C,D} */
/* Bus, device, slots IRQs for {A,B,C,D}. */
pci_assign_irqs(pirq_tbl->slots[i].bus,
pirq_tbl->slots[i].devfn >> 3, pirq);
} }
/* put the PIR table in memory and checksum */ /* Put the PIR table in memory and checksum. */
return pirtable_end; return pirtable_end;
} }

6
src/northbridge/amd/lx/raminit.c
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@ -29,9 +29,9 @@ static const unsigned char NumColAddr[] = {
void banner(char *s) void banner(char *s)
{ {
print_emerg("==========================="); print_debug("===========================");
print_emerg(s); print_debug(s);
print_emerg("======================================\r\n"); print_debug("======================================\r\n");
} }
void hcf(void) void hcf(void)
{ {

2
targets/pcengines/alix1c/Config.lb
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@ -15,7 +15,7 @@ option ROM_IMAGE_SIZE=64*1024
option FALLBACK_SIZE = ROM_SIZE option FALLBACK_SIZE = ROM_SIZE
option DEFAULT_CONSOLE_LOGLEVEL = 11 option DEFAULT_CONSOLE_LOGLEVEL = 3
option MAXIMUM_CONSOLE_LOGLEVEL = 11 option MAXIMUM_CONSOLE_LOGLEVEL = 11
romimage "fallback" romimage "fallback"
option USE_FALLBACK_IMAGE=1 option USE_FALLBACK_IMAGE=1