Final set of changes to make Alix1c work.
Fix IRQ tables (Thanks to Marc Jones) Fix IRQ SLOT # Comment out ram test in early startup. make the debug print in lx/raminit.c a debug print, not emerg print Set the default console log level to 3, but leave in the possibility of running with more info (leave maximum at 11) Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Marc Jones <marc.jones@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2952 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich
parent
cce5040153
commit
6503cd9d00
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@ -103,7 +103,7 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
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## Build code to export a programmable irq routing table
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##
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default HAVE_PIRQ_TABLE=1
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default IRQ_SLOT_COUNT=9
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default IRQ_SLOT_COUNT=5
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#object irq_tables.o
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##
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@ -169,7 +169,8 @@ void cache_as_ram_main(void)
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sdram_initialize(1, memctrl);
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/* Check memory */
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ram_check(0x00000000, 640 * 1024);
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/* enable this only if you are having questions */
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/* ram_check(0x00000000, 640 * 1024);*/
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/* Switch from Cache as RAM to real RAM
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* There are two ways we could think about this.
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@ -1,21 +1,21 @@
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/*
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* This file is part of the LinuxBIOS project.
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*
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* Copyright (C) 2007 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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* This file is part of the LinuxBIOS project.
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*
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* Copyright (C) 2007 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/pirq_routing.h>
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#include <console/console.h>
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@ -25,9 +25,9 @@
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/* Platform IRQs */
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#define PIRQA 11
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#define PIRQB 5
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#define PIRQC 10
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#define PIRQD 10
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#define PIRQB 10
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#define PIRQC 11
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#define PIRQD 9
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/* Map */
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#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
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@ -41,67 +41,104 @@
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#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
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#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
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/* ALIX 1c interrupt wiring. Devices are:
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* 00:01.0 Host bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] Host Bridge (rev 31)
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* 00:01.2 Entertainment encryption device: Advanced Micro Devices [AMD] Geode LX AES Security Block
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* 00:0d.0 Ethernet controller: VIA Technologies, Inc. VT6105M [Rhine-III] (rev 96)
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* 00:0e.0 Network controller: Intersil Corporation Prism 2.5 Wavelan chipset (rev 01)
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* 00:0f.0 ISA bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA (rev 03)
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* 00:0f.2 IDE interface: Advanced Micro Devices [AMD] CS5536 [Geode companion] IDE (rev 01)
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* 00:0f.3 Multimedia audio controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] Audio (rev 01)
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* 00:0f.4 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] OHC (rev 02)
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* 00:0f.5 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC (rev 02)
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* The only devices that interrupt are:
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* What device IRQ PIN PIN WIRED TO
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* AES 00:01.2 0a 01 A A
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* 3VPCI 00:0c.0 0a 01 A A
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* eth0 00:0d.0 0b 01 A B
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* mpci 00:0e.0 0a 01 A A
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* usb 00:0f.3 0b 02 B B
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* usb 00:0f.4 0b 04 D D
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* usb 00:0f.5 0b 04 D D
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*
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* The only swizzled interrupt is eth0, where INTA is wired to interrupt controller line B
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*/
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const struct irq_routing_table intel_irq_routing_table = {
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PIRQ_SIGNATURE, /* u32 signature */
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PIRQ_VERSION, /* u16 version */
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32+16*IRQ_SLOT_COUNT, /* There can be total IRQ_SLOT_COUNT devices on the bus */
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0x00, /* Where the interrupt router lies (bus) */
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(0x0f<<3)|0x0, /* Where the interrupt router lies (dev) */
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0, /* IRQs devoted exclusively to PCI usage */
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0x100b, /* Vendor */
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0x2b, /* Device */
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0, /* Crap (miniport) */
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
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0xe, /* u8 checksum. This has to be set to some
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value that would give 0 after the sum of all
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bytes for this structure (including checksum) */
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{
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PIRQ_SIGNATURE, /* u32 signature */
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PIRQ_VERSION, /* u16 version */
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32 + 16 * IRQ_SLOT_COUNT,
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0x00, /* Where the interrupt router lies (bus) */
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(0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
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0x00, /* IRQs devoted exclusively to PCI usage */
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0x100B, /* Vendor */
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0x002B, /* Device */
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0, /* Crap (miniport) */
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{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
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0x00, /* u8 checksum , this has to set to
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* some value that would give 0
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* after the sum of all bytes
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* for this structure
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* (including checksum)
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*/
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{
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/* If you change the number of entries,
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* change the IRQ_SLOT_COUNT above!
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*/
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/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
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{0x00,(0x01<<3)|0x0, {{0x01, 0x0400}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
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{0x00,(0x0f<<3)|0x0, {{0x01, 0x0400}, {0x02, 0x0800}, {0x03, 0x0400}, {0x04, 0x00800}}, 0x0, 0x0},
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{0x00,(0x13<<3)|0x0, {{0x01, 0x0400}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
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{0x00,(0x12<<3)|0x0, {{0x03, 0x0400}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
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{0x00,(0x11<<3)|0x0, {{0x01, 0x0400}, {0x02, 0x0800}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
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{0x00,(0x0a<<3)|0x0, {{0x01, 0x0400}, {0x02, 0x0800}, {0x03, 0x0400}, {0x04, 0x00800}}, 0x1, 0x0},
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{0x00,(0x0b<<3)|0x0, {{0x02, 0x0800}, {0x03, 0x0400}, {0x04, 0x0800}, {0x01, 0x00400}}, 0x2, 0x0},
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{0x00,(0x0c<<3)|0x0, {{0x03, 0x0400}, {0x04, 0x0800}, {0x01, 0x0400}, {0x02, 0x00800}}, 0x3, 0x0},
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{0x00,(0x0d<<3)|0x0, {{0x04, 0x0800}, {0x01, 0x0400}, {0x02, 0x0800}, {0x03, 0x00400}}, 0x4, 0x0},
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{0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */
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/* PCI SLOT */
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{0x00, (0x0C << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x4, 0x0}, /* slot1 */
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/* ONBOARD ETHER */
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{0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet */
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/* MINI PCI */
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{0x00, (0x0E << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x1, 0x0}, /* mini slot2 */
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/* Chipset slots -- f.3 wires to B, and f.4 and f.5 wires to D */
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{0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */
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}
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};
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unsigned long write_pirq_routing_table(unsigned long addr){
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unsigned long write_pirq_routing_table(unsigned long addr)
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{
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int i, j, k, num_entries;
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unsigned int pirq[4];
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unsigned char pirq[4];
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uint16_t chipset_irq_map;
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uint32_t pciAddr, pirtable_end;
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struct irq_routing_table *pirq_tbl;
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pirtable_end = copy_pirq_routing_table(addr);
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/* Set up chipset IRQ steering */
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/* Set up chipset IRQ steering. */
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pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
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chipset_irq_map = (11 << 12 | 10 << 8 | 11 << 4 | 10);
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printk_debug("%s(%08X, %04X)\n", __FUNCTION__, pciAddr, chipset_irq_map);
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chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA);
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printk_debug("%s(%08X, %04X)\n", __FUNCTION__, pciAddr,
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chipset_irq_map);
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outl(pciAddr & ~3, 0xCF8);
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outl(chipset_irq_map, 0xCFC);
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pirq_tbl = (struct irq_routing_table *)(addr);
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num_entries = (pirq_tbl->size - 32)/16;
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pirq_tbl = (struct irq_routing_table *) (addr);
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num_entries = (pirq_tbl->size - 32) / 16;
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/* Set PCI IRQs */
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for (i=0; i < num_entries; i++){
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printk_debug("PIR Entry %d Dev/Fn: %X Slot: %d\n", i, pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot);
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for (j = 0; j < 4; j++){
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printk_debug("INT: %c bitmap: %x ", 'A'+j, pirq_tbl->slots[i].irq[j].bitmap);
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for (k = 0; (!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1)) && (pirq_tbl->slots[i].irq[j].bitmap != 0); k++); /* finds lsb in bitmap to IRQ# */
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/* Set PCI IRQs. */
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for (i = 0; i < num_entries; i++) {
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printk_debug("PIR Entry %d Dev/Fn: %X Slot: %d\n", i,
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pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot);
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for (j = 0; j < 4; j++) {
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printk_debug("INT: %c bitmap: %x ", 'A' + j,
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pirq_tbl->slots[i].irq[j].bitmap);
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/* Finds lsb in bitmap to IRQ#. */
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for (k = 0;
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(!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1))
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&& (pirq_tbl->slots[i].irq[j].bitmap != 0);
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k++);
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pirq[j] = k;
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printk_debug("PIRQ: %d\n", k);
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}
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pci_assign_irqs(pirq_tbl->slots[i].bus, pirq_tbl->slots[i].devfn, pirq); /* bus, device, slots IRQs for {A,B,C,D} */
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/* Bus, device, slots IRQs for {A,B,C,D}. */
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pci_assign_irqs(pirq_tbl->slots[i].bus,
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pirq_tbl->slots[i].devfn >> 3, pirq);
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}
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/* put the PIR table in memory and checksum */
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/* Put the PIR table in memory and checksum. */
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return pirtable_end;
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}
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@ -29,9 +29,9 @@ static const unsigned char NumColAddr[] = {
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void banner(char *s)
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{
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print_emerg("===========================");
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print_emerg(s);
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print_emerg("======================================\r\n");
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print_debug("===========================");
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print_debug(s);
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print_debug("======================================\r\n");
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}
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void hcf(void)
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{
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@ -15,7 +15,7 @@ option ROM_IMAGE_SIZE=64*1024
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option FALLBACK_SIZE = ROM_SIZE
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option DEFAULT_CONSOLE_LOGLEVEL = 11
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option DEFAULT_CONSOLE_LOGLEVEL = 3
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option MAXIMUM_CONSOLE_LOGLEVEL = 11
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romimage "fallback"
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option USE_FALLBACK_IMAGE=1
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