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nb/intel/sandybridge: use MESEG register names from datasheet 

I used register names guessed on what the registers do, since the SNB
documentation marked those registers as reserved; the IVB documentation
(326765-005) has names for the registers, so I'll use those.

Change-Id: I2f1194438a56546d9836dd12635d064a900a2fd8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38008
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Held 2019-12-30 16:28:48 +01:00
parent 6ad0ab1a69
commit 651f99f12b
3 changed files with 15 additions and 15 deletions
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2
src/northbridge/intel/sandybridge/finalize.c
View File

@ -24,7 +24,7 @@ void intel_sandybridge_finalize_smm(void)
pci_or_config16(PCI_DEV_SNB, GGC, 1 << 0);
pci_or_config16(PCI_DEV_SNB, PAVPC, 1 << 2);
pci_or_config32(PCI_DEV_SNB, DPR, 1 << 0);
pci_or_config32(PCI_DEV_SNB, MEMASK, 1 << 10);
pci_or_config32(PCI_DEV_SNB, MESEG_MASK, 1 << 10);
pci_or_config32(PCI_DEV_SNB, REMAPBASE, 1 << 0);
pci_or_config32(PCI_DEV_SNB, REMAPLIMIT, 1 << 0);
pci_or_config32(PCI_DEV_SNB, TOM, 1 << 0);

24
src/northbridge/intel/sandybridge/raminit_common.c
View File

@ -585,33 +585,33 @@ void dram_memorymap(ramctr_timing * ctrl, int me_uma_size)
pci_write_config32(PCI_DEV(0, 0, 0), BGSM, reg);
if (me_uma_size) {
reg = pci_read_config32(PCI_DEV(0, 0, 0), MEMASK + 4);
reg = pci_read_config32(PCI_DEV(0, 0, 0), MESEG_MASK + 4);
val = (0x80000 - me_uma_size) & 0xfffff000;
reg = (reg & ~0x000fffff) | (val >> 12);
printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MEMASK + 4, reg);
pci_write_config32(PCI_DEV(0, 0, 0), MEMASK + 4, reg);
printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_MASK + 4, reg);
pci_write_config32(PCI_DEV(0, 0, 0), MESEG_MASK + 4, reg);
// ME base
reg = pci_read_config32(PCI_DEV(0, 0, 0), MEBASE);
reg = pci_read_config32(PCI_DEV(0, 0, 0), MESEG_BASE);
val = mestolenbase & 0xfff;
reg = (reg & ~0xfff00000) | (val << 20);
printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MEBASE, reg);
pci_write_config32(PCI_DEV(0, 0, 0), MEBASE, reg);
printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_BASE, reg);
pci_write_config32(PCI_DEV(0, 0, 0), MESEG_BASE, reg);
reg = pci_read_config32(PCI_DEV(0, 0, 0), MEBASE + 4);
reg = pci_read_config32(PCI_DEV(0, 0, 0), MESEG_BASE + 4);
val = mestolenbase & 0xfffff000;
reg = (reg & ~0x000fffff) | (val >> 12);
printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MEBASE + 4, reg);
pci_write_config32(PCI_DEV(0, 0, 0), MEBASE + 4, reg);
printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_BASE + 4, reg);
pci_write_config32(PCI_DEV(0, 0, 0), MESEG_BASE + 4, reg);
// ME mask
reg = pci_read_config32(PCI_DEV(0, 0, 0), MEMASK);
reg = pci_read_config32(PCI_DEV(0, 0, 0), MESEG_MASK);
val = (0x80000 - me_uma_size) & 0xfff;
reg = (reg & ~0xfff00000) | (val << 20);
reg = reg | (1 << 10); // set lockbit on ME mem
reg = reg | (1 << 11); // set ME memory enable
printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MEMASK, reg);
pci_write_config32(PCI_DEV(0, 0, 0), MEMASK, reg);
printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_MASK, reg);
pci_write_config32(PCI_DEV(0, 0, 0), MESEG_MASK, reg);
}
}

4
src/northbridge/intel/sandybridge/sandybridge.h
View File

@ -82,8 +82,8 @@ enum platform_type {
#define PAVPC 0x58 /* Protected Audio Video Path Control */
#define DPR 0x5c /* DMA Protected Range */
#define MEBASE 0x70
#define MEMASK 0x78
#define MESEG_BASE 0x70
#define MESEG_MASK 0x78
#define PAM0 0x80
#define PAM1 0x81