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mb/google/brya/var/kano: Update TDP PL1, PL2, and PL4 for U28 SKUs 

Based on testing results from the thermal team, they have decided
to update PL1, PL2 and PL4 for U28 SKUs.

BUG=b:221338290
TEST=Run with U28 and ensure the PL1/PL2/PL4 settings are correct

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ib82e2dbacd6cbc39390eb28f27ca9db48d6c215c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62466
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
This commit is contained in:
David Wu 2022-03-01 13:59:20 +08:00 committed by Felix Held
parent fadd0ff40a
commit 6555c4c601
2 changed files with 17 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
src/mainboard/google/brya/variants/kano/overridetree.cb
View File

@ -63,6 +63,18 @@ chip soc/intel/alderlake
},
}"
register "power_limits_config[ADL_P_282_482_28W_CORE]" = "{
.tdp_pl1_override = 20,
.tdp_pl2_override = 43,
.tdp_pl4 = 105,
}"
register "power_limits_config[ADL_P_682_28W_CORE]" = "{
.tdp_pl1_override = 20,
.tdp_pl2_override = 43,
.tdp_pl4 = 105,
}"
device domain 0 on
device ref dtt on
chip drivers/intel/dptf
@ -119,14 +131,14 @@ chip soc/intel/alderlake
register "controls.power_limits" = "{
.pl1 = {
.min_power = 18000,
.max_power = 28000,
.max_power = 20000,
.time_window_min = 28 * MSECS_PER_SEC,
.time_window_max = 32 * MSECS_PER_SEC,
.granularity = 200,
},
.pl2 = {
.min_power = 40000,
.max_power = 40000,
.min_power = 43000,
.max_power = 43000,
.time_window_min = 28 * MSECS_PER_SEC,
.time_window_max = 32 * MSECS_PER_SEC,
.granularity = 1000,

4
src/mainboard/google/brya/variants/kano/ramstage.c
View File

@ -7,8 +7,8 @@ const struct cpu_power_limits limits[] = {
/* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */
{ PCI_DID_INTEL_ADL_P_ID_7, 15, 12000, 15000, 40000, 40000, 105000 },
{ PCI_DID_INTEL_ADL_P_ID_6, 15, 12000, 15000, 40000, 40000, 105000 },
{ PCI_DID_INTEL_ADL_P_ID_5, 28, 18000, 28000, 40000, 40000, 105000 },
{ PCI_DID_INTEL_ADL_P_ID_3, 28, 18000, 28000, 40000, 40000, 105000 },
{ PCI_DID_INTEL_ADL_P_ID_5, 28, 18000, 20000, 43000, 43000, 105000 },
{ PCI_DID_INTEL_ADL_P_ID_3, 28, 18000, 20000, 43000, 43000, 105000 },
};
void variant_devtree_update(void)