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soc/mediatek/mt8192: Increase PRERAM_CBMEM_CONSOLE to 400K 

Move PRERAM_CBMEM_CONSOLE to SRAM L2C and increase its size from 15K to
400K. With this change, most part of the DRAM full calibration log can
be stored in CBMEM console.

BUG=b:181933863
TEST=emerge-asurada coreboot
TEST=Hayato boots
BRANCH=none

Change-Id: I896884d298e197149f75865e9d00579124a34404
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
This commit is contained in:
Yu-Ping Wu 2021-03-02 17:52:08 +08:00 committed by Hung-Te Lin
parent a3b19441f6
commit 656fa56a22
1 changed files with 1 additions and 1 deletions
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2
src/soc/mediatek/mt8192/include/soc/memlayout.ld
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@ -26,7 +26,6 @@ SECTIONS
TPM_TCPA_LOG(0x00103000, 2K) TPM_TCPA_LOG(0x00103000, 2K)
FMAP_CACHE(0x00103800, 2K) FMAP_CACHE(0x00103800, 2K)
WATCHDOG_TOMBSTONE(0x00104000, 4) WATCHDOG_TOMBSTONE(0x00104000, 4)
PRERAM_CBMEM_CONSOLE(0x00104004, 15K - 4)
CBFS_MCACHE(0x00107c00, 8K) CBFS_MCACHE(0x00107c00, 8K)
TIMESTAMP(0x00109c00, 1K) TIMESTAMP(0x00109c00, 1K)
STACK(0x0010a000, 12K) STACK(0x0010a000, 12K)
@ -49,6 +48,7 @@ SECTIONS
*/ */
DRAM_INIT_CODE(0x00250000, 256K) DRAM_INIT_CODE(0x00250000, 256K)
PRERAM_CBFS_CACHE(0x00290000, 48K) PRERAM_CBFS_CACHE(0x00290000, 48K)
PRERAM_CBMEM_CONSOLE(0x0029c000, 400K)
SRAM_L2C_END(0x00300000) SRAM_L2C_END(0x00300000)
DRAM_START(0x40000000) DRAM_START(0x40000000)