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soc/mediatek/mt8173,mt8183: revise SOC DRAM implementation 

Many header files and helper macros have been moved to the
common folder and we want to use them in mt8173/mt8183
DRAM calibration code.

Signed-off-by: Xi Chen <xixi.chen@mediatek.com>
Change-Id: Ifa483dcfffe0e1383cb46811563c90f0ab484d5d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51224
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Xi Chen 2021-03-03 18:04:28 +08:00 committed by Hung-Te Lin
parent 05764cd6c9
commit a3b19441f6
9 changed files with 86 additions and 103 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
src/soc/mediatek/mt8173/Kconfig
View File

@ -7,6 +7,7 @@ config SOC_MEDIATEK_MT8173
select ARCH_ROMSTAGE_ARMV8_64
select ARCH_VERSTAGE_ARMV8_64
select ARM64_USE_ARM_TRUSTED_FIRMWARE
select HAVE_DEBUG_RAM_SETUP
select HAVE_UART_SPECIAL
select GENERIC_GPIO_LIB
select RTC
@ -26,17 +27,11 @@ config VBOOT
config DEBUG_SOC_DRIVER
bool "The top level switch for soc driver debug messages"
default n
select DEBUG_DRAM
select DEBUG_RAM_SETUP
select DEBUG_I2C
select DEBUG_PMIC
select DEBUG_PMIC_WRAP
config DEBUG_DRAM
bool "Output verbose DRAM related debug messages"
default n
help
This option enables additional DRAM related debug messages.
config DEBUG_I2C
bool "Output verbose I2C related debug messages"
default n

13
src/soc/mediatek/mt8173/dramc_pi_basic_api.c
View File

@ -8,6 +8,7 @@
#include <soc/dramc_common.h>
#include <soc/dramc_register.h>
#include <soc/dramc_pi_api.h>
#include <soc/dramc_soc.h>
#include <soc/emi.h>
#include <soc/mt6391.h>
#include <soc/pll.h>
@ -184,7 +185,7 @@ static void pll_phase_check(u32 channel, struct mem_pll *mempll, int idx)
u16 one_count = (u16)((value >> 16) & 0xffff);
u16 zero_count = (u16)(value & 0xffff);
dramc_dbg_msg("PLL %d, phase %d, one_count %d, zero_count %d\n",
dramc_dbg("PLL %d, phase %d, one_count %d, zero_count %d\n",
(idx + 2), mempll->phase, one_count, zero_count);
switch (mempll->phase) {
@ -232,8 +233,8 @@ static void mem_pll_phase_cali(u32 channel)
{0, 0, 0},
};
dramc_dbg_msg("[PLL_Phase_Calib] ===== PLL Phase Calibration: ");
dramc_dbg_msg("CHANNEL %d (0: CHA, 1: CHB) =====\n", channel);
dramc_dbg("[PLL_Phase_Calib] ===== PLL Phase Calibration: ");
dramc_dbg("CHANNEL %d (0: CHA, 1: CHB) =====\n", channel);
/* 1. set jitter meter count number to 1024 for mempll 2 3 4 */
for (i = 0; i < 3; i++)
@ -283,11 +284,11 @@ static void mem_pll_phase_cali(u32 channel)
}
}
dramc_dbg_msg("pll done: ");
dramc_dbg("pll done: ");
dramc_dbg_msg("%d, %d, %d\n",
dramc_dbg("%d, %d, %d\n",
mempll[0].done, mempll[1].done, mempll[2].done);
dramc_dbg_msg("pll dl: %d, %d, %d\n",
dramc_dbg("pll dl: %d, %d, %d\n",
mempll[0].delay, mempll[1].delay, mempll[2].delay);
}

137
src/soc/mediatek/mt8173/dramc_pi_calibration_api.c
View File

@ -6,6 +6,7 @@
#include <soc/dramc_common.h>
#include <soc/dramc_register.h>
#include <soc/dramc_pi_api.h>
#include <soc/dramc_soc.h>
#include <soc/emi.h>
static u8 opt_gw_coarse_value[CHANNEL_NUM][DUAL_RANKS];
@ -19,8 +20,8 @@ void sw_impedance_cal(u32 channel,
const struct mt8173_calib_params *params = &sdram_params->calib_params;
dramc_dbg_msg("[Imp Calibration] DRVP:%d\n", params->impedance_drvp);
dramc_dbg_msg("[Imp Calibration] DRVN:%d\n", params->impedance_drvn);
dramc_dbg("[Imp Calibration] DRVP:%d\n", params->impedance_drvp);
dramc_dbg("[Imp Calibration] DRVN:%d\n", params->impedance_drvn);
mask = 0xf << 28 | 0xf << 24 | 0xf << 12 | 0xf << 8; /* driving */
@ -110,18 +111,18 @@ void ca_training(u32 channel, const struct mt8173_sdram_params *sdram_params)
0xf << PADCTL1_CLK_SHIFT,
ca_max_center << PADCTL1_CLK_SHIFT);
dramc_dbg_msg("=========================================\n");
dramc_dbg_msg(" [Channel %d] CA training\n", channel);
dramc_dbg_msg("=========================================\n");
dramc_dbg("=========================================\n");
dramc_dbg(" [Channel %d] CA training\n", channel);
dramc_dbg("=========================================\n");
for (i = 0; i < CATRAINING_NUM; i++)
dramc_dbg_msg("[CA] CA %d\tShift %d\n", i, ca_shift[i]);
dramc_dbg("[CA] CA %d\tShift %d\n", i, ca_shift[i]);
dramc_dbg_msg("[CA] Reg CMDDLY4 = %xh\n",
dramc_dbg("[CA] Reg CMDDLY4 = %xh\n",
read32(&ch[channel].ddrphy_regs->cmddly[4]));
dramc_dbg_msg("[CA] Reg DQSCAL1 = %xh\n",
dramc_dbg("[CA] Reg DQSCAL1 = %xh\n",
read32(&ch[channel].ao_regs->dqscal1));
dramc_dbg_msg("[CA] Reg PADCTL1 = %xh\n",
dramc_dbg("[CA] Reg PADCTL1 = %xh\n",
read32(&ch[channel].ddrphy_regs->padctl1));
}
@ -154,17 +155,17 @@ void write_leveling(u32 channel, const struct mt8173_sdram_params *sdram_params)
write32(&ch[channel].ddrphy_regs->dqodly[byte_i], value);
}
dramc_dbg_msg("========================================\n");
dramc_dbg_msg("[Channel %d] dramc_write_leveling_swcal\n", channel);
dramc_dbg_msg("========================================\n");
dramc_dbg("========================================\n");
dramc_dbg("[Channel %d] dramc_write_leveling_swcal\n", channel);
dramc_dbg("========================================\n");
dramc_dbg_msg("[WL] DQS: %#x",
dramc_dbg("[WL] DQS: %#x",
read32(&ch[channel].ddrphy_regs->padctl3));
dramc_dbg_msg("[WL] DQM: %#x\n",
dramc_dbg("[WL] DQM: %#x\n",
read32(&ch[channel].ddrphy_regs->padctl2));
for (byte_i = 0; byte_i < DQS_NUMBER; byte_i++)
dramc_dbg_msg("[WL] DQ byte%d: %#x\n", byte_i,
dramc_dbg("[WL] DQ byte%d: %#x\n", byte_i,
read32(&ch[channel].ddrphy_regs->dqodly[byte_i]));
}
@ -358,11 +359,11 @@ void rx_dqs_gating_cal(u32 channel, u8 rank,
gw_coarse_val = sdram_params->calib_params.gating_win[channel][rank][0];
gw_fine_val = sdram_params->calib_params.gating_win[channel][rank][1];
dramc_dbg_msg("****************************************************\n");
dramc_dbg_msg("Channel %d Rank %d DQS GW Calibration\n", channel, rank);
dramc_dbg_msg("Default (coarse, fine) tune value %d, %d.\n",
dramc_dbg("****************************************************\n");
dramc_dbg("Channel %d Rank %d DQS GW Calibration\n", channel, rank);
dramc_dbg("Default (coarse, fine) tune value %d, %d.\n",
gw_coarse_val, gw_fine_val);
dramc_dbg_msg("****************************************************\n");
dramc_dbg("****************************************************\n");
/* set default coarse and fine value */
set_gw_coarse_factor(channel, gw_coarse_val);
@ -596,7 +597,7 @@ u8 dramk_calcu_best_dly(u8 bit, struct dqs_perbit_dly *p, u8 *p_max_byte)
}
}
dramc_dbg_msg("bit#%d : dq =%d dqs=%d win=%d (%d, %d)\n",
dramc_dbg("bit#%d : dq =%d dqs=%d win=%d (%d, %d)\n",
bit, setup, hold, setup + hold,
p->best_dqdly, p->best_dqsdly);
@ -618,8 +619,8 @@ void clk_duty_cal(u32 channel)
max_win_size = read32(&ch[channel].ddrphy_regs->phyclkduty);
dramc_dbg_msg("[Channel %d CLK DUTY CALIB] ", channel);
dramc_dbg_msg("Final DUTY_SEL=%d, DUTY=%d, rx window size=%d\n",
dramc_dbg("[Channel %d CLK DUTY CALIB] ", channel);
dramc_dbg("Final DUTY_SEL=%d, DUTY=%d, rx window size=%d\n",
max_duty_sel, max_duty, max_win_size);
}
@ -673,18 +674,18 @@ void dual_rank_rx_datlat_cal(u32 channel,
clrbits32(&ch[channel].ao_regs->rkcfg, MASK_RKCFG_RKSWAP_EN);
/* output dle setting of rank 0 and 1 */
dramc_dbg_msg("[DLE] Rank 0 DLE calibrated setting = %xh.\n"
dramc_dbg("[DLE] Rank 0 DLE calibrated setting = %xh.\n"
"[DLE] Rank 1 DLE calibrated setting = %xh.\n",
r0_dle_setting, r1_dle_setting);
if (r1_dle_setting < r0_dle_setting) {
/* compare dle setting of two ranks */
dramc_dbg_msg("[DLE] rank 0 > rank 1. set to rank 0.\n");
dramc_dbg("[DLE] rank 0 > rank 1. set to rank 0.\n");
/* case 1: set rank 0 dle setting */
set_dle_factor(channel, r0_dle_setting);
} else {
/* compare dle setting of two ranks */
dramc_dbg_msg("[DLE] rank 0 < rank 1. use rank 1.\n");
dramc_dbg("[DLE] rank 0 < rank 1. use rank 1.\n");
/* case 2: set rank 1 dle setting */
set_dle_factor(channel, r1_dle_setting);
}
@ -696,10 +697,10 @@ u8 rx_datlat_cal(u32 channel, u8 rank,
u8 i, best_step;
u32 err[DLE_TEST_NUM];
dramc_dbg_msg("=========================================\n");
dramc_dbg_msg("[Channel %d] [Rank %d] DATLAT calibration\n",
dramc_dbg("=========================================\n");
dramc_dbg("[Channel %d] [Rank %d] DATLAT calibration\n",
channel, rank);
dramc_dbg_msg("=========================================\n");
dramc_dbg("=========================================\n");
clrbits32(&ch[channel].ao_regs->mckdly,
0x11 << MCKDLY_DQIENQKEND_SHIFT |
@ -736,7 +737,7 @@ u8 rx_datlat_cal(u32 channel, u8 rank,
*/
set_dle_factor(channel, best_step);
dramc_dbg_msg("[DLE] adjusted value = %#x\n", best_step);
dramc_dbg("[DLE] adjusted value = %#x\n", best_step);
return best_step;
}
@ -754,7 +755,7 @@ void tx_delay_for_wrleveling(u32 channel,
index = i / DQS_BIT_NUMBER;
if (i % DQS_BIT_NUMBER == 0)
dramc_dbg_msg("DQS%d: %d\n", index,
dramc_dbg("DQS%d: %d\n", index,
wrlevel_dqs_dly[channel][index]);
if (max_dqsdly_byte[index] <= wrlevel_dqs_dly[channel][index]) {
@ -872,9 +873,9 @@ static void set_rx_best_dly_factor(u32 channel,
write32(&ch[channel].ao_regs->r0deldly, value);
write32(&ch[channel].ao_regs->r1deldly, value);
dramc_dbg_msg("[RX] DQS Reg R0DELDLY=%xh\n",
dramc_dbg("[RX] DQS Reg R0DELDLY=%xh\n",
read32(&ch[channel].ao_regs->r0deldly));
dramc_dbg_msg("[RX] DQS Reg R1DELDLY=%xh\n",
dramc_dbg("[RX] DQS Reg R1DELDLY=%xh\n",
read32(&ch[channel].ao_regs->r1deldly));
for (i = 0; i < DATA_WIDTH_32BIT; i += 4) {
@ -885,7 +886,7 @@ static void set_rx_best_dly_factor(u32 channel,
(((u32)dqdqs_perbit_dly[i + 3].best_dqdly) << 24);
write32(&ch[channel].ao_regs->dqidly[i / 4], value);
dramc_dbg_msg("[RX] DQ DQIDLY%d = %xh\n", (i + 4) / 4, value);
dramc_dbg("[RX] DQ DQIDLY%d = %xh\n", (i + 4) / 4, value);
}
}
@ -901,7 +902,7 @@ static void set_tx_best_dly_factor(u32 channel,
}
write32(&ch[channel].ddrphy_regs->padctl3, value);
dramc_dbg_msg("[TX] DQS PADCTL3 Reg = %#x\n", value);
dramc_dbg("[TX] DQS PADCTL3 Reg = %#x\n", value);
/* DQ delay */
for (bit = 0; bit < DATA_WIDTH_32BIT; bit++) {
@ -916,7 +917,7 @@ static void set_tx_best_dly_factor(u32 channel,
/* each register is with 8 DQ */
if ((bit + 1) % DQS_BIT_NUMBER == 0) {
write32(&ch[channel].ddrphy_regs->dqodly[dqs_index], value);
dramc_dbg_msg("[TX] DQ DQ0DLY%d = %xh\n",
dramc_dbg("[TX] DQ DQ0DLY%d = %xh\n",
dqs_index + 1, value);
}
}
@ -929,7 +930,7 @@ static void set_tx_best_dly_factor(u32 channel,
value += (((u32)ave_dqdly_byte[bit]) << (4 * bit));
}
write32(&ch[channel].ddrphy_regs->padctl2, value);
dramc_dbg_msg("[TX] DQM PADCTL2 Reg = %#x\n", value);
dramc_dbg("[TX] DQM PADCTL2 Reg = %#x\n", value);
}
void perbit_window_cal(u32 channel, u8 type)
@ -940,7 +941,7 @@ void perbit_window_cal(u32 channel, u8 type)
struct dqs_perbit_dly dqdqs_perbit_dly[DQ_DATA_WIDTH];
dramc_dbg_msg("\n[Channel %d] %s DQ/DQS per bit :\n",
dramc_dbg("\n[Channel %d] %s DQ/DQS per bit :\n",
channel, (type == TX_WIN)? "TX": "RX");
if (type == TX_WIN)
@ -967,13 +968,13 @@ void perbit_window_cal(u32 channel, u8 type)
/* 1. set DQS delay to 0 first */
set_dly_factor(channel, STAGE_HOLD, type, FIRST_DQS_DELAY);
dramc_dbg_msg("----------------------------------"
dramc_dbg("----------------------------------"
"--------------------\n");
dramc_dbg_msg("Start DQ delay to find pass range,"
dramc_dbg("Start DQ delay to find pass range,"
"DQS delay fixed to %#x...\n", FIRST_DQS_DELAY);
dramc_dbg_msg("----------------------------------"
dramc_dbg("----------------------------------"
"-------------------\n");
dramc_dbg_msg("x-axis is bit #; y-axis is DQ delay (%d~%d)\n",
dramc_dbg("x-axis is bit #; y-axis is DQ delay (%d~%d)\n",
FIRST_DQ_DELAY, MAX_DQDLY_TAPS - 1);
/* delay DQ from 0 to 15 to get the setup time */
@ -988,12 +989,12 @@ void perbit_window_cal(u32 channel, u8 type)
dramk_check_dq_win(&(dqdqs_perbit_dly[bit]), dly,
MAX_DQDLY_TAPS - 1, fail_bit);
if (fail_bit == 0) {
dramc_dbg_msg("o");
dramc_dbg("o");
} else {
dramc_dbg_msg("x");
dramc_dbg("x");
}
}
dramc_dbg_msg("\n");
dramc_dbg("\n");
}
/* 2. set DQ delay to 0 */
@ -1002,13 +1003,13 @@ void perbit_window_cal(u32 channel, u8 type)
/* DQS delay taps: tx and rx are 16 and 64 taps */
max_dqs_taps = (type == TX_WIN)? MAX_TX_DQSDLY_TAPS: MAX_RX_DQSDLY_TAPS;
dramc_dbg_msg("-----------------------------------"
dramc_dbg("-----------------------------------"
"-------------------\n");
dramc_dbg_msg("Start DQS delay to find pass range,"
dramc_dbg("Start DQS delay to find pass range,"
"DQ delay fixed to %#x...\n", FIRST_DQ_DELAY);
dramc_dbg_msg("------------------------------------"
dramc_dbg("------------------------------------"
"------------------\n");
dramc_dbg_msg("x-axis is bit #; y-axis is DQS delay (%d~%d)\n",
dramc_dbg("x-axis is bit #; y-axis is DQS delay (%d~%d)\n",
FIRST_DQS_DELAY + 1, max_dqs_taps - 1);
/* delay DQS to get the hold time, dq_dly = dqs_dly = 0 is counted */
@ -1024,22 +1025,22 @@ void perbit_window_cal(u32 channel, u8 type)
dramk_check_dqs_win(&(dqdqs_perbit_dly[bit]), dly,
max_dqs_taps - 1, fail_bit);
if (fail_bit == 0) {
dramc_dbg_msg("o");
dramc_dbg("o");
} else {
dramc_dbg_msg("x");
dramc_dbg("x");
}
}
dramc_dbg_msg("\n");
dramc_dbg("\n");
}
/* 3 calculate dq and dqs time */
dramc_dbg_msg("-------------------------------"
dramc_dbg("-------------------------------"
"-----------------------\n");
dramc_dbg_msg("Start calculate dq time and dqs "
dramc_dbg("Start calculate dq time and dqs "
"time:\n");
dramc_dbg_msg("Find max DQS delay per byte / "
dramc_dbg("Find max DQS delay per byte / "
"Adjust DQ delay to align DQS...\n");
dramc_dbg_msg("--------------------------------"
dramc_dbg("--------------------------------"
"----------------------\n");
/* As per byte, check max DQS delay in 8-bit.
@ -1059,7 +1060,7 @@ void perbit_window_cal(u32 channel, u8 type)
&max_dqsdly_byte[index]);
if ((i + 1) % DQS_BIT_NUMBER == 0)
dramc_dbg_msg("----separate line----\n");
dramc_dbg("----separate line----\n");
}
for (i = 0; i < DATA_WIDTH_32BIT; i++) {
@ -1088,34 +1089,34 @@ void perbit_window_cal(u32 channel, u8 type)
if (fail == 1) /* error handling */
die("fail on %s()\n", __func__);
dramc_dbg_msg("==================================================\n");
dramc_dbg_msg(" dramc_perbit_window_swcal:\n");
dramc_dbg_msg(" channel=%d(0:cha, 1:chb)\n", channel);
dramc_dbg_msg(" bus width=%d\n", DATA_WIDTH_32BIT);
dramc_dbg_msg("==================================================\n");
dramc_dbg_msg("DQS Delay :\n DQS0 = %d DQS1 = %d DQS2 = %d DQS3 = %d\n",
dramc_dbg("==================================================\n");
dramc_dbg(" dramc_perbit_window_swcal:\n");
dramc_dbg(" channel=%d(0:cha, 1:chb)\n", channel);
dramc_dbg(" bus width=%d\n", DATA_WIDTH_32BIT);
dramc_dbg("==================================================\n");
dramc_dbg("DQS Delay :\n DQS0 = %d DQS1 = %d DQS2 = %d DQS3 = %d\n",
max_dqsdly_byte[0], max_dqsdly_byte[1],
max_dqsdly_byte[2], max_dqsdly_byte[3]);
if (type == TX_WIN)
dramc_dbg_msg("DQM Delay :\n"
dramc_dbg("DQM Delay :\n"
"DQM0 = %d DQM1 = %d DQM2 = %d DQM3 = %d\n",
ave_dqdly_byte[0], ave_dqdly_byte[1],
ave_dqdly_byte[2], ave_dqdly_byte[3]);
dramc_dbg_msg("DQ Delay :\n");
dramc_dbg("DQ Delay :\n");
for (i = 0; i < DATA_WIDTH_32BIT; i++) {
dramc_dbg_msg("DQ%d = %d ", i, dqdqs_perbit_dly[i].best_dqdly);
dramc_dbg("DQ%d = %d ", i, dqdqs_perbit_dly[i].best_dqdly);
if (((i + 1) % 4) == 0)
dramc_dbg_msg("\n");
dramc_dbg("\n");
}
dramc_dbg_msg("____________________________________"
dramc_dbg("____________________________________"
"____________________________________\n");
if (type == TX_WIN) {
/* Add CLK to DQS/DQ skew after write leveling */
dramc_dbg_msg("Add CLK to DQS/DQ skew based on write leveling.\n");
dramc_dbg("Add CLK to DQS/DQ skew based on write leveling.\n");
/* this subroutine add clk delay to DQS/DQ after WL */
tx_delay_for_wrleveling(channel, dqdqs_perbit_dly,
max_dqsdly_byte, ave_dqdly_byte);

1
src/soc/mediatek/mt8173/emi.c
View File

@ -6,6 +6,7 @@
#include <soc/dramc_common.h>
#include <soc/dramc_register.h>
#include <soc/dramc_pi_api.h>
#include <soc/dramc_soc.h>
#include <soc/mt6391.h>
#include <soc/pmic_wrap.h>
#include <soc/pll.h>

8
src/soc/mediatek/mt8173/include/soc/dramc_pi_api.h
View File

@ -3,6 +3,8 @@
#ifndef _DRAMC_PI_API_H
#define _DRAMC_PI_API_H
#include <soc/dramc_common.h>
#include <soc/dramc_soc.h>
#include <soc/emi.h>
#include <console/console.h>
@ -165,10 +167,4 @@ void dramk_check_dq_win(struct dqs_perbit_dly *p, u8 dly_step, u8 last_step, u32
void tx_delay_for_wrleveling(u32 channel, struct dqs_perbit_dly *dqdqs_perbit_dly,
u8 *ave_dqdly_byte, u8 *max_dqsdly_byte);
#if CONFIG(DEBUG_DRAM)
#define dramc_dbg_msg(_x_...) printk(BIOS_DEBUG, _x_)
#else
#define dramc_dbg_msg(_x_...)
#endif
#endif /* _PI_API_H */

4
src/soc/mediatek/mt8173/include/soc/dramc_common.h → src/soc/mediatek/mt8173/include/soc/dramc_soc.h
View File

@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef _DRAMC_COMMON_H_
#define _DRAMC_COMMON_H_
#ifndef _DRAMC_SOC_H_
#define _DRAMC_SOC_H_
enum {
CHANNEL_A = 0,

1
src/soc/mediatek/mt8173/include/soc/emi.h
View File

@ -4,6 +4,7 @@
#define SOC_MEDIATEK_MT8173_EMI_H
#include <soc/dramc_common.h>
#include <soc/dramc_soc.h>
#include <types.h>
/* DDR type */

7
src/soc/mediatek/mt8183/Kconfig
View File

@ -6,6 +6,7 @@ config SOC_MEDIATEK_MT8183
select ARCH_ROMSTAGE_ARMV8_64
select ARCH_VERSTAGE_ARMV8_64
select ARM64_USE_ARM_TRUSTED_FIRMWARE
select HAVE_DEBUG_RAM_SETUP
select HAVE_UART_SPECIAL
select COMPRESS_BOOTBLOCK
select SOC_MEDIATEK_COMMON
@ -22,12 +23,6 @@ config VBOOT
select VBOOT_SEPARATE_VERSTAGE
select VBOOT_RETURN_FROM_VERSTAGE
config DEBUG_DRAM
bool "Output verbose DRAM related debug messages"
default n
help
This option enables additional DRAM related debug messages.
config MT8183_DRAM_EMCP
bool
default n

9
src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h
View File

@ -4,17 +4,10 @@
#define _DRAMC_PI_API_MT8183_H
#include <types.h>
#include <soc/dramc_common.h>
#include <soc/emi.h>
#include <console/console.h>
#define dramc_err(_x_...) printk(BIOS_ERR, _x_)
#define dramc_show(_x_...) printk(BIOS_INFO, _x_)
#if CONFIG(DEBUG_DRAM)
#define dramc_dbg(_x_...) printk(BIOS_DEBUG, _x_)
#else
#define dramc_dbg(_x_...)
#endif
#define DATLAT_TAP_NUMBER 32
#define HW_REG_SHUFFLE_MAX 4