mb/asus/p8h61-m_pro: Add new mainboard
Tested with GRUB 2.02 as a payload, booting Arch Linux as well as Debian. This code is based on the output of autoport as well as other mainboards supported in coreboot already. Working: - Serial port I/O - S3 suspend/resume. Untested with SeaBIOS since it failed to resume on a similar board. It is likely to be due to low memory corruption, but I have not worked on it. - USB ports and headers - USB3 ports attached to the ASM1042 controller. SeaBIOS can boot from them, and it is likely GRUB can detect devices on those ports as well. The chip has a small SPI flash nearby, which seems to hold an Option ROM. - Gigabit Ethernet - Integrated graphics (libgfxinit) - VGA BIOS for integrated graphics init - PCIe x16 graphics - PCIe x1 - SATA controller - Hardware Monitor - Fan Control (fancontrol on linux works well) - Native raminit - flashrom, using the internal programmer. Tested with coreboot, as well as with the vendor firmware. - NVRAM settings. Only debug_level has been tested. Untested: - DVI port. It can detect a "fake" display, that is, an EEPROM connected to the DVI port. Thus, gma-mainboard.ads has been setup accordingly. - PS/2 port. - Audio: Only rear output (green) has been tested. - EHCI debug. - Parallel port header. - Non-Linux OSes - ACPI thermal zone and fan control (probably not working) Not working: - Booting from devices attached to the ASM1061 controller. Devices on ports work fine once Linux has loaded. - Any SATA devices with Tianocore (payload issue) Change-Id: I7e89ebe43a2e1ff0308f4876e98bbf2f5a0d85f2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/26419 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons
Nico Huber
parent
fe2510764d
commit
65ddbb720b
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2018 Angel Pons <th3fanbus@gmail.com>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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if BOARD_ASUS_P8H61_M_PRO
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select ARCH_X86
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select BOARD_ROMSIZE_KB_4096
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select CPU_INTEL_SOCKET_LGA1155
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select NORTHBRIDGE_INTEL_IVYBRIDGE
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select SERIRQ_CONTINUOUS_MODE
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select SOUTHBRIDGE_INTEL_BD82X6X
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select USE_NATIVE_RAMINIT
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select SUPERIO_NUVOTON_NCT6776
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select MAINBOARD_HAS_LIBGFXINIT
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select HAVE_OPTION_TABLE
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select HAVE_CMOS_DEFAULT
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select DRIVERS_ASMEDIA_ASPM_BLACKLIST
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config HAVE_IFD_BIN
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bool
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default n
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config MAINBOARD_DIR
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string
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default asus/p8h61-m_pro
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config MAINBOARD_PART_NUMBER
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string
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default "P8H61-M PRO"
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config VGA_BIOS_FILE
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string
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default "pci8086,0152.rom"
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config VGA_BIOS_ID
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string
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default "8086,0152"
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config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
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hex
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default 0x844d
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config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
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hex
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default 0x1043
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config MAX_CPUS
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int
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default 8
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endif # BOARD_ASUS_P8H61_M_PRO
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@ -0,0 +1,2 @@
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config BOARD_ASUS_P8H61_M_PRO
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bool "P8H61-M PRO"
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@ -0,0 +1,3 @@
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romstage-y += gpio.c
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ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* The _PTS method (Prepare To Sleep) is called before the OS is
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* entering a sleep state. The sleep state number is passed in Arg0
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*/
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Method(_PTS,1)
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{
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}
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/* The _WAK method is called on system wakeup */
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Method(_WAK,1)
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{
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Return(Package(){0,0})
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}
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <drivers/pc80/pc/ps2_controller.asl>
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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* Copyright (C) 2014 Vladimir Serbinenko
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* Copyright (C) 2018 Angel Pons <th3fanbus@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <southbridge/intel/bd82x6x/nvs.h>
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void acpi_create_gnvs(global_nvs_t *gnvs)
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{
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/* Disable USB ports in S3 by default */
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gnvs->s3u0 = 0;
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gnvs->s3u1 = 0;
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/* Disable USB ports in S5 by default */
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gnvs->s5u0 = 0;
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gnvs->s5u1 = 0;
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gnvs->tcrt = 100;
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gnvs->tpsv = 90;
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}
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@ -0,0 +1,6 @@
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Category: desktop
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Board URL: https://www.asus.com/Motherboards/P8H61M_PRO
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ROM package: DIP-8
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ROM protocol: SPI
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ROM socketed: y
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Flashrom support: y
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boot_option=Fallback
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debug_level=Debug
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power_on_after_fail=Enable
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nmi=Enable
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sata_mode=AHCI
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gfx_uma_size=32M
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007-2008 coresystems GmbH
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## Copyright (C) 2014 Vladimir Serbinenko
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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# -----------------------------------------------------------------
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entries
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# -----------------------------------------------------------------
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# Status Register A
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# -----------------------------------------------------------------
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# Status Register B
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# -----------------------------------------------------------------
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# Status Register C
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#96 4 r 0 status_c_rsvd
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#100 1 r 0 uf_flag
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#101 1 r 0 af_flag
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#102 1 r 0 pf_flag
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#103 1 r 0 irqf_flag
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# -----------------------------------------------------------------
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# Status Register D
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#104 7 r 0 status_d_rsvd
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#111 1 r 0 valid_cmos_ram
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# -----------------------------------------------------------------
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# Diagnostic Status Register
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#112 8 r 0 diag_rsvd1
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# -----------------------------------------------------------------
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0 120 r 0 reserved_memory
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#120 264 r 0 unused
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# -----------------------------------------------------------------
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# RTC_BOOT_BYTE (coreboot hardcoded)
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384 1 e 4 boot_option
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388 4 h 0 reboot_counter
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#390 2 r 0 unused?
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# -----------------------------------------------------------------
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# coreboot config options: console
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#392 3 r 0 unused
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395 4 e 6 debug_level
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#399 1 r 0 unused
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# coreboot config options: southbridge
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408 1 e 1 nmi
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409 2 e 7 power_on_after_fail
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#411 10 r 0 unused
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421 1 e 9 sata_mode
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#422 2 r 0 unused
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# coreboot config options: cpu
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#425 7 r 0 unused
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# coreboot config options: northbridge
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432 3 e 11 gfx_uma_size
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#435 549 r 0 unused
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# coreboot config options: check sums
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984 16 h 0 check_sum
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# -----------------------------------------------------------------
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enumerations
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#ID value text
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1 0 Disable
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1 1 Enable
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4 0 Fallback
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4 1 Normal
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6 0 Emergency
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6 1 Alert
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6 2 Critical
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6 3 Error
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6 4 Warning
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6 5 Notice
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6 6 Info
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6 7 Debug
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6 8 Spew
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7 0 Disable
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7 1 Enable
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7 2 Keep
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9 0 AHCI
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9 1 IDE
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11 0 32M
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11 1 64M
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11 2 96M
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11 3 128M
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11 4 160M
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11 5 192M
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11 6 224M
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# -----------------------------------------------------------------
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checksums
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checksum 392 439 984
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@ -0,0 +1,126 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2018 Angel Pons <th3fanbus@gmail.com>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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chip northbridge/intel/sandybridge
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register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }"
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register "gfx.ndid" = "3"
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device cpu_cluster 0x0 on
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chip cpu/intel/socket_LGA1155
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device lapic 0x0 on
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end
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end
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chip cpu/intel/model_206ax
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register "c1_acpower" = "1"
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register "c1_battery" = "1"
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register "c2_acpower" = "3"
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register "c2_battery" = "3"
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register "c3_acpower" = "5"
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register "c3_battery" = "5"
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device lapic 0xacac off
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end
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end
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end
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register "pci_mmio_size" = "2048"
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device domain 0x0 on
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chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
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register "c2_latency" = "0x0065"
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register "docking_supported" = "0"
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register "gen1_dec" = "0x000c0291" # HWM
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register "p_cnt_throttling_supported" = "0"
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register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
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register "sata_interface_speed_support" = "0x3"
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register "sata_port_map" = "0x33"
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register "spi_lvscc" = "0x2005"
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register "spi_uvscc" = "0x2005"
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT
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device pci 19.0 off end # Intel Gigabit Ethernet
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device pci 1a.0 on end # USB2 EHCI #2
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device pci 1b.0 on end # High Definition Audio Audio controller
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device pci 1c.0 on end # PCIe x1 Port (PCIEX1_1)
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device pci 1c.1 on end # PCIe x1 Port (PCIEX1_2)
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device pci 1c.2 on end # Realtek RTL8111E Ethernet Controller
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device pci 1c.3 on end # ASMedia ASM1042 USB3 Controller
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device pci 1c.4 on end # PCIe x1 Port, x16 size (PCIEX16_2)
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device pci 1c.5 on end # ASMedia ASM1062 SATA Controller
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device pci 1c.6 off end # Unused PCIe Port
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device pci 1c.7 off end # Unused PCIe Port
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device pci 1d.0 on end # USB2 EHCI #1
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device pci 1e.0 off end # PCI bridge
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device pci 1f.0 on # LPC bridge
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chip superio/nuvoton/nct6776
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device pnp 2e.0 off end # Floppy
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device pnp 2e.1 on # Parallel port
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io 0x60 = 0x378
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irq 0x70 = 5
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drq 0x74 = 4
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irq 0xf0 = 0x3c
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end
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device pnp 2e.2 on # COM1
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io 0x60 = 0x3f8
|
||||||
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irq 0x70 = 4
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||||||
|
end
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device pnp 2e.3 off end # COM2, IR
|
||||||
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device pnp 2e.5 on # Keyboard
|
||||||
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io 0x60 = 0x60
|
||||||
|
io 0x62 = 0x64
|
||||||
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irq 0x70 = 1
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||||||
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irq 0x72 = 12
|
||||||
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end
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||||||
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device pnp 2e.6 off end # CIR
|
||||||
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device pnp 2e.7 off end # GPIO6-9
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||||||
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device pnp 2e.8 off end # WDT1, GPIO0, GPIO1, GPIOA
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device pnp 2e.9 off end # GPIO2-5
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||||||
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device pnp 2e.a on # ACPI
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||||||
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irq 0xe5 = 0x06
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||||||
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irq 0xe6 = 0x0c
|
||||||
|
irq 0xe7 = 0x11
|
||||||
|
irq 0xf0 = 0x20
|
||||||
|
irq 0xf2 = 0x5d
|
||||||
|
end
|
||||||
|
device pnp 2e.b on # HWM, LED
|
||||||
|
io 0x60 = 0x0290
|
||||||
|
io 0x62 = 0x0200
|
||||||
|
end
|
||||||
|
device pnp 2e.d on end # VID
|
||||||
|
device pnp 2e.e off end # CIR WAKE-UP
|
||||||
|
device pnp 2e.f on # GPIO Push-Pull or Open-drain
|
||||||
|
irq 0xf0 = 0x9d
|
||||||
|
end
|
||||||
|
device pnp 2e.14 on end # SVID
|
||||||
|
device pnp 2e.16 on # Deep Sleep
|
||||||
|
io 0x30 = 0x20
|
||||||
|
end
|
||||||
|
device pnp 2e.17 on # GPIOA
|
||||||
|
irq 0xe0 = 0xff
|
||||||
|
irq 0xe1 = 0xff
|
||||||
|
irq 0xe2 = 0xff
|
||||||
|
irq 0xe3 = 0xff
|
||||||
|
irq 0xe5 = 0xff
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
device pci 1f.2 on end # SATA Controller 1
|
||||||
|
device pci 1f.3 on end # SMBus
|
||||||
|
device pci 1f.5 off end # SATA Controller 2
|
||||||
|
device pci 1f.6 off end # Thermal
|
||||||
|
end
|
||||||
|
device pci 00.0 on end # Host bridge
|
||||||
|
device pci 01.0 on end # PCIe bridge for discrete graphics (PCIEX16_1)
|
||||||
|
device pci 02.0 on end # Internal graphics VGA controller
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
@ -0,0 +1,44 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2018 Angel Pons <th3fanbus@gmail.com>
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; version 2 of the License.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
|
||||||
|
DefinitionBlock(
|
||||||
|
"dsdt.aml",
|
||||||
|
"DSDT",
|
||||||
|
0x03, // DSDT revision: ACPI v3.0
|
||||||
|
"COREv4", // OEM id
|
||||||
|
"COREBOOT", // OEM table id
|
||||||
|
0x20141018 // OEM revision
|
||||||
|
)
|
||||||
|
{
|
||||||
|
// Some generic macros
|
||||||
|
#include "acpi/platform.asl"
|
||||||
|
#include "acpi/superio.asl"
|
||||||
|
#include <cpu/intel/model_206ax/acpi/cpu.asl>
|
||||||
|
#include <southbridge/intel/bd82x6x/acpi/platform.asl>
|
||||||
|
|
||||||
|
/* global NVS and variables. */
|
||||||
|
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
|
||||||
|
#include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
|
||||||
|
|
||||||
|
Scope (\_SB) {
|
||||||
|
Device (PCI0)
|
||||||
|
{
|
||||||
|
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
|
||||||
|
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
|
||||||
|
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,34 @@
|
||||||
|
--
|
||||||
|
-- This file is part of the coreboot project.
|
||||||
|
--
|
||||||
|
-- Copyright (C) 2018 Angel Pons <th3fanbus@gmail.com>
|
||||||
|
--
|
||||||
|
-- This program is free software; you can redistribute it and/or modify
|
||||||
|
-- it under the terms of the GNU General Public License as published by
|
||||||
|
-- the Free Software Foundation; version 2 of the License.
|
||||||
|
--
|
||||||
|
-- This program is distributed in the hope that it will be useful,
|
||||||
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
-- GNU General Public License for more details.
|
||||||
|
--
|
||||||
|
|
||||||
|
with HW.GFX.GMA;
|
||||||
|
with HW.GFX.GMA.Display_Probing;
|
||||||
|
|
||||||
|
use HW.GFX.GMA;
|
||||||
|
use HW.GFX.GMA.Display_Probing;
|
||||||
|
|
||||||
|
private package GMA.Mainboard is
|
||||||
|
|
||||||
|
-- For a three-pipe setup, bandwidth is shared between the 2nd and
|
||||||
|
-- the 3rd pipe. Thus, probe ports that likely have a high-resolution
|
||||||
|
-- display attached first.
|
||||||
|
|
||||||
|
ports : constant Port_List :=
|
||||||
|
(HDMI3, -- mainboard HDMI port
|
||||||
|
HDMI1, -- mainboard DVI-D port
|
||||||
|
Analog,
|
||||||
|
others => Disabled);
|
||||||
|
|
||||||
|
end GMA.Mainboard;
|
||||||
|
|
@ -0,0 +1,196 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2018 Angel Pons <th3fanbus@gmail.com>
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; version 2 of the License.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <southbridge/intel/common/gpio.h>
|
||||||
|
|
||||||
|
static const struct pch_gpio_set1 pch_gpio_set1_mode = {
|
||||||
|
.gpio0 = GPIO_MODE_GPIO,
|
||||||
|
.gpio1 = GPIO_MODE_GPIO,
|
||||||
|
.gpio2 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio3 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio4 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio5 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio6 = GPIO_MODE_GPIO,
|
||||||
|
.gpio7 = GPIO_MODE_GPIO,
|
||||||
|
.gpio8 = GPIO_MODE_GPIO,
|
||||||
|
.gpio9 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio10 = GPIO_MODE_GPIO,
|
||||||
|
.gpio11 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio12 = GPIO_MODE_GPIO,
|
||||||
|
.gpio13 = GPIO_MODE_GPIO,
|
||||||
|
.gpio14 = GPIO_MODE_GPIO,
|
||||||
|
.gpio15 = GPIO_MODE_GPIO,
|
||||||
|
.gpio16 = GPIO_MODE_GPIO,
|
||||||
|
.gpio17 = GPIO_MODE_GPIO,
|
||||||
|
.gpio18 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio19 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio20 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio21 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio22 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio23 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio24 = GPIO_MODE_GPIO,
|
||||||
|
.gpio25 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio26 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio27 = GPIO_MODE_GPIO,
|
||||||
|
.gpio28 = GPIO_MODE_GPIO,
|
||||||
|
.gpio29 = GPIO_MODE_GPIO,
|
||||||
|
.gpio30 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio31 = GPIO_MODE_GPIO,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct pch_gpio_set1 pch_gpio_set1_direction = {
|
||||||
|
.gpio0 = GPIO_DIR_OUTPUT,
|
||||||
|
.gpio1 = GPIO_DIR_INPUT,
|
||||||
|
.gpio6 = GPIO_DIR_INPUT,
|
||||||
|
.gpio7 = GPIO_DIR_INPUT,
|
||||||
|
.gpio8 = GPIO_DIR_INPUT,
|
||||||
|
.gpio10 = GPIO_DIR_INPUT,
|
||||||
|
.gpio12 = GPIO_DIR_INPUT,
|
||||||
|
.gpio13 = GPIO_DIR_INPUT,
|
||||||
|
.gpio14 = GPIO_DIR_INPUT,
|
||||||
|
.gpio15 = GPIO_DIR_OUTPUT,
|
||||||
|
.gpio16 = GPIO_DIR_INPUT,
|
||||||
|
.gpio17 = GPIO_DIR_INPUT,
|
||||||
|
.gpio24 = GPIO_DIR_OUTPUT,
|
||||||
|
.gpio27 = GPIO_DIR_INPUT,
|
||||||
|
.gpio28 = GPIO_DIR_OUTPUT,
|
||||||
|
.gpio29 = GPIO_DIR_INPUT,
|
||||||
|
.gpio31 = GPIO_DIR_OUTPUT,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct pch_gpio_set1 pch_gpio_set1_level = {
|
||||||
|
.gpio0 = GPIO_LEVEL_LOW,
|
||||||
|
.gpio15 = GPIO_LEVEL_LOW,
|
||||||
|
.gpio24 = GPIO_LEVEL_LOW,
|
||||||
|
.gpio28 = GPIO_LEVEL_LOW,
|
||||||
|
.gpio31 = GPIO_LEVEL_HIGH,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct pch_gpio_set1 pch_gpio_set1_reset = {
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct pch_gpio_set1 pch_gpio_set1_invert = {
|
||||||
|
.gpio1 = GPIO_INVERT,
|
||||||
|
.gpio6 = GPIO_INVERT,
|
||||||
|
.gpio13 = GPIO_INVERT,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct pch_gpio_set1 pch_gpio_set1_blink = {
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct pch_gpio_set2 pch_gpio_set2_mode = {
|
||||||
|
.gpio32 = GPIO_MODE_GPIO,
|
||||||
|
.gpio33 = GPIO_MODE_GPIO,
|
||||||
|
.gpio34 = GPIO_MODE_GPIO,
|
||||||
|
.gpio35 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio36 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio37 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio38 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio39 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio40 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio41 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio42 = GPIO_MODE_GPIO,
|
||||||
|
.gpio43 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio44 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio45 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio46 = GPIO_MODE_GPIO,
|
||||||
|
.gpio47 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio48 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio49 = GPIO_MODE_GPIO,
|
||||||
|
.gpio50 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio51 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio52 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio53 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio54 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio55 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio56 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio57 = GPIO_MODE_GPIO,
|
||||||
|
.gpio58 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio59 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio60 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio61 = GPIO_MODE_GPIO,
|
||||||
|
.gpio62 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio63 = GPIO_MODE_NATIVE,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct pch_gpio_set2 pch_gpio_set2_direction = {
|
||||||
|
.gpio32 = GPIO_DIR_OUTPUT,
|
||||||
|
.gpio33 = GPIO_DIR_OUTPUT,
|
||||||
|
.gpio34 = GPIO_DIR_INPUT,
|
||||||
|
.gpio42 = GPIO_DIR_INPUT,
|
||||||
|
.gpio46 = GPIO_DIR_INPUT,
|
||||||
|
.gpio49 = GPIO_DIR_INPUT,
|
||||||
|
.gpio57 = GPIO_DIR_INPUT,
|
||||||
|
.gpio61 = GPIO_DIR_OUTPUT,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct pch_gpio_set2 pch_gpio_set2_level = {
|
||||||
|
.gpio32 = GPIO_LEVEL_HIGH,
|
||||||
|
.gpio33 = GPIO_LEVEL_HIGH,
|
||||||
|
.gpio61 = GPIO_LEVEL_HIGH,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct pch_gpio_set2 pch_gpio_set2_reset = {
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct pch_gpio_set3 pch_gpio_set3_mode = {
|
||||||
|
.gpio64 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio65 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio66 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio67 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio68 = GPIO_MODE_GPIO,
|
||||||
|
.gpio69 = GPIO_MODE_GPIO,
|
||||||
|
.gpio70 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio71 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio72 = GPIO_MODE_GPIO,
|
||||||
|
.gpio73 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio74 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio75 = GPIO_MODE_NATIVE,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct pch_gpio_set3 pch_gpio_set3_direction = {
|
||||||
|
.gpio68 = GPIO_DIR_INPUT,
|
||||||
|
.gpio69 = GPIO_DIR_INPUT,
|
||||||
|
.gpio72 = GPIO_DIR_INPUT,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct pch_gpio_set3 pch_gpio_set3_level = {
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct pch_gpio_set3 pch_gpio_set3_reset = {
|
||||||
|
};
|
||||||
|
|
||||||
|
const struct pch_gpio_map mainboard_gpio_map = {
|
||||||
|
.set1 = {
|
||||||
|
.mode = &pch_gpio_set1_mode,
|
||||||
|
.direction = &pch_gpio_set1_direction,
|
||||||
|
.level = &pch_gpio_set1_level,
|
||||||
|
.blink = &pch_gpio_set1_blink,
|
||||||
|
.invert = &pch_gpio_set1_invert,
|
||||||
|
.reset = &pch_gpio_set1_reset,
|
||||||
|
},
|
||||||
|
.set2 = {
|
||||||
|
.mode = &pch_gpio_set2_mode,
|
||||||
|
.direction = &pch_gpio_set2_direction,
|
||||||
|
.level = &pch_gpio_set2_level,
|
||||||
|
.reset = &pch_gpio_set2_reset,
|
||||||
|
},
|
||||||
|
.set3 = {
|
||||||
|
.mode = &pch_gpio_set3_mode,
|
||||||
|
.direction = &pch_gpio_set3_direction,
|
||||||
|
.level = &pch_gpio_set3_level,
|
||||||
|
.reset = &pch_gpio_set3_reset,
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
@ -0,0 +1,86 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2018 Angel Pons <th3fanbus@gmail.com>
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; version 2 of the License.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <device/azalia_device.h>
|
||||||
|
|
||||||
|
const u32 cim_verb_data[] = {
|
||||||
|
0x10ec0887, /* Codec Vendor / Device ID: Realtek */
|
||||||
|
0x10438444, /* Subsystem ID */
|
||||||
|
|
||||||
|
0x0000000f, /* Number of 4 dword sets */
|
||||||
|
/* NID 0x01: Subsystem ID. */
|
||||||
|
AZALIA_SUBVENDOR(0x0, 0x10438444),
|
||||||
|
|
||||||
|
/* NID 0x11. */
|
||||||
|
AZALIA_PIN_CFG(0x0, 0x11, 0x99430140),
|
||||||
|
|
||||||
|
/* NID 0x12. */
|
||||||
|
AZALIA_PIN_CFG(0x0, 0x12, 0x411111f0),
|
||||||
|
|
||||||
|
/* NID 0x14. */
|
||||||
|
AZALIA_PIN_CFG(0x0, 0x14, 0x01014010),
|
||||||
|
|
||||||
|
/* NID 0x15. */
|
||||||
|
AZALIA_PIN_CFG(0x0, 0x15, 0x01011012),
|
||||||
|
|
||||||
|
/* NID 0x16. */
|
||||||
|
AZALIA_PIN_CFG(0x0, 0x16, 0x01016011),
|
||||||
|
|
||||||
|
/* NID 0x17. */
|
||||||
|
AZALIA_PIN_CFG(0x0, 0x17, 0x01012014),
|
||||||
|
|
||||||
|
/* NID 0x18. */
|
||||||
|
AZALIA_PIN_CFG(0x0, 0x18, 0x01a19850),
|
||||||
|
|
||||||
|
/* NID 0x19. */
|
||||||
|
AZALIA_PIN_CFG(0x0, 0x19, 0x02a19c60),
|
||||||
|
|
||||||
|
/* NID 0x1a. */
|
||||||
|
AZALIA_PIN_CFG(0x0, 0x1a, 0x0181305f),
|
||||||
|
|
||||||
|
/* NID 0x1b. */
|
||||||
|
AZALIA_PIN_CFG(0x0, 0x1b, 0x02214c20),
|
||||||
|
|
||||||
|
/* NID 0x1c. */
|
||||||
|
AZALIA_PIN_CFG(0x0, 0x1c, 0x411111f0),
|
||||||
|
|
||||||
|
/* NID 0x1d. */
|
||||||
|
AZALIA_PIN_CFG(0x0, 0x1d, 0x4005e601),
|
||||||
|
|
||||||
|
/* NID 0x1e. */
|
||||||
|
AZALIA_PIN_CFG(0x0, 0x1e, 0x01456130),
|
||||||
|
|
||||||
|
/* NID 0x1f. */
|
||||||
|
AZALIA_PIN_CFG(0x0, 0x1f, 0x411111f0),
|
||||||
|
0x80862805, /* Codec Vendor / Device ID: Intel */
|
||||||
|
0x80860101, /* Subsystem ID */
|
||||||
|
|
||||||
|
0x00000004, /* Number of 4 dword sets */
|
||||||
|
/* NID 0x01: Subsystem ID. */
|
||||||
|
AZALIA_SUBVENDOR(0x3, 0x80860101),
|
||||||
|
|
||||||
|
/* NID 0x05. */
|
||||||
|
AZALIA_PIN_CFG(0x3, 0x05, 0x58560010),
|
||||||
|
|
||||||
|
/* NID 0x06. */
|
||||||
|
AZALIA_PIN_CFG(0x3, 0x06, 0x58560020),
|
||||||
|
|
||||||
|
/* NID 0x07. */
|
||||||
|
AZALIA_PIN_CFG(0x3, 0x07, 0x18560030),
|
||||||
|
};
|
||||||
|
|
||||||
|
const u32 pc_beep_verbs[0] = {};
|
||||||
|
|
||||||
|
AZALIA_ARRAY_SIZES;
|
||||||
|
|
@ -0,0 +1,84 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2018 Angel Pons <th3fanbus@gmail.com>
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; version 2 of the License.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <northbridge/intel/sandybridge/raminit_native.h>
|
||||||
|
#include <northbridge/intel/sandybridge/sandybridge.h>
|
||||||
|
#include <southbridge/intel/bd82x6x/pch.h>
|
||||||
|
#include <superio/nuvoton/common/nuvoton.h>
|
||||||
|
#include <superio/nuvoton/nct6776/nct6776.h>
|
||||||
|
|
||||||
|
#define GLOBAL_DEV PNP_DEV(0x2e, 0)
|
||||||
|
#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1)
|
||||||
|
#define ACPI_DEV PNP_DEV(0x2e, NCT6776_ACPI)
|
||||||
|
|
||||||
|
void pch_enable_lpc(void)
|
||||||
|
{
|
||||||
|
/* Enable the Super IO */
|
||||||
|
pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN |
|
||||||
|
KBC_LPC_EN | LPT_LPC_EN | COMA_LPC_EN);
|
||||||
|
}
|
||||||
|
|
||||||
|
void mainboard_rcba_config(void)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
const struct southbridge_usb_port mainboard_usb_ports[] = {
|
||||||
|
{ 1, 0, 0 },
|
||||||
|
{ 1, 0, 0 },
|
||||||
|
{ 1, 0, 1 },
|
||||||
|
{ 1, 0, 1 },
|
||||||
|
{ 1, 0, 2 },
|
||||||
|
{ 1, 0, 2 },
|
||||||
|
{ 1, 0, 3 },
|
||||||
|
{ 1, 0, 3 },
|
||||||
|
{ 1, 0, 4 },
|
||||||
|
{ 1, 0, 4 },
|
||||||
|
{ 1, 0, 6 },
|
||||||
|
{ 1, 0, 5 },
|
||||||
|
{ 1, 0, 5 },
|
||||||
|
{ 1, 0, 6 },
|
||||||
|
};
|
||||||
|
|
||||||
|
void mainboard_early_init(int s3resume)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
void mainboard_config_superio(void)
|
||||||
|
{
|
||||||
|
/* Enable UART */
|
||||||
|
nuvoton_pnp_enter_conf_state(GLOBAL_DEV);
|
||||||
|
|
||||||
|
/* Select SIO pin states. */
|
||||||
|
pnp_write_config(GLOBAL_DEV, 0x1c, 0x83);
|
||||||
|
pnp_write_config(GLOBAL_DEV, 0x24, 0x30);
|
||||||
|
pnp_write_config(GLOBAL_DEV, 0x27, 0x40);
|
||||||
|
pnp_write_config(GLOBAL_DEV, 0x2a, 0x20);
|
||||||
|
|
||||||
|
/* Power RAM in S3. */
|
||||||
|
pnp_set_logical_device(ACPI_DEV);
|
||||||
|
pnp_write_config(ACPI_DEV, 0xe4, 0x10);
|
||||||
|
|
||||||
|
pnp_set_logical_device(SERIAL_DEV);
|
||||||
|
|
||||||
|
nuvoton_pnp_exit_conf_state(GLOBAL_DEV);
|
||||||
|
|
||||||
|
nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||||
|
}
|
||||||
|
|
||||||
|
void mainboard_get_spd(spd_raw_data *spd, bool id_only)
|
||||||
|
{
|
||||||
|
read_spd(&spd[0], 0x50, id_only);
|
||||||
|
read_spd(&spd[2], 0x52, id_only);
|
||||||
|
}
|
||||||
Loading…
Reference in New Issue