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soc/amd/common/block/spi/fch_spi_ctrl: Fix restricted command write 

The SPI_RESTRICTED_CMD register is not a PCI configuration register.  It
is memory mapped from the SPI bar.

Verified against PPR 55570 rev 3.16, PPR 56569 rev 3.03, and PPR 57243
rev 1.50

TEST=Compile tested only

Change-Id: I7c88aaea9ddac200644bb368be3bd4e9be47fd7b
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63305
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Fred Reitberger 2022-04-01 16:13:18 -04:00 committed by Martin Roth
parent 6a0e470197
commit 65f558f576
1 changed files with 1 additions and 1 deletions
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2
src/soc/amd/common/block/spi/fch_spi_ctrl.c
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@ -282,7 +282,7 @@ static int fch_spi_flash_protect(const struct spi_flash *flash, const struct reg
} }
/* Final steps to protect region */ /* Final steps to protect region */
pci_write_config32(SOC_LPC_DEV, SPI_RESTRICTED_CMD1, reg32); spi_write32(SPI_RESTRICTED_CMD1, reg32);
reg32 = spi_read32(SPI_CNTRL0); reg32 = spi_read32(SPI_CNTRL0);
reg32 &= ~SPI_ACCESS_MAC_ROM_EN; reg32 &= ~SPI_ACCESS_MAC_ROM_EN;
spi_write32(SPI_CNTRL0, reg32); spi_write32(SPI_CNTRL0, reg32);