soc/amd/common/block/spi/fch_spi_ctrl: Fix restricted command write
The SPI_RESTRICTED_CMD register is not a PCI configuration register. It is memory mapped from the SPI bar. Verified against PPR 55570 rev 3.16, PPR 56569 rev 3.03, and PPR 57243 rev 1.50 TEST=Compile tested only Change-Id: I7c88aaea9ddac200644bb368be3bd4e9be47fd7b Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63305 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -282,7 +282,7 @@ static int fch_spi_flash_protect(const struct spi_flash *flash, const struct reg
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}
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/* Final steps to protect region */
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pci_write_config32(SOC_LPC_DEV, SPI_RESTRICTED_CMD1, reg32);
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spi_write32(SPI_RESTRICTED_CMD1, reg32);
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reg32 = spi_read32(SPI_CNTRL0);
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reg32 &= ~SPI_ACCESS_MAC_ROM_EN;
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spi_write32(SPI_CNTRL0, reg32);
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